From: Krzysztof Kozlowski <krzk@kernel.org>
To: peter.griffin@linaro.org, s.nawrocki@samsung.com,
cw00.choi@samsung.com, mturquette@baylibre.com,
sboyd@kernel.org, Kuan-Wei Chiu <visitorckw@gmail.com>
Cc: andre.draszik@linaro.org, tudor.ambarus@linaro.org,
alim.akhtar@samsung.com, semen.protsenko@linaro.org,
wllee@google.com, hsuanting@google.com, marscheng@google.com,
jserv@ccns.ncku.edu.tw, linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, visitorckw@google.com,
Yu-Chun Lin <eleanor.lin@realtek.com>
Subject: Re: [PATCH] clk: samsung: gs101: Fix missing USI7_USI DIV clock in peric0_clk_regs
Date: Thu, 14 May 2026 18:56:39 +0200 [thread overview]
Message-ID: <177877779906.167822.16215877297807645211.b4-ty@b4> (raw)
In-Reply-To: <20260505171457.1960837-1-visitorckw@gmail.com>
On Tue, 05 May 2026 17:14:57 +0000, Kuan-Wei Chiu wrote:
> In the peric0_clk_regs array, the divider register offset for USI6 was
> accidentally listed twice, while the divider for USI7 was omitted.
>
> Missing this DIV register causes the USI7 clock divider setting to be
> lost and reset to its hardware default value during a suspend/resume
> cycle.
>
> [...]
Applied, thanks!
[1/1] clk: samsung: gs101: Fix missing USI7_USI DIV clock in peric0_clk_regs
https://git.kernel.org/krzk/linux/c/78ee734b36284d82454e87a92094fdb926985b47
Best regards,
--
Krzysztof Kozlowski <krzk@kernel.org>
prev parent reply other threads:[~2026-05-14 16:56 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-05 17:14 [PATCH] clk: samsung: gs101: Fix missing USI7_USI DIV clock in peric0_clk_regs Kuan-Wei Chiu
2026-05-06 11:54 ` Tudor Ambarus
2026-05-07 10:53 ` Peter Griffin
2026-05-14 16:56 ` Krzysztof Kozlowski [this message]
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