From: Pritam Manohar Sutar <pritam.sutar@samsung.com>
To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
alim.akhtar@samsung.com
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
rosa.pila@samsung.com, dev.tailor@samsung.com,
faraz.ata@samsung.com, muhammed.ali@samsung.com,
selvarasu.g@samsung.com, pritam.sutar@samsung.com
Subject: [PATCH 1/3] arm64: dts: exynos: ExynosAutov920: Add USB and USB-phy nodes
Date: Fri, 24 Oct 2025 17:18:43 +0530 [thread overview]
Message-ID: <20251024114845.2395166-2-pritam.sutar@samsung.com> (raw)
In-Reply-To: <20251024114845.2395166-1-pritam.sutar@samsung.com>
Add USB and USB PHY controller nodes.
Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
---
.../arm64/boot/dts/exynos/exynosautov920.dtsi | 162 ++++++++++++++++++
1 file changed, 162 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index 6ee74d260776..6ff0e00fd901 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -1409,6 +1409,168 @@ pinctrl_hsi1: pinctrl@16450000 {
interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
};
+ usbdrd31_ssphy: phy@16480000 {
+ compatible = "samsung,exynosautov920-usb31drd-combo-ssphy";
+ reg = <0x16480000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ usbdrd31_hsphy: phy@16490000 {
+ compatible = "samsung,exynosautov920-usbdrd-combo-hsphy";
+ reg = <0x16490000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ usbdrd20_phy0: phy@16500000 {
+ compatible = "samsung,exynosautov920-usbdrd-phy";
+ reg = <0x16500000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ usbdrd20_phy1: phy@16510000 {
+ compatible = "samsung,exynosautov920-usbdrd-phy";
+ reg = <0x16510000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ usbdrd20_phy2: phy@16520000 {
+ compatible = "samsung,exynosautov920-usbdrd-phy";
+ reg = <0x16520000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ /* This usb port supports usb31 and usb20 speeds */
+ usbdrd31: usb@16600000 {
+ compatible = "samsung,exynosautov920-dwusb3";
+ ranges = <0x0 0x16600000 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usbdrd31_dwc3: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ interrupts = <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd31_hsphy 0>, <&usbdrd31_ssphy 0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ snps,has-lpm-erratum;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
+ /* This usb port supports only usb20 speeds */
+ usbdrd20_0: usb@16700000 {
+ compatible = "samsung,exynosautov920-dwusb3";
+ ranges = <0x0 0x16700000 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usbdrd20_dwc3_0: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd20_phy0 0>;
+ phy-names = "usb2-phy";
+ snps,has-lpm-erratum;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ };
+ };
+
+ /* This usb port supports only usb20 speeds */
+ usbdrd20_1: usb@16800000 {
+ compatible = "samsung,exynosautov920-dwusb3";
+ ranges = <0x0 0x16800000 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usbdrd20_dwc3_1: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd20_phy1 0>;
+ phy-names = "usb2-phy";
+ snps,has-lpm-erratum;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ };
+ };
+
+ /* This usb port supports only usb20 speeds */
+ usbdrd20_2: usb@16900000 {
+ compatible = "samsung,exynosautov920-dwusb3";
+ ranges = <0x0 0x16900000 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usbdrd20_dwc3_2: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ interrupts = <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd20_phy2 0>;
+ phy-names = "usb2-phy";
+ snps,has-lpm-erratum;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ };
+ };
+
cmu_hsi2: clock-controller@16b00000 {
compatible = "samsung,exynosautov920-cmu-hsi2";
reg = <0x16b00000 0x8000>;
--
2.34.1
next prev parent reply other threads:[~2025-10-24 11:40 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20251024114018epcas5p4e09ca8ea47ff2295a08a162864a47284@epcas5p4.samsung.com>
2025-10-24 11:48 ` [PATCH 0/3] Add and enable USB nodes for ExynosAutov920 SoC Pritam Manohar Sutar
2025-10-24 11:48 ` Pritam Manohar Sutar [this message]
2025-10-24 11:48 ` [PATCH 2/3] arm64: dts: exynos: ExynosAutov920: Add regulators for the USB Pritam Manohar Sutar
2025-10-24 11:48 ` [PATCH 3/3] arm64: dts: exynos: ExynosAutov920: Enable USB nodes Pritam Manohar Sutar
2026-01-22 10:31 ` [PATCH 0/3] Add and enable USB nodes for ExynosAutov920 SoC Pritam Manohar Sutar
2026-01-22 10:40 ` Krzysztof Kozlowski
2026-01-22 12:57 ` Pritam Manohar Sutar
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