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From: Sanghoon Bae <sh86.bae@samsung.com>
To: robh@kernel.org, krzk@kernel.org, conor+dt@kernel.org,
	vkoul@kernel.org, alim.akhtar@samsung.com, kishon@kernel.org
Cc: krzk+dt@kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
	sowon.na@samsung.com, Sanghoon Bae <sh86.bae@samsung.com>
Subject: [PATCH 0/1] Add ExynosAutov920 hsi0 support to exynos-sysreg
Date: Mon, 17 Nov 2025 17:51:32 +0900	[thread overview]
Message-ID: <20251117085134.289371-1-sh86.bae@samsung.com> (raw)
In-Reply-To: CGME20251117085144epcas2p25da059e85e91568711fb1232487159e0@epcas2p2.samsung.com

The ExynosAutov920 SoC includes a PCIe IP and a hsi0 register block that
is mapped in the exynos-sysreg.

To manage PCIe PHY power, configure the PCIe PLL, and set the device direction,
the hsi0 registers need to be defined in exynos-sysreg.

This patch must be applied before the ExynosAutov920 PCIe PHY is enabled.

Sanghoon Bae (1):
  dt-bindings: soc: samsung: exynos-sysreg: add hsi0 for ExynosAutov920

 .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml   | 1 +
 1 file changed, 1 insertion(+)

-- 
2.45.2


       reply	other threads:[~2025-11-17  8:51 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20251117085144epcas2p25da059e85e91568711fb1232487159e0@epcas2p2.samsung.com>
2025-11-17  8:51 ` Sanghoon Bae [this message]
2025-11-17  8:51   ` [PATCH 1/1] dt-bindings: soc: samsung: exynos-sysreg: add hsi0 for ExynosAutov920 Sanghoon Bae
2025-11-17  9:23     ` Krzysztof Kozlowski
2026-02-12  8:16       ` Sanghoon Bae
2025-11-17  8:51   ` [PATCH 0/1] Add ExynosAutov920 hsi0 support to exynos-sysreg Sanghoon Bae

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