From: Anup Patel <apatel@ventanamicro.com>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>,
Conor Dooley <conor@kernel.org>,
linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 2/5] RISC-V: Add SBI debug console helper routines
Date: Thu, 23 Nov 2023 16:17:02 +0530 [thread overview]
Message-ID: <CAK9=C2X-cOxjJ-fBLrcvWvP+K8fD=PGucmrWN+m1ZK3j7ae_zg@mail.gmail.com> (raw)
In-Reply-To: <20231120-639982716fbfd33a6fc144d6@orel>
On Mon, Nov 20, 2023 at 1:35 PM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Sat, Nov 18, 2023 at 09:08:56AM +0530, Anup Patel wrote:
> > Let us provide SBI debug console helper routines which can be
> > shared by serial/earlycon-riscv-sbi.c and hvc/hvc_riscv_sbi.c.
> >
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > ---
> > arch/riscv/include/asm/sbi.h | 5 +++++
> > arch/riscv/kernel/sbi.c | 43 ++++++++++++++++++++++++++++++++++++
> > 2 files changed, 48 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> > index 66f3933c14f6..ee7aef5f6233 100644
> > --- a/arch/riscv/include/asm/sbi.h
> > +++ b/arch/riscv/include/asm/sbi.h
> > @@ -334,6 +334,11 @@ static inline unsigned long sbi_mk_version(unsigned long major,
> > }
> >
> > int sbi_err_map_linux_errno(int err);
> > +
> > +extern bool sbi_debug_console_available;
> > +int sbi_debug_console_write(unsigned int num_bytes, phys_addr_t base_addr);
> > +int sbi_debug_console_read(unsigned int num_bytes, phys_addr_t base_addr);
> > +
> > #else /* CONFIG_RISCV_SBI */
> > static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1; }
> > static inline void sbi_init(void) {}
> > diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> > index 5a62ed1da453..73a9c22c3945 100644
> > --- a/arch/riscv/kernel/sbi.c
> > +++ b/arch/riscv/kernel/sbi.c
> > @@ -571,6 +571,44 @@ long sbi_get_mimpid(void)
> > }
> > EXPORT_SYMBOL_GPL(sbi_get_mimpid);
> >
> > +bool sbi_debug_console_available;
> > +
> > +int sbi_debug_console_write(unsigned int num_bytes, phys_addr_t base_addr)
> > +{
> > + struct sbiret ret;
> > +
> > + if (!sbi_debug_console_available)
> > + return -EOPNOTSUPP;
> > +
> > + if (IS_ENABLED(CONFIG_32BIT))
> > + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE,
> > + num_bytes, lower_32_bits(base_addr),
> > + upper_32_bits(base_addr), 0, 0, 0);
> > + else
> > + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE,
> > + num_bytes, base_addr, 0, 0, 0, 0);
> > +
> > + return ret.error ? sbi_err_map_linux_errno(ret.error) : ret.value;
>
> We can't get perfect mappings, but I wonder if we can do better than
> returning ENOTSUPP for "Failed to write the byte due to I/O errors."
>
> How about
>
> if (ret.error == SBI_ERR_FAILURE)
> return -EIO;
>
> return ret.error ? sbi_err_map_linux_errno(ret.error) : ret.value;
Seems overkill but I will update anyway.
>
>
> > +}
> > +
> > +int sbi_debug_console_read(unsigned int num_bytes, phys_addr_t base_addr)
> > +{
> > + struct sbiret ret;
> > +
> > + if (!sbi_debug_console_available)
> > + return -EOPNOTSUPP;
> > +
> > + if (IS_ENABLED(CONFIG_32BIT))
> > + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ,
> > + num_bytes, lower_32_bits(base_addr),
> > + upper_32_bits(base_addr), 0, 0, 0);
> > + else
> > + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ,
> > + num_bytes, base_addr, 0, 0, 0, 0);
> > +
> > + return ret.error ? sbi_err_map_linux_errno(ret.error) : ret.value;
>
> Same comment as above.
Okay.
>
> > +}
> > +
> > void __init sbi_init(void)
> > {
> > int ret;
> > @@ -612,6 +650,11 @@ void __init sbi_init(void)
> > sbi_srst_reboot_nb.priority = 192;
> > register_restart_handler(&sbi_srst_reboot_nb);
> > }
> > + if ((sbi_spec_version >= sbi_mk_version(2, 0)) &&
> > + (sbi_probe_extension(SBI_EXT_DBCN) > 0)) {
> > + pr_info("SBI DBCN extension detected\n");
> > + sbi_debug_console_available = true;
> > + }
> > } else {
> > __sbi_set_timer = __sbi_set_timer_v01;
> > __sbi_send_ipi = __sbi_send_ipi_v01;
> > --
> > 2.34.1
> >
>
> Otherwise,
>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>
> Thanks,
> drew
Regards,
Anup
next prev parent reply other threads:[~2023-11-23 10:47 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-18 3:38 [PATCH v4 0/5] RISC-V SBI debug console extension support Anup Patel
2023-11-18 3:38 ` [PATCH v4 1/5] RISC-V: Add stubs for sbi_console_putchar/getchar() Anup Patel
2023-11-21 22:36 ` Samuel Holland
2023-11-23 10:38 ` Anup Patel
2023-11-23 14:45 ` Samuel Holland
2023-11-18 3:38 ` [PATCH v4 2/5] RISC-V: Add SBI debug console helper routines Anup Patel
2023-11-20 8:05 ` Andrew Jones
2023-11-23 10:47 ` Anup Patel [this message]
2023-11-21 22:45 ` Samuel Holland
2023-11-23 10:44 ` Anup Patel
2023-11-18 3:38 ` [PATCH v4 3/5] tty/serial: Add RISC-V SBI debug console based earlycon Anup Patel
2023-11-21 22:41 ` Samuel Holland
2023-11-23 10:43 ` Anup Patel
2023-11-18 3:38 ` [PATCH v4 4/5] tty: Add SBI debug console support to HVC SBI driver Anup Patel
2023-11-20 7:16 ` Jiri Slaby
2023-11-21 8:21 ` Atish Kumar Patra
2023-11-18 3:38 ` [PATCH v4 5/5] RISC-V: Enable SBI based earlycon support Anup Patel
2023-11-21 22:48 ` Samuel Holland
2023-11-23 10:39 ` Anup Patel
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