From: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
To: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
<linux-riscv@lists.infradead.org>, <linux-spi@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
<valentina.fernandezalanis@microchip.com>,
Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Subject: [PATCH 1/3] spi: spi-microchip-core: Add support for GPIO based CS
Date: Thu, 2 May 2024 15:34:08 +0100 [thread overview]
Message-ID: <20240502143410.12629-2-prajna.rajendrakumar@microchip.com> (raw)
In-Reply-To: <20240502143410.12629-1-prajna.rajendrakumar@microchip.com>
The SPI controller within the PolarFire SoC is capable of handling
multiple CS, but only one CS line is wired in the MSS. Therefore,
use GPIO descriptors to configure additional CS lines.
Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
---
drivers/spi/spi-microchip-core.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/spi/spi-microchip-core.c b/drivers/spi/spi-microchip-core.c
index 634364c7cfe6..71886c27bca3 100644
--- a/drivers/spi/spi-microchip-core.c
+++ b/drivers/spi/spi-microchip-core.c
@@ -258,6 +258,9 @@ static int mchp_corespi_setup(struct spi_device *spi)
struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller);
u32 reg;
+ if (spi->cs_gpiod)
+ return 0;
+
/*
* Active high targets need to be specifically set to their inactive
* states during probe by adding them to the "control group" & thus
@@ -516,6 +519,7 @@ static int mchp_corespi_probe(struct platform_device *pdev)
host->num_chipselect = num_cs;
host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
+ host->use_gpio_descriptors = true;
host->setup = mchp_corespi_setup;
host->bits_per_word_mask = SPI_BPW_MASK(8);
host->transfer_one = mchp_corespi_transfer_one;
--
2.25.1
next prev parent reply other threads:[~2024-05-02 14:34 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-02 14:34 [PATCH 0/3] Add support for GPIO based CS Prajna Rajendra Kumar
2024-05-02 14:34 ` Prajna Rajendra Kumar [this message]
2024-05-02 15:54 ` [PATCH 1/3] spi: spi-microchip-core: " Conor Dooley
2024-05-03 5:27 ` kernel test robot
2024-05-03 5:37 ` kernel test robot
2024-05-02 14:34 ` [PATCH 2/3] spi: dt-bindings: Add num-cs property for mpfs-spi Prajna Rajendra Kumar
2024-05-02 14:53 ` Krzysztof Kozlowski
2024-05-03 12:54 ` Prajna.Rajendrakumar
2024-05-03 14:46 ` Krzysztof Kozlowski
2024-05-03 16:11 ` Conor Dooley
2024-05-07 7:57 ` Prajna.Rajendrakumar
2024-05-03 10:40 ` Conor Dooley
2024-05-02 14:34 ` [PATCH 3/3] spi: spi-microchip-core: Fix the number of chip selects supported Prajna Rajendra Kumar
2024-05-02 15:47 ` Conor Dooley
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