From: Andy Shevchenko <andriy.shevchenko@intel.com>
To: Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: Mark Brown <broonie@kernel.org>,
linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org
Subject: Re: [PATCH v3 REBASED] spi: Add capability to perform some transfer with chipselect off
Date: Tue, 7 May 2024 19:24:45 +0300 [thread overview]
Message-ID: <ZjpVzexVvyih2vGG@smile.fi.intel.com> (raw)
In-Reply-To: <20220907141344.oDJgraej0r_TWCpXPzNZwflzEvN3hBXTvsBehJGtLSY@z>
On Wed, Sep 07, 2022 at 04:13:44PM +0200, Christophe Leroy wrote:
> Some components require a few clock cycles with chipselect off before
> or/and after the data transfer done with CS on.
>
> Typically IDT 801034 QUAD PCM CODEC datasheet states "Note *: CCLK
> should have one cycle before CS goes low, and two cycles after
> CS goes high".
>
> The cycles "before" are implicitely provided by all previous activity
> on the SPI bus. But the cycles "after" must be provided in order to
> terminate the SPI transfer.
>
> In order to use that kind of component, add a cs_off flag to
> spi_transfer struct. When this flag is set, the transfer is performed
> with chipselect off. This allows consummer to add a dummy transfer
> at the end of the transfer list which is performed with chipselect
> OFF, providing the required additional clock cycles.
Interesting. Wondering if this helps to improve mmc-spi.c case, which
abuses SPI protocol on the initialisation phase.
P.S> just noticed this change in the Git history of spi.c changes :-)
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2024-05-07 16:24 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-07 14:11 [PATCH v3 REBASED] spi: Add capability to perform some transfer with chipselect off Christophe Leroy
2022-09-07 14:13 ` Christophe Leroy
2024-05-07 16:24 ` Andy Shevchenko [this message]
2022-09-07 15:12 ` Mark Brown
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