From: Krishna Yarlagadda <kyarlagadda@nvidia.com>
To: <linux-tegra@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-doc@vger.kernel.org>, <linux-i2c@vger.kernel.org>,
<linux-mmc@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<corbet@lwn.net>, <andi.shyti@kernel.org>,
<wsa+renesas@sang-engineering.com>, <ulf.hansson@linaro.org>,
<adrian.hunter@intel.com>, <digetx@gmail.com>,
<ldewangan@nvidia.com>, <kyarlagadda@nvidia.com>,
<mkumard@nvidia.com>
Subject: [RFC PATCH 06/11] i2c: tegra: split clock initialization code
Date: Tue, 7 May 2024 04:21:34 +0530 [thread overview]
Message-ID: <20240506225139.57647-7-kyarlagadda@nvidia.com> (raw)
In-Reply-To: <20240506225139.57647-1-kyarlagadda@nvidia.com>
Add new methods for setting clock parameters and setting
clock divisor.
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
---
drivers/i2c/busses/i2c-tegra.c | 127 ++++++++++++++++++++-------------
1 file changed, 77 insertions(+), 50 deletions(-)
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 85b31edc558d..b3dc2603db35 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -604,12 +604,83 @@ static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
return 0;
}
+static void tegra_i2c_set_clk_params(struct tegra_i2c_dev *i2c_dev)
+{
+ u32 val, clk_divisor, tsu_thd, tlow, thigh, non_hs_mode;
+
+ switch (i2c_dev->timings.bus_freq_hz) {
+ case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ:
+ default:
+ tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
+ thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
+ tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
+
+ if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_FREQ)
+ non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
+ else
+ non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
+ break;
+
+ case 0 ... I2C_MAX_STANDARD_MODE_FREQ:
+ tlow = i2c_dev->hw->tlow_std_mode;
+ thigh = i2c_dev->hw->thigh_std_mode;
+ tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
+ non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
+ break;
+ }
+
+ /* make sure clock divisor programmed correctly */
+ clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
+ i2c_dev->hw->clk_divisor_hs_mode) |
+ FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode);
+ i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
+
+ if (i2c_dev->hw->has_interface_timing_reg) {
+ val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
+ FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
+ i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
+ }
+
+ /*
+ * Configure setup and hold times only when tsu_thd is non-zero.
+ * Otherwise, preserve the chip default values.
+ */
+ if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
+ i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
+}
+
+static int tegra_i2c_set_div_clk(struct tegra_i2c_dev *i2c_dev)
+{
+ u32 clk_multiplier, tlow, thigh, non_hs_mode;
+ u32 timing, clk_divisor;
+ int err;
+
+ timing = i2c_readl(i2c_dev, I2C_INTERFACE_TIMING_0);
+
+ tlow = FIELD_GET(I2C_INTERFACE_TIMING_TLOW, timing);
+ thigh = FIELD_GET(I2C_INTERFACE_TIMING_THIGH, timing);
+
+ clk_divisor = i2c_readl(i2c_dev, I2C_CLK_DIVISOR);
+
+ non_hs_mode = FIELD_GET(I2C_CLK_DIVISOR_STD_FAST_MODE, clk_divisor);
+
+ clk_multiplier = (thigh + tlow + 2) * (non_hs_mode + 1);
+
+ err = clk_set_rate(i2c_dev->div_clk,
+ i2c_dev->timings.bus_freq_hz * clk_multiplier);
+ if (err) {
+ dev_err(i2c_dev->dev, "failed to set div_clk rate: %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
{
- u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode;
+ u32 val;
+ int err;
acpi_handle handle = ACPI_HANDLE(i2c_dev->dev);
- struct i2c_timings *t = &i2c_dev->timings;
- int err;
/*
* The reset shouldn't ever fail in practice. The failure will be a
@@ -641,54 +712,10 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
if (IS_VI(i2c_dev))
tegra_i2c_vi_init(i2c_dev);
- switch (t->bus_freq_hz) {
- case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ:
- default:
- tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
- thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
- tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
-
- if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ)
- non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
- else
- non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
- break;
-
- case 0 ... I2C_MAX_STANDARD_MODE_FREQ:
- tlow = i2c_dev->hw->tlow_std_mode;
- thigh = i2c_dev->hw->thigh_std_mode;
- tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
- non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
- break;
- }
-
- /* make sure clock divisor programmed correctly */
- clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
- i2c_dev->hw->clk_divisor_hs_mode) |
- FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode);
- i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
-
- if (i2c_dev->hw->has_interface_timing_reg) {
- val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
- FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
- i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
- }
-
- /*
- * Configure setup and hold times only when tsu_thd is non-zero.
- * Otherwise, preserve the chip default values.
- */
- if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
- i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
-
- clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1);
-
- err = clk_set_rate(i2c_dev->div_clk,
- t->bus_freq_hz * clk_multiplier);
- if (err) {
- dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err);
+ tegra_i2c_set_clk_params(i2c_dev);
+ err = tegra_i2c_set_div_clk(i2c_dev);
+ if (err)
return err;
- }
if (!IS_DVC(i2c_dev) && !IS_VI(i2c_dev)) {
u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
--
2.43.2
next prev parent reply other threads:[~2024-05-06 22:53 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-06 22:51 [RFC PATCH 00/11] Introduce Tegra register config settings Krishna Yarlagadda
2024-05-06 22:51 ` [RFC PATCH 01/11] Documentation: Introduce config settings framework Krishna Yarlagadda
2024-05-06 22:51 ` [RFC PATCH 02/11] soc: tegra: Add config setting framework Krishna Yarlagadda
2024-05-06 22:51 ` [RFC PATCH 03/11] soc: tegra: config settings binding document Krishna Yarlagadda
2024-05-07 6:32 ` Krzysztof Kozlowski
2024-05-24 8:01 ` Thierry Reding
2024-05-06 22:51 ` [RFC PATCH 04/11] i2c: dt-bindings: configuration settings Krishna Yarlagadda
2024-05-07 6:34 ` Krzysztof Kozlowski
2024-05-07 12:35 ` Rob Herring (Arm)
2024-05-06 22:51 ` [RFC PATCH 05/11] i2c: core: Avoid config node enumeration Krishna Yarlagadda
2024-05-07 6:35 ` Krzysztof Kozlowski
2024-05-06 22:51 ` Krishna Yarlagadda [this message]
2024-05-06 22:51 ` [RFC PATCH 07/11] i2c: tegra: config settings for interface timings Krishna Yarlagadda
2024-05-06 22:51 ` [RFC PATCH 08/11] arm64: tegra: I2C " Krishna Yarlagadda
2024-05-06 22:51 ` [RFC PATCH 09/11] sdhci: dt-bindings: configuration settings Krishna Yarlagadda
2024-05-07 6:37 ` Krzysztof Kozlowski
2024-05-06 22:51 ` [RFC PATCH 10/11] mmc: host: tegra: config settings for timing Krishna Yarlagadda
2024-05-06 22:51 ` [RFC PATCH 11/11] arm64: tegra: SDHCI timing settings Krishna Yarlagadda
2024-05-07 6:38 ` [RFC PATCH 00/11] Introduce Tegra register config settings Krzysztof Kozlowski
2024-05-24 7:52 ` Thierry Reding
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240506225139.57647-7-kyarlagadda@nvidia.com \
--to=kyarlagadda@nvidia.com \
--cc=adrian.hunter@intel.com \
--cc=andi.shyti@kernel.org \
--cc=conor+dt@kernel.org \
--cc=corbet@lwn.net \
--cc=devicetree@vger.kernel.org \
--cc=digetx@gmail.com \
--cc=jonathanh@nvidia.com \
--cc=krzk+dt@kernel.org \
--cc=ldewangan@nvidia.com \
--cc=linux-doc@vger.kernel.org \
--cc=linux-i2c@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mmc@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=mkumard@nvidia.com \
--cc=robh@kernel.org \
--cc=thierry.reding@gmail.com \
--cc=ulf.hansson@linaro.org \
--cc=wsa+renesas@sang-engineering.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).