* [PATCH 0/6] Add LS1043A SoC support
@ 2015-09-21 12:22 Zhiqiang Hou
2015-09-21 12:22 ` [PATCH 1/6] i2c: Add i2c support to Freescale Layerscape platforms Zhiqiang Hou
` (5 more replies)
0 siblings, 6 replies; 22+ messages in thread
From: Zhiqiang Hou @ 2015-09-21 12:22 UTC (permalink / raw
To: linux-arm-kernel, catalin.marinas, will.deacon, linux-i2c,
linux-watchdog, linux-doc, linux-clk
Cc: wsa, wim, corbet, mturquette, sboyd, Mingkai.Hu, Shaohui.Xie,
Wenbin.Song, scottwood, bhupesh.sharma, leoli
This patchest adds support for Freescale's LS1043A SoC which is
based on ARMv8 architecture.
Some pending patches are depended on:
1. The LS1043A is belong to Freescale's ARMv8 Layerscape SoC family,
so depends on the updating ARCH kconfig patch.
https://patchwork.kernel.org/patch/7120101/
2. The LS1043A use the new clockgen binding updated by Scott Wood,
depends on the patchset:
https://patchwork.kernel.org/patch/7225421/
https://patchwork.kernel.org/patch/7225461/
https://patchwork.kernel.org/patch/7225431/
https://patchwork.kernel.org/patch/7225441/
https://patchwork.kernel.org/patch/7225451/
[PATCH 1/6] i2c: Add i2c support to Freescale Layerscape platforms
[PATCH 2/6] watchdog: Add support for Freescale Layerscape platforms
[PATCH 3/6] Documentation: DT: Add entry for FSL LS1043ARDB board
[PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
[PATCH 5/6] clk: qoriq: Add ls1043a support.
[PATCH 6/6] dts/ls1043a: add LS1043ARDB board support
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 1/6] i2c: Add i2c support to Freescale Layerscape platforms
2015-09-21 12:22 [PATCH 0/6] Add LS1043A SoC support Zhiqiang Hou
@ 2015-09-21 12:22 ` Zhiqiang Hou
2015-09-21 12:22 ` [PATCH 2/6] watchdog: Add support for " Zhiqiang Hou
` (4 subsequent siblings)
5 siblings, 0 replies; 22+ messages in thread
From: Zhiqiang Hou @ 2015-09-21 12:22 UTC (permalink / raw
To: linux-arm-kernel, catalin.marinas, will.deacon, linux-i2c,
linux-watchdog, linux-doc, linux-clk
Cc: wsa, wim, corbet, mturquette, sboyd, Mingkai.Hu, Shaohui.Xie,
Wenbin.Song, scottwood, bhupesh.sharma, leoli, Hou Zhiqiang
From: Shaohui Xie <Shaohui.Xie@freescale.com>
Modify the I2C_IMX config to support to Layerscape platforms.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Wenbin Song <Wenbin.Song@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
---
drivers/i2c/busses/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 08b8617..14147ec 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -582,10 +582,10 @@ config I2C_IMG
config I2C_IMX
tristate "IMX I2C interface"
- depends on ARCH_MXC
+ depends on ARCH_MXC || ARCH_LAYERSCAPE
help
Say Y here if you want to use the IIC bus controller on
- the Freescale i.MX/MXC processors.
+ the Freescale i.MX/MXC or Layerscape processors.
This driver can also be built as a module. If so, the module
will be called i2c-imx.
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 2/6] watchdog: Add support for Freescale Layerscape platforms
2015-09-21 12:22 [PATCH 0/6] Add LS1043A SoC support Zhiqiang Hou
2015-09-21 12:22 ` [PATCH 1/6] i2c: Add i2c support to Freescale Layerscape platforms Zhiqiang Hou
@ 2015-09-21 12:22 ` Zhiqiang Hou
2015-09-21 15:04 ` Guenter Roeck
2015-09-21 12:22 ` [PATCH 3/6] Documentation: DT: Add entry for FSL LS1043ARDB board Zhiqiang Hou
` (3 subsequent siblings)
5 siblings, 1 reply; 22+ messages in thread
From: Zhiqiang Hou @ 2015-09-21 12:22 UTC (permalink / raw
To: linux-arm-kernel, catalin.marinas, will.deacon, linux-i2c,
linux-watchdog, linux-doc, linux-clk
Cc: wsa, wim, corbet, mturquette, sboyd, Mingkai.Hu, Shaohui.Xie,
Wenbin.Song, scottwood, bhupesh.sharma, leoli, Hou Zhiqiang
From: Shaohui Xie <Shaohui.Xie@freescale.com>
Modify watchdog/Kconfig file to support Layerscape platforms.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Wenbin Song <Wenbin.Song@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
---
drivers/watchdog/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index c68edc1..2862219 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -446,7 +446,7 @@ config MAX63XX_WATCHDOG
config IMX2_WDT
tristate "IMX2+ Watchdog"
- depends on ARCH_MXC
+ depends on ARCH_MXC || ARCH_LAYERSCAPE
select REGMAP_MMIO
select WATCHDOG_CORE
help
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 3/6] Documentation: DT: Add entry for FSL LS1043ARDB board
2015-09-21 12:22 [PATCH 0/6] Add LS1043A SoC support Zhiqiang Hou
2015-09-21 12:22 ` [PATCH 1/6] i2c: Add i2c support to Freescale Layerscape platforms Zhiqiang Hou
2015-09-21 12:22 ` [PATCH 2/6] watchdog: Add support for " Zhiqiang Hou
@ 2015-09-21 12:22 ` Zhiqiang Hou
2015-09-21 12:22 ` [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC Zhiqiang Hou
` (2 subsequent siblings)
5 siblings, 0 replies; 22+ messages in thread
From: Zhiqiang Hou @ 2015-09-21 12:22 UTC (permalink / raw
To: linux-arm-kernel, catalin.marinas, will.deacon, linux-i2c,
linux-watchdog, linux-doc, linux-clk
Cc: wsa, wim, corbet, mturquette, sboyd, Mingkai.Hu, Shaohui.Xie,
Wenbin.Song, scottwood, bhupesh.sharma, leoli, Hou Zhiqiang
From: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
---
Documentation/devicetree/bindings/arm/fsl.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 34c88b0..752a685 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -131,6 +131,10 @@ Example:
Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
----------------------------------------------------------------
+LS1043A ARMv8 based RDB Board
+Required root node properties:
+ - compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
+
LS2080A ARMv8 based Simulator model
Required root node properties:
- compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-21 12:22 [PATCH 0/6] Add LS1043A SoC support Zhiqiang Hou
` (2 preceding siblings ...)
2015-09-21 12:22 ` [PATCH 3/6] Documentation: DT: Add entry for FSL LS1043ARDB board Zhiqiang Hou
@ 2015-09-21 12:22 ` Zhiqiang Hou
2015-09-22 1:24 ` Mark Rutland, marc.zyngier
2015-09-21 12:22 ` [PATCH 5/6] clk: qoriq: Add ls1043a support Zhiqiang Hou
2015-09-21 12:22 ` [PATCH 6/6] dts/ls1043a: add LS1043ARDB board support Zhiqiang Hou
5 siblings, 1 reply; 22+ messages in thread
From: Zhiqiang Hou @ 2015-09-21 12:22 UTC (permalink / raw
To: linux-arm-kernel, catalin.marinas, will.deacon, linux-i2c,
linux-watchdog, linux-doc, linux-clk
Cc: wsa, wim, corbet, mturquette, sboyd, Mingkai.Hu, Shaohui.Xie,
Wenbin.Song, scottwood, bhupesh.sharma, leoli, Hou Zhiqiang
From: Mingkai Hu <Mingkai.Hu@freescale.com>
LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks
similar to LS1021a which complies to Chassis 2.1 spec.
Following levels of DTSI/DTS files have been created for the
LS1043A SoC family:
- fsl-ls1043a.dtsi:
DTS-Include file for FSL LS1043A SoC.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Wenbin Song <Wenbin.Song@freescale.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 501 +++++++++++++++++++++++++
1 file changed, 501 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
new file mode 100644
index 0000000..eca094d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -0,0 +1,501 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright 2014-2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/memreserve/ 0x80000000 0x00010000;
+
+/ {
+ compatible = "fsl,ls1043a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ clocks = <&clockgen 1 0>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0x1>, /* Physical Secure PPI */
+ <1 14 0x1>, /* Physical Non-Secure PPI */
+ <1 11 0x1>, /* Virtual PPI */
+ <1 10 0x1>; /* Hypervisor PPI */
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 106 0x4>,
+ <0 107 0x4>,
+ <0 95 0x4>,
+ <0 97 0x4>;
+ };
+
+ gic: interrupt-controller@1400000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+ <0x0 0x1402000 0 0x1000>, /* GICC */
+ <0x0 0x1404000 0 0x2000>, /* GICH */
+ <0x0 0x1406000 0 0x2000>; /* GICV */
+ interrupts = <1 9 0xf08>;
+ };
+
+ msi1: msi-controller1@1571000 {
+ compatible = "fsl,1s1043a-msi";
+ reg = <0x0 0x1571000 0x0 0x4>,
+ <0x0 0x1571004 0x0 0x4>;
+ reg-names = "msiir", "msir";
+ msi-controller;
+ interrupts = <0 116 0x4>;
+ };
+
+ msi2: msi-controller2@1572000 {
+ compatible = "fsl,1s1043a-msi";
+ reg = <0x0 0x1572000 0x0 0x4>,
+ <0x0 0x1572004 0x0 0x4>;
+ reg-names = "msiir", "msir";
+ msi-controller;
+ interrupts = <0 126 0x4>;
+ };
+
+ msi3: msi-controller3@1573000 {
+ compatible = "fsl,1s1043a-msi";
+ reg = <0x0 0x1573000 0x0 0x4>,
+ <0x0 0x1573004 0x0 0x4>;
+ reg-names = "msiir", "msir";
+ msi-controller;
+ interrupts = <0 160 0x4>;
+ };
+
+ ifc: ifc@1530000 {
+ compatible = "fsl,ifc", "simple-bus";
+ reg = <0x0 0x1530000 0x0 0x10000>;
+ interrupts = <0 43 0x4>;
+ };
+
+ esdhc: esdhc@1560000 {
+ compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
+ reg = <0x0 0x1560000 0x0 0x10000>;
+ interrupts = <0 62 0x4>;
+ clock-frequency = <0>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ big-endian;
+ bus-width = <4>;
+ };
+
+ scfg: scfg@1570000 {
+ compatible = "fsl,ls1043a-scfg", "syscon";
+ reg = <0x0 0x1570000 0x0 0x10000>;
+ big-endian;
+ };
+
+ dcfg: dcfg@1ee0000 {
+ compatible = "fsl,ls1043a-dcfg", "syscon";
+ reg = <0x0 0x1ee0000 0x0 0x10000>;
+ };
+
+ clockgen: clocking@1ee1000 {
+ compatible = "fsl,ls1043a-clockgen";
+ reg = <0x0 0x1ee1000 0x0 0x1000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+ };
+
+ dspi0: dspi@2100000 {
+ compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <0 64 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ spi-num-chipselects = <5>;
+ big-endian;
+ status = "disabled";
+ };
+
+ dspi1: dspi@2110000 {
+ compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2110000 0x0 0x10000>;
+ interrupts = <0 65 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ spi-num-chipselects = <5>;
+ big-endian;
+ status = "disabled";
+ };
+
+ i2c0: i2c@2180000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <0 56 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ dmas = <&edma0 1 39>,
+ <&edma0 1 38>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c1: i2c@2190000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <0 57 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@21a0000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21a0000 0x0 0x10000>;
+ interrupts = <0 58 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@21b0000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21b0000 0x0 0x10000>;
+ interrupts = <0 59 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ duart0: serial@21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0500 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart1: serial@21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0600 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart2: serial@21d0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0500 0x0 0x100>;
+ interrupts = <0 55 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart3: serial@21d0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0600 0x0 0x100>;
+ interrupts = <0 55 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ gpio1: gpio@2300000 {
+ compatible = "fsl,ls1043a-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 66 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2310000 {
+ compatible = "fsl,ls1043a-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 67 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2320000 {
+ compatible = "fsl,ls1043a-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <0 68 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@2330000 {
+ compatible = "fsl,ls1043a-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <0 134 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ lpuart0: serial@2950000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2950000 0x0 0x1000>;
+ interrupts = <0 48 0x4>;
+ clocks = <&clockgen 0 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart1: serial@2960000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2960000 0x0 0x1000>;
+ interrupts = <0 49 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart2: serial@2970000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2970000 0x0 0x1000>;
+ interrupts = <0 50 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart3: serial@2980000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2980000 0x0 0x1000>;
+ interrupts = <0 51 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart4: serial@2990000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2990000 0x0 0x1000>;
+ interrupts = <0 52 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart5: serial@29a0000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x29a0000 0x0 0x1000>;
+ interrupts = <0 53 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ wdog0: wdog@2ad0000 {
+ compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
+ reg = <0x0 0x2ad0000 0x0 0x10000>;
+ interrupts = <0 83 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "wdog";
+ big-endian;
+ };
+
+ edma0: edma@2c00000 {
+ #dma-cells = <2>;
+ compatible = "fsl,vf610-edma";
+ reg = <0x0 0x2c00000 0x0 0x10000>,
+ <0x0 0x2c10000 0x0 0x10000>,
+ <0x0 0x2c20000 0x0 0x10000>;
+ interrupts = <0 103 0x4>,
+ <0 103 0x4>;
+ interrupt-names = "edma-tx", "edma-err";
+ dma-channels = <32>;
+ big-endian;
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&clockgen 4 0>,
+ <&clockgen 4 0>;
+ };
+
+ usb0: usb3@2f00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x2f00000 0x0 0x10000>;
+ interrupts = <0 60 0x4>;
+ dr_mode = "host";
+ };
+
+ usb1: usb3@3000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3000000 0x0 0x10000>;
+ interrupts = <0 61 0x4>;
+ dr_mode = "host";
+ };
+ usb2: usb3@3100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <0 63 0x4>;
+ dr_mode = "host";
+ };
+
+ pcie@3400000 {
+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 118 0x4>, /* controller interrupt */
+ <0 117 0x4>; /* PME interrupt */
+ interrupt-names = "intr", "pme";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&msi1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
+ <0000 0 0 2 &gic 0 111 0x4>,
+ <0000 0 0 3 &gic 0 112 0x4>,
+ <0000 0 0 4 &gic 0 113 0x4>;
+ };
+
+ pcie@3500000 {
+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
+ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 128 0x4>,
+ <0 127 0x4>;
+ interrupt-names = "intr", "pme";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&msi2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
+ <0000 0 0 2 &gic 0 121 0x4>,
+ <0000 0 0 3 &gic 0 122 0x4>,
+ <0000 0 0 4 &gic 0 123 0x4>;
+ };
+
+ pcie@3600000 {
+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
+ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 162 0x4>,
+ <0 161 0x4>;
+ interrupt-names = "intr", "pme";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&msi3>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
+ <0000 0 0 2 &gic 0 155 0x4>,
+ <0000 0 0 3 &gic 0 156 0x4>,
+ <0000 0 0 4 &gic 0 157 0x4>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0 0x80000000>;
+ /* DRAM space 1 - 2 GB DRAM */
+ };
+
+};
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 5/6] clk: qoriq: Add ls1043a support.
2015-09-21 12:22 [PATCH 0/6] Add LS1043A SoC support Zhiqiang Hou
` (3 preceding siblings ...)
2015-09-21 12:22 ` [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC Zhiqiang Hou
@ 2015-09-21 12:22 ` Zhiqiang Hou
2015-10-01 22:56 ` Stephen Boyd
2015-09-21 12:22 ` [PATCH 6/6] dts/ls1043a: add LS1043ARDB board support Zhiqiang Hou
5 siblings, 1 reply; 22+ messages in thread
From: Zhiqiang Hou @ 2015-09-21 12:22 UTC (permalink / raw
To: linux-arm-kernel, catalin.marinas, will.deacon, linux-i2c,
linux-watchdog, linux-doc, linux-clk
Cc: wsa, wim, corbet, mturquette, sboyd, Mingkai.Hu, Shaohui.Xie,
Wenbin.Song, scottwood, bhupesh.sharma, leoli, Hou Zhiqiang
From: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
---
drivers/clk/clk-qoriq.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 7753fa3..e71927b 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -244,6 +244,28 @@ static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
},
};
+static const struct clockgen_muxinfo ls1043a_hwa1 = {
+ {
+ {},
+ {},
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
+ {},
+ {},
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
+ },
+};
+
+static const struct clockgen_muxinfo ls1043a_hwa2 = {
+ {
+ {},
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
+ {},
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
+ },
+};
+
static const struct clockgen_muxinfo t1023_hwa1 = {
{
{},
@@ -452,6 +474,21 @@ static const struct clockgen_chipinfo chipinfo[] = {
.pll_mask = 0x03,
},
{
+ .compat = "fsl,ls1043a-clockgen",
+ .init_periph = t2080_init_periph,
+ .cmux_groups = {
+ &t1040_cmux
+ },
+ .hwaccel = {
+ &ls1043a_hwa1, &ls1043a_hwa2
+ },
+ .cmux_to_group = {
+ 0, -1
+ },
+ .pll_mask = 0x07,
+ .flags = CG_PLL_8BIT,
+ },
+ {
.compat = "fsl,ls2080a-clockgen",
.cmux_groups = {
&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
@@ -1228,6 +1265,7 @@ err:
CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
/* Legacy nodes */
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 6/6] dts/ls1043a: add LS1043ARDB board support
2015-09-21 12:22 [PATCH 0/6] Add LS1043A SoC support Zhiqiang Hou
` (4 preceding siblings ...)
2015-09-21 12:22 ` [PATCH 5/6] clk: qoriq: Add ls1043a support Zhiqiang Hou
@ 2015-09-21 12:22 ` Zhiqiang Hou
2015-09-21 23:13 ` Scott Wood
5 siblings, 1 reply; 22+ messages in thread
From: Zhiqiang Hou @ 2015-09-21 12:22 UTC (permalink / raw
To: linux-arm-kernel, catalin.marinas, will.deacon, linux-i2c,
linux-watchdog, linux-doc, linux-clk
Cc: wsa, wim, corbet, mturquette, sboyd, Mingkai.Hu, Shaohui.Xie,
Wenbin.Song, scottwood, bhupesh.sharma, leoli, Hou Zhiqiang
From: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Wenbin Song <Wenbin.Song@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
---
arch/arm64/boot/dts/freescale/Makefile | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 116 ++++++++++++++++++++++
2 files changed, 117 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 57b41c7..33b1e57 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -1,4 +1,4 @@
-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb fsl-ls2080a-rdb.dtb fsl-ls2080a-simu.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb fsl-ls2080a-rdb.dtb fsl-ls2080a-simu.dtb fsl-ls1043a-rdb.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
new file mode 100644
index 0000000..d14052c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -0,0 +1,116 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright 2014-2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "fsl-ls1043a.dtsi"
+
+/ {
+ model = "LS1043A RDB Board";
+};
+
+&i2c0 {
+ status = "okay";
+ ina220@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+ adt7461a@4c {
+ compatible = "adi,adt7461";
+ reg = <0x4c>;
+ };
+ eeprom@56 {
+ compatible = "at24,24c512";
+ reg = <0x52>;
+ };
+ eeprom@57 {
+ compatible = "at24,24c512";
+ reg = <0x53>;
+ };
+ rtc@68 {
+ compatible = "pericom,pt7c4338";
+ reg = <0x68>;
+ };
+};
+
+&ifc {
+ status = "okay";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR, NAND Flashes and FPGA on board */
+ ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+ 0x1 0x0 0x0 0x7e800000 0x00010000
+ 0x2 0x0 0x0 0x7fb00000 0x00000100>;
+
+ nor@0,0 {
+ compatible = "cfi-flash";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand@1,0 {
+ compatible = "fsl,ifc-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1 0x0 0x10000>;
+ };
+
+ cpld: board-control@2,0 {
+ compatible = "fsl,ls1043ardb-cpld", "simple-bus";
+ reg = <0x2 0x0 0x0000100>;
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
+ status = "okay";
+};
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 2/6] watchdog: Add support for Freescale Layerscape platforms
2015-09-21 12:22 ` [PATCH 2/6] watchdog: Add support for " Zhiqiang Hou
@ 2015-09-21 15:04 ` Guenter Roeck
0 siblings, 0 replies; 22+ messages in thread
From: Guenter Roeck @ 2015-09-21 15:04 UTC (permalink / raw
To: Zhiqiang Hou, linux-arm-kernel, catalin.marinas, will.deacon,
linux-i2c, linux-watchdog, linux-doc, linux-clk
Cc: wsa, wim, corbet, mturquette, sboyd, Mingkai.Hu, Shaohui.Xie,
Wenbin.Song, scottwood, bhupesh.sharma, leoli
On 09/21/2015 05:22 AM, Zhiqiang Hou wrote:
> From: Shaohui Xie <Shaohui.Xie@freescale.com>
>
> Modify watchdog/Kconfig file to support Layerscape platforms.
>
"Enable IMX2+ watchdog for Layerscape platforms" would be a better
description.
Nitpick, so
Acked-by: Guenter Roeck <linux@roeck-us.net>
> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
> Signed-off-by: Wenbin Song <Wenbin.Song@freescale.com>
> Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
> ---
> drivers/watchdog/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index c68edc1..2862219 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -446,7 +446,7 @@ config MAX63XX_WATCHDOG
>
> config IMX2_WDT
> tristate "IMX2+ Watchdog"
> - depends on ARCH_MXC
> + depends on ARCH_MXC || ARCH_LAYERSCAPE
> select REGMAP_MMIO
> select WATCHDOG_CORE
> help
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 6/6] dts/ls1043a: add LS1043ARDB board support
2015-09-21 12:22 ` [PATCH 6/6] dts/ls1043a: add LS1043ARDB board support Zhiqiang Hou
@ 2015-09-21 23:13 ` Scott Wood
2015-09-22 9:51 ` Hou Zhiqiang
0 siblings, 1 reply; 22+ messages in thread
From: Scott Wood @ 2015-09-21 23:13 UTC (permalink / raw
To: Zhiqiang Hou
Cc: linux-arm-kernel, catalin.marinas, will.deacon, linux-i2c,
linux-watchdog, linux-doc, linux-clk, wsa, wim, corbet,
mturquette, sboyd, Mingkai.Hu, Shaohui.Xie, Wenbin.Song,
bhupesh.sharma, leoli
On Mon, 2015-09-21 at 20:22 +0800, Zhiqiang Hou wrote:
> + cpld: board-control@2,0 {
> + compatible = "fsl,ls1043ardb-cpld", "simple-bus";
> + reg = <0x2 0x0 0x0000100>;
> + };
Again, why "simple-bus"?
-Scott
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-21 12:22 ` [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC Zhiqiang Hou
@ 2015-09-22 1:24 ` Mark Rutland, marc.zyngier
2015-09-22 1:30 ` Scott Wood
2015-09-22 9:50 ` Hou Zhiqiang
0 siblings, 2 replies; 22+ messages in thread
From: Mark Rutland, marc.zyngier @ 2015-09-22 1:24 UTC (permalink / raw
To: Zhiqiang Hou, marc.zyngier
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui.Xie@freescale.com,
corbet@lwn.net, bhupesh.sharma@freescale.com,
mturquette@baylibre.com, wsa@the-dreams.de, sboyd@codeaurora.org,
wim@iguana.be, Wenbin.Song@freescale.com, scottwood@freescale.com,
Mingkai.Hu@freescale.com, leoli@freescale.com
Hi,
> +/memreserve/ 0x80000000 0x00010000;
Why is this necessary?
If this is necessary, please add a comment stating what this is for.
> + cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0 0x3>;
> + clocks = <&clockgen 1 0>;
> + };
Missing enable-method properties on all the secondary CPUs.
[...]
> + gic: interrupt-controller@1400000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
> + <0x0 0x1402000 0 0x1000>, /* GICC */
> + <0x0 0x1404000 0 0x2000>, /* GICH */
> + <0x0 0x1406000 0 0x2000>; /* GICV */
> + interrupts = <1 9 0xf08>;
> + };
These sizes don't look right.
To the best of my knowledge, GICC (and GICV) should be 0x2000 in size, while
GICD and GICH should be 0x1000.
[...]
> + ifc: ifc@1530000 {
> + compatible = "fsl,ifc", "simple-bus";
> + reg = <0x0 0x1530000 0x0 0x10000>;
> + interrupts = <0 43 0x4>;
> + };
Why simple-bus?
> + clockgen: clocking@1ee1000 {
> + compatible = "fsl,ls1043a-clockgen";
> + reg = <0x0 0x1ee1000 0x0 0x1000>;
> + #clock-cells = <2>;
> + clocks = <&sysclk>;
> + sysclk: sysclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + clock-output-names = "sysclk";
> + };
> + };
Why does this fixed clock live under the clockgen? It should live directly
under the root node.
[...]
> + pcie@3400000 {
> + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
> + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> + interrupts = <0 118 0x4>, /* controller interrupt */
> + <0 117 0x4>; /* PME interrupt */
> + interrupt-names = "intr", "pme";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <4>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
> + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + msi-parent = <&msi1>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
> + <0000 0 0 2 &gic 0 111 0x4>,
> + <0000 0 0 3 &gic 0 112 0x4>,
> + <0000 0 0 4 &gic 0 113 0x4>;
> + };
> +
> + pcie@3500000 {
> + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
> + 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> + interrupts = <0 128 0x4>,
> + <0 127 0x4>;
> + interrupt-names = "intr", "pme";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <2>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
> + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + msi-parent = <&msi2>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
> + <0000 0 0 2 &gic 0 121 0x4>,
> + <0000 0 0 3 &gic 0 122 0x4>,
> + <0000 0 0 4 &gic 0 123 0x4>;
> + };
> +
> + pcie@3600000 {
> + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
> + 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> + interrupts = <0 162 0x4>,
> + <0 161 0x4>;
> + interrupt-names = "intr", "pme";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <2>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
> + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + msi-parent = <&msi3>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
> + <0000 0 0 2 &gic 0 155 0x4>,
> + <0000 0 0 3 &gic 0 156 0x4>,
> + <0000 0 0 4 &gic 0 157 0x4>;
> + };
You wait ages for a bus, then three show up at once...
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0 0x80000000>;
> + /* DRAM space 1 - 2 GB DRAM */
I don't understand the comment. This describes 2GB at 2GB.
Does the bootloader overwrite this?
Thanks,
Mark.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-22 1:24 ` Mark Rutland, marc.zyngier
@ 2015-09-22 1:30 ` Scott Wood
2015-09-22 9:50 ` Hou Zhiqiang
1 sibling, 0 replies; 22+ messages in thread
From: Scott Wood @ 2015-09-22 1:30 UTC (permalink / raw
To: Mark Rutland, marc.zyngier
Cc: Zhiqiang Hou, linux-arm-kernel@lists.infradead.org,
Catalin Marinas, Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui.Xie@freescale.com,
corbet@lwn.net, bhupesh.sharma@freescale.com,
mturquette@baylibre.com, wsa@the-dreams.de, sboyd@codeaurora.org,
wim@iguana.be, Wenbin.Song@freescale.com,
Mingkai.Hu@freescale.com, leoli@freescale.com
On Tue, 2015-09-22 at 02:24 +0100, Mark Rutland wrote:
> > + clockgen: clocking@1ee1000{
> > + compatible = "fsl,ls1043a-clockgen";
> > + reg = <0x0 0x1ee1000 0x0 0x1000>;
> > + #clock-cells = <2>;
> > + clocks = <&sysclk>;
> > + sysclk: sysclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + clock-output-names = "sysclk";
> > + };
> > + };
>
> Why does this fixed clock live under the clockgen? It should live directly
> under the root node.
I think this is copy-and-paste from some legacy PPC stuff. There's no reason
anymore to put sysclk under clockgen.
-Scott
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-22 1:24 ` Mark Rutland, marc.zyngier
2015-09-22 1:30 ` Scott Wood
@ 2015-09-22 9:50 ` Hou Zhiqiang
2015-09-22 17:23 ` Li Leo
2015-09-22 22:15 ` Mark Rutland
1 sibling, 2 replies; 22+ messages in thread
From: Hou Zhiqiang @ 2015-09-22 9:50 UTC (permalink / raw
To: Mark Rutland, marc.zyngier@arm.com
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent, Li Leo
Hi Mark,
> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland@arm.com]
> Sent: 2015年9月22日 9:24
> To: Hou Zhiqiang-B48286; marc.zyngier@arm.com
> Cc: linux-arm-kernel@lists.infradead.org; Catalin Marinas; Will Deacon;
> linux-i2c@vger.kernel.org; linux-watchdog@vger.kernel.org; linux-
> doc@vger.kernel.org; linux-clk@vger.kernel.org; Xie Shaohui-B21989;
> corbet@lwn.net; Sharma Bhupesh-B45370; mturquette@baylibre.com; wsa@the-
> dreams.de; sboyd@codeaurora.org; wim@iguana.be; Song Wenbin-B53747; Wood
> Scott-B07421; Hu Mingkai-B21284; Li Yang-Leo-R58472
> Subject: Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
>
> Hi,
>
> > +/memreserve/ 0x80000000 0x00010000;
>
> Why is this necessary?
This memory region is pre-reserved for the spin-table/psci, although didn't add
Enable method of secondary cores.
> If this is necessary, please add a comment stating what this is for.
>
> > + cpu@3 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x0 0x3>;
> > + clocks = <&clockgen 1 0>;
> > + };
>
> Missing enable-method properties on all the secondary CPUs.
>
There are two methods (spin-table and psci) to bring up secondary cores, which one
do you think is better?
> [...]
>
> > + gic: interrupt-controller@1400000 {
> > + compatible = "arm,gic-400";
> > + #interrupt-cells = <3>;
> > + interrupt-controller;
> > + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
> > + <0x0 0x1402000 0 0x1000>, /* GICC */
> > + <0x0 0x1404000 0 0x2000>, /* GICH */
> > + <0x0 0x1406000 0 0x2000>; /* GICV */
> > + interrupts = <1 9 0xf08>;
> > + };
>
> These sizes don't look right.
>
> To the best of my knowledge, GICC (and GICV) should be 0x2000 in size,
> while GICD and GICH should be 0x1000.
Thanks for your correction.
>
> [...]
>
> > + ifc: ifc@1530000 {
> > + compatible = "fsl,ifc", "simple-bus";
> > + reg = <0x0 0x1530000 0x0 0x10000>;
> > + interrupts = <0 43 0x4>;
> > + };
>
> Why simple-bus?
There are 3 child node located in dtsi file that should be created and added
to platform device list.
>
> > + clockgen: clocking@1ee1000 {
> > + compatible = "fsl,ls1043a-clockgen";
> > + reg = <0x0 0x1ee1000 0x0 0x1000>;
> > + #clock-cells = <2>;
> > + clocks = <&sysclk>;
> > + sysclk: sysclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + clock-output-names = "sysclk";
> > + };
> > + };
>
> Why does this fixed clock live under the clockgen? It should live
> directly under the root node.
>
Thanks and will move it out in v2.
> [...]
>
> > + pcie@3400000 {
> > + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> > + reg = <0x00 0x03400000 0x0 0x00100000 /* controller
> registers */
> > + 0x40 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > + interrupts = <0 118 0x4>, /* controller interrupt */
> > + <0 117 0x4>; /* PME interrupt */
> > + interrupt-names = "intr", "pme";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + num-lanes = <4>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0
> 0x00010000 /* downstream I/O */
> > + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&msi1>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
> > + <0000 0 0 2 &gic 0 111 0x4>,
> > + <0000 0 0 3 &gic 0 112 0x4>,
> > + <0000 0 0 4 &gic 0 113 0x4>;
> > + };
> > +
> > + pcie@3500000 {
> > + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> > + reg = <0x00 0x03500000 0x0 0x00100000 /* controller
> registers */
> > + 0x48 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > + interrupts = <0 128 0x4>,
> > + <0 127 0x4>;
> > + interrupt-names = "intr", "pme";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + num-lanes = <2>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0
> 0x00010000 /* downstream I/O */
> > + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&msi2>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
> > + <0000 0 0 2 &gic 0 121 0x4>,
> > + <0000 0 0 3 &gic 0 122 0x4>,
> > + <0000 0 0 4 &gic 0 123 0x4>;
> > + };
> > +
> > + pcie@3600000 {
> > + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> > + reg = <0x00 0x03600000 0x0 0x00100000 /* controller
> registers */
> > + 0x50 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > + interrupts = <0 162 0x4>,
> > + <0 161 0x4>;
> > + interrupt-names = "intr", "pme";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + num-lanes = <2>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0
> 0x00010000 /* downstream I/O */
> > + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&msi3>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
> > + <0000 0 0 2 &gic 0 155 0x4>,
> > + <0000 0 0 3 &gic 0 156 0x4>,
> > + <0000 0 0 4 &gic 0 157 0x4>;
> > + };
>
> You wait ages for a bus, then three show up at once...
>
> > +
> > + memory@80000000 {
> > + device_type = "memory";
> > + reg = <0x0 0x80000000 0 0x80000000>;
> > + /* DRAM space 1 - 2 GB DRAM */
>
> I don't understand the comment. This describes 2GB at 2GB.
>
Yes, there is a 2GB space for DRAM from address 2G.
The DRAM address 0x0 will be remapped to SoC address 2G, this remap is done by hardware.
> Does the bootloader overwrite this?
No.
Thanks,
Zhiqiang
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH 6/6] dts/ls1043a: add LS1043ARDB board support
2015-09-21 23:13 ` Scott Wood
@ 2015-09-22 9:51 ` Hou Zhiqiang
0 siblings, 0 replies; 22+ messages in thread
From: Hou Zhiqiang @ 2015-09-22 9:51 UTC (permalink / raw
To: Scott Wood
Cc: linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com,
will.deacon@arm.com, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, wsa@the-dreams.de, wim@iguana.be,
corbet@lwn.net, mturquette@baylibre.com, sboyd@codeaurora.org,
Hu Vincent, Shaohui Xie, Wenbin Song, Sharma Bhupesh, Li Leo
Hi Scott,
> -----Original Message-----
> From: Wood Scott-B07421
> Sent: 2015年9月22日 7:14
> To: Hou Zhiqiang-B48286
> Cc: linux-arm-kernel@lists.infradead.org; catalin.marinas@arm.com;
> will.deacon@arm.com; linux-i2c@vger.kernel.org; linux-
> watchdog@vger.kernel.org; linux-doc@vger.kernel.org; linux-
> clk@vger.kernel.org; wsa@the-dreams.de; wim@iguana.be; corbet@lwn.net;
> mturquette@baylibre.com; sboyd@codeaurora.org; Hu Mingkai-B21284; Xie
> Shaohui-B21989; Song Wenbin-B53747; Sharma Bhupesh-B45370; Li Yang-Leo-
> R58472
> Subject: Re: [PATCH 6/6] dts/ls1043a: add LS1043ARDB board support
>
> On Mon, 2015-09-21 at 20:22 +0800, Zhiqiang Hou wrote:
>
> > + cpld: board-control@2,0 {
> > + compatible = "fsl,ls1043ardb-cpld", "simple-bus";
> > + reg = <0x2 0x0 0x0000100>;
> > + };
>
> Again, why "simple-bus"?
Thanks and will remove it in v2.
Thanks,
Zhiqiang
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-22 9:50 ` Hou Zhiqiang
@ 2015-09-22 17:23 ` Li Leo
2015-09-22 19:04 ` Sharma Bhupesh
2015-09-23 3:05 ` Hou Zhiqiang
2015-09-22 22:15 ` Mark Rutland
1 sibling, 2 replies; 22+ messages in thread
From: Li Leo @ 2015-09-22 17:23 UTC (permalink / raw
To: Hou Zhiqiang, Mark Rutland, marc.zyngier@arm.com
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent
> >
> > Hi,
> >
> > > +/memreserve/ 0x80000000 0x00010000;
> >
> > Why is this necessary?
>
> This memory region is pre-reserved for the spin-table/psci, although didn't add
> Enable method of secondary cores.
Can this be reserved by bootloader?
>
> > If this is necessary, please add a comment stating what this is for.
> >
> > > + cpu@3 {
> > > + device_type = "cpu";
> > > + compatible = "arm,cortex-a53";
> > > + reg = <0x0 0x3>;
> > > + clocks = <&clockgen 1 0>;
> > > + };
> >
> > Missing enable-method properties on all the secondary CPUs.
> >
>
> There are two methods (spin-table and psci) to bring up secondary cores, which
> one do you think is better?
Do we have the PSCI support ready in both UEFI and u-boot? If not, we should use spin-table for now.
Regards,
Leo
--
To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-22 17:23 ` Li Leo
@ 2015-09-22 19:04 ` Sharma Bhupesh
2015-09-23 3:05 ` Hou Zhiqiang
1 sibling, 0 replies; 22+ messages in thread
From: Sharma Bhupesh @ 2015-09-22 19:04 UTC (permalink / raw
To: Li Leo, Hou Zhiqiang, Mark Rutland, marc.zyngier@arm.com
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
mturquette@baylibre.com, wsa@the-dreams.de, sboyd@codeaurora.org,
wim@iguana.be, Wenbin Song, Scott Wood, Hu Vincent
> -----Original Message-----
> From: Li Yang-Leo-R58472
> Sent: Tuesday, September 22, 2015 10:53 PM
> To: Hou Zhiqiang-B48286; Mark Rutland; marc.zyngier@arm.com
> Cc: linux-arm-kernel@lists.infradead.org; Catalin Marinas; Will Deacon;
> linux-i2c@vger.kernel.org; linux-watchdog@vger.kernel.org; linux-
> doc@vger.kernel.org; linux-clk@vger.kernel.org; Xie Shaohui-B21989;
> corbet@lwn.net; Sharma Bhupesh-B45370; mturquette@baylibre.com; wsa@the-
> dreams.de; sboyd@codeaurora.org; wim@iguana.be; Song Wenbin-B53747; Wood
> Scott-B07421; Hu Mingkai-B21284
> Subject: RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
>=20
> > >
> > > Hi,
> > >
> > > > +/memreserve/ 0x80000000 0x00010000;
> > >
> > > Why is this necessary?
> >
> > This memory region is pre-reserved for the spin-table/psci, although
> > didn't add Enable method of secondary cores.
>=20
> Can this be reserved by bootloader?
No need to reserve this for PSCI based secondary bootup.
> >
> > > If this is necessary, please add a comment stating what this is for.
> > >
> > > > + cpu@3 {
> > > > + device_type =3D "cpu";
> > > > + compatible =3D "arm,cortex-a53";
> > > > + reg =3D <0x0 0x3>;
> > > > + clocks =3D <&clockgen 1 0>;
> > > > + };
> > >
> > > Missing enable-method properties on all the secondary CPUs.
> > >
> >
> > There are two methods (spin-table and psci) to bring up secondary
> > cores, which one do you think is better?
>=20
> Do we have the PSCI support ready in both UEFI and u-boot? If not, we
> should use spin-table for now.
UEFI has been using PSCI with Arm Trusted Firmware (ATF) since some time. U=
-boot can also work with ATF seamlessly.
Spin-table method is deprecated and newer patches should support PSCI. If n=
ot, all intelligence should be left to the
Bootloader and the Linux DTS should not mention the 'enable-method' and the=
'memreserve' regions.=20
For details please see the LS2085A Freescale DTS already present in mainlin=
e kernel.
Regards,
Bhupesh
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-22 9:50 ` Hou Zhiqiang
2015-09-22 17:23 ` Li Leo
@ 2015-09-22 22:15 ` Mark Rutland
2015-09-22 22:39 ` Li Leo
` (2 more replies)
1 sibling, 3 replies; 22+ messages in thread
From: Mark Rutland @ 2015-09-22 22:15 UTC (permalink / raw
To: Hou Zhiqiang
Cc: Marc Zyngier, linux-arm-kernel@lists.infradead.org,
Catalin Marinas, Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent, Li Leo
On Tue, Sep 22, 2015 at 10:50:21AM +0100, Hou Zhiqiang wrote:
> Hi Mark,
>
> > -----Original Message-----
> > From: Mark Rutland [mailto:mark.rutland@arm.com]
> > Sent: 2015年9月22日 9:24
> > To: Hou Zhiqiang-B48286; marc.zyngier@arm.com
> > Cc: linux-arm-kernel@lists.infradead.org; Catalin Marinas; Will Deacon;
> > linux-i2c@vger.kernel.org; linux-watchdog@vger.kernel.org; linux-
> > doc@vger.kernel.org; linux-clk@vger.kernel.org; Xie Shaohui-B21989;
> > corbet@lwn.net; Sharma Bhupesh-B45370; mturquette@baylibre.com; wsa@the-
> > dreams.de; sboyd@codeaurora.org; wim@iguana.be; Song Wenbin-B53747; Wood
> > Scott-B07421; Hu Mingkai-B21284; Li Yang-Leo-R58472
> > Subject: Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
> >
> > Hi,
> >
> > > +/memreserve/ 0x80000000 0x00010000;
> >
> > Why is this necessary?
>
> This memory region is pre-reserved for the spin-table/psci, although didn't add
> Enable method of secondary cores.
Your PSCI implementation isn't in secure memory?
> > > + ifc: ifc@1530000 {
> > > + compatible = "fsl,ifc", "simple-bus";
> > > + reg = <0x0 0x1530000 0x0 0x10000>;
> > > + interrupts = <0 43 0x4>;
> > > + };
> >
> > Why simple-bus?
>
> There are 3 child node located in dtsi file that should be created and added
> to platform device list.
Are they usable even if the kernel knew nothing about the IFC node? If not, the
IFC driver should probe them, and simple-bus should go.
> > > + memory@80000000 {
> > > + device_type = "memory";
> > > + reg = <0x0 0x80000000 0 0x80000000>;
> > > + /* DRAM space 1 - 2 GB DRAM */
> >
> > I don't understand the comment. This describes 2GB at 2GB.
> >
>
> Yes, there is a 2GB space for DRAM from address 2G.
> The DRAM address 0x0 will be remapped to SoC address 2G, this remap is done by hardware.
I just realised my mistake -- I read this as "1 to 2 GB", when this is actually
"DRAM space 1". Sorry for the noise.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-22 22:15 ` Mark Rutland
@ 2015-09-22 22:39 ` Li Leo
2015-09-22 22:43 ` Scott Wood
2015-09-23 3:57 ` Hou Zhiqiang
2 siblings, 0 replies; 22+ messages in thread
From: Li Leo @ 2015-09-22 22:39 UTC (permalink / raw
To: Mark Rutland, Hou Zhiqiang, Kushwaha Prabhakar
Cc: Marc Zyngier, linux-arm-kernel@lists.infradead.org,
Catalin Marinas, Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent
> > > > + ifc: ifc@1530000 {
> > > > + compatible = "fsl,ifc", "simple-bus";
> > > > + reg = <0x0 0x1530000 0x0 0x10000>;
> > > > + interrupts = <0 43 0x4>;
> > > > + };
> > >
> > > Why simple-bus?
> >
> > There are 3 child node located in dtsi file that should be created and
> > added to platform device list.
>
> Are they usable even if the kernel knew nothing about the IFC node? If not, the
> IFC driver should probe them, and simple-bus should go.
Adding the IFC driver owner to the loop.
Regards,
Leo
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-22 22:15 ` Mark Rutland
2015-09-22 22:39 ` Li Leo
@ 2015-09-22 22:43 ` Scott Wood
2015-09-23 3:57 ` Hou Zhiqiang
2 siblings, 0 replies; 22+ messages in thread
From: Scott Wood @ 2015-09-22 22:43 UTC (permalink / raw
To: Mark Rutland
Cc: Hou Zhiqiang, Marc Zyngier, linux-arm-kernel@lists.infradead.org,
Catalin Marinas, Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Hu Vincent,
Li Leo, Kushwaha Prabhakar-B32579
On Tue, 2015-09-22 at 23:15 +0100, Mark Rutland wrote:
> On Tue, Sep 22, 2015 at 10:50:21AM +0100, Hou Zhiqiang wrote:
> > > > + ifc: ifc@1530000{
> > > > + compatible = "fsl,ifc", "simple-bus";
> > > > + reg = <0x0 0x1530000 0x0 0x10000>;
> > > > + interrupts = <0 43 0x4>;
> > > > + };
> > >
> > > Why simple-bus?
> >
> > There are 3 child node located in dtsi file that should be created and
> > added
> > to platform device list.
>
> Are they usable even if the kernel knew nothing about the IFC node?
Yes, except for NAND.
> If not, the IFC driver should probe them, and simple-bus should go.
IFC is not a new binding. IFC nodes are expected to have simple-bus.
-Scott
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-22 17:23 ` Li Leo
2015-09-22 19:04 ` Sharma Bhupesh
@ 2015-09-23 3:05 ` Hou Zhiqiang
2015-09-23 4:16 ` Li Leo
1 sibling, 1 reply; 22+ messages in thread
From: Hou Zhiqiang @ 2015-09-23 3:05 UTC (permalink / raw
To: Li Leo, Mark Rutland, marc.zyngier@arm.com
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent
> -----Original Message-----
> From: Li Yang-Leo-R58472
> Sent: 2015年9月23日 1:23
> To: Hou Zhiqiang-B48286; Mark Rutland; marc.zyngier@arm.com
> Cc: linux-arm-kernel@lists.infradead.org; Catalin Marinas; Will Deacon;
> linux-i2c@vger.kernel.org; linux-watchdog@vger.kernel.org; linux-
> doc@vger.kernel.org; linux-clk@vger.kernel.org; Xie Shaohui-B21989;
> corbet@lwn.net; Sharma Bhupesh-B45370; mturquette@baylibre.com; wsa@the-
> dreams.de; sboyd@codeaurora.org; wim@iguana.be; Song Wenbin-B53747; Wood
> Scott-B07421; Hu Mingkai-B21284
> Subject: RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
>
> > >
> > > Hi,
> > >
> > > > +/memreserve/ 0x80000000 0x00010000;
> > >
> > > Why is this necessary?
> >
> > This memory region is pre-reserved for the spin-table/psci, although
> > didn't add Enable method of secondary cores.
>
> Can this be reserved by bootloader?
Yes, the memory for psci was reserved by u-boot code. But due to spin-table
need the release address, is it better adding the /memreserve/ in dts file?
Or add it by bootloader and fix the release address accordingly?
>
> >
> > > If this is necessary, please add a comment stating what this is for.
> > >
> > > > + cpu@3 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x0 0x3>;
> > > > + clocks = <&clockgen 1 0>;
> > > > + };
> > >
> > > Missing enable-method properties on all the secondary CPUs.
> > >
> >
> > There are two methods (spin-table and psci) to bring up secondary
> > cores, which one do you think is better?
>
> Do we have the PSCI support ready in both UEFI and u-boot? If not, we
> should use spin-table for now.
>
our internal u-boot supports PSCI but opensource doesn't support it for ARMv8.
Thanks,
Zhiqiang
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-22 22:15 ` Mark Rutland
2015-09-22 22:39 ` Li Leo
2015-09-22 22:43 ` Scott Wood
@ 2015-09-23 3:57 ` Hou Zhiqiang
2 siblings, 0 replies; 22+ messages in thread
From: Hou Zhiqiang @ 2015-09-23 3:57 UTC (permalink / raw
To: Mark Rutland
Cc: Marc Zyngier, linux-arm-kernel@lists.infradead.org,
Catalin Marinas, Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent, Li Leo
> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland@arm.com]
> Sent: 2015年9月23日 6:15
> To: Hou Zhiqiang-B48286
> Cc: Marc Zyngier; linux-arm-kernel@lists.infradead.org; Catalin Marinas;
> Will Deacon; linux-i2c@vger.kernel.org; linux-watchdog@vger.kernel.org;
> linux-doc@vger.kernel.org; linux-clk@vger.kernel.org; Xie Shaohui-B21989;
> corbet@lwn.net; Sharma Bhupesh-B45370; mturquette@baylibre.com; wsa@the-
> dreams.de; sboyd@codeaurora.org; wim@iguana.be; Song Wenbin-B53747; Wood
> Scott-B07421; Hu Mingkai-B21284; Li Yang-Leo-R58472
> Subject: Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
>
> On Tue, Sep 22, 2015 at 10:50:21AM +0100, Hou Zhiqiang wrote:
> > Hi Mark,
> >
> > > -----Original Message-----
> > > From: Mark Rutland [mailto:mark.rutland@arm.com]
> > > Sent: 2015年9月22日 9:24
> > > To: Hou Zhiqiang-B48286; marc.zyngier@arm.com
> > > Cc: linux-arm-kernel@lists.infradead.org; Catalin Marinas; Will
> > > Deacon; linux-i2c@vger.kernel.org; linux-watchdog@vger.kernel.org;
> > > linux- doc@vger.kernel.org; linux-clk@vger.kernel.org; Xie
> > > Shaohui-B21989; corbet@lwn.net; Sharma Bhupesh-B45370;
> > > mturquette@baylibre.com; wsa@the- dreams.de; sboyd@codeaurora.org;
> > > wim@iguana.be; Song Wenbin-B53747; Wood Scott-B07421; Hu
> > > Mingkai-B21284; Li Yang-Leo-R58472
> > > Subject: Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale
> > > LS1043A SoC
> > >
> > > Hi,
> > >
> > > > +/memreserve/ 0x80000000 0x00010000;
> > >
> > > Why is this necessary?
> >
> > This memory region is pre-reserved for the spin-table/psci, although
> > didn't add Enable method of secondary cores.
>
> Your PSCI implementation isn't in secure memory?
>
Sorry, this is for spin-table, psci will fix it in u-boot.
> > > > + ifc: ifc@1530000 {
> > > > + compatible = "fsl,ifc", "simple-bus";
> > > > + reg = <0x0 0x1530000 0x0 0x10000>;
> > > > + interrupts = <0 43 0x4>;
> > > > + };
> > >
> > > Why simple-bus?
> >
> > There are 3 child node located in dtsi file that should be created and
> > added to platform device list.
>
> Are they usable even if the kernel knew nothing about the IFC node? If
> not, the IFC driver should probe them, and simple-bus should go.
>
> > > > + memory@80000000 {
> > > > + device_type = "memory";
> > > > + reg = <0x0 0x80000000 0 0x80000000>;
> > > > + /* DRAM space 1 - 2 GB DRAM */
> > >
> > > I don't understand the comment. This describes 2GB at 2GB.
> > >
> >
> > Yes, there is a 2GB space for DRAM from address 2G.
> > The DRAM address 0x0 will be remapped to SoC address 2G, this remap is
> done by hardware.
>
> I just realised my mistake -- I read this as "1 to 2 GB", when this is
> actually "DRAM space 1". Sorry for the noise.
>
Thanks,
Zhiqiang
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-23 3:05 ` Hou Zhiqiang
@ 2015-09-23 4:16 ` Li Leo
0 siblings, 0 replies; 22+ messages in thread
From: Li Leo @ 2015-09-23 4:16 UTC (permalink / raw
To: Hou Zhiqiang, Mark Rutland, marc.zyngier@arm.com
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent
> > > >
> > > > Hi,
> > > >
> > > > > +/memreserve/ 0x80000000 0x00010000;
> > > >
> > > > Why is this necessary?
> > >
> > > This memory region is pre-reserved for the spin-table/psci, although
> > > didn't add Enable method of secondary cores.
> >
> > Can this be reserved by bootloader?
>
> Yes, the memory for psci was reserved by u-boot code. But due to spin-table
> need the release address, is it better adding the /memreserve/ in dts file?
> Or add it by bootloader and fix the release address accordingly?
Both the reserved memory region and cpu-release-addr should be updated by bootloader.
Regards,
Leo
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 5/6] clk: qoriq: Add ls1043a support.
2015-09-21 12:22 ` [PATCH 5/6] clk: qoriq: Add ls1043a support Zhiqiang Hou
@ 2015-10-01 22:56 ` Stephen Boyd
0 siblings, 0 replies; 22+ messages in thread
From: Stephen Boyd @ 2015-10-01 22:56 UTC (permalink / raw
To: Zhiqiang Hou
Cc: linux-arm-kernel, catalin.marinas, will.deacon, linux-i2c,
linux-watchdog, linux-doc, linux-clk, wsa, wim, corbet,
mturquette, Mingkai.Hu, Shaohui.Xie, Wenbin.Song, scottwood,
bhupesh.sharma, leoli
On 09/21, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <B48286@freescale.com>
>
> Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
> ---
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2015-10-01 22:56 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-09-21 12:22 [PATCH 0/6] Add LS1043A SoC support Zhiqiang Hou
2015-09-21 12:22 ` [PATCH 1/6] i2c: Add i2c support to Freescale Layerscape platforms Zhiqiang Hou
2015-09-21 12:22 ` [PATCH 2/6] watchdog: Add support for " Zhiqiang Hou
2015-09-21 15:04 ` Guenter Roeck
2015-09-21 12:22 ` [PATCH 3/6] Documentation: DT: Add entry for FSL LS1043ARDB board Zhiqiang Hou
2015-09-21 12:22 ` [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC Zhiqiang Hou
2015-09-22 1:24 ` Mark Rutland, marc.zyngier
2015-09-22 1:30 ` Scott Wood
2015-09-22 9:50 ` Hou Zhiqiang
2015-09-22 17:23 ` Li Leo
2015-09-22 19:04 ` Sharma Bhupesh
2015-09-23 3:05 ` Hou Zhiqiang
2015-09-23 4:16 ` Li Leo
2015-09-22 22:15 ` Mark Rutland
2015-09-22 22:39 ` Li Leo
2015-09-22 22:43 ` Scott Wood
2015-09-23 3:57 ` Hou Zhiqiang
2015-09-21 12:22 ` [PATCH 5/6] clk: qoriq: Add ls1043a support Zhiqiang Hou
2015-10-01 22:56 ` Stephen Boyd
2015-09-21 12:22 ` [PATCH 6/6] dts/ls1043a: add LS1043ARDB board support Zhiqiang Hou
2015-09-21 23:13 ` Scott Wood
2015-09-22 9:51 ` Hou Zhiqiang
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