From: "André Draszik" <andre.draszik@linaro.org>
To: Peter Griffin <peter.griffin@linaro.org>,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org,
tomasz.figa@gmail.com, s.nawrocki@samsung.com,
linus.walleij@linaro.org, wim@linux-watchdog.org,
linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org,
arnd@arndb.de, olof@lixom.net, gregkh@linuxfoundation.org,
jirislaby@kernel.org, cw00.choi@samsung.com,
alim.akhtar@samsung.com
Cc: tudor.ambarus@linaro.org, semen.protsenko@linaro.org,
saravanak@google.com, willmcvicker@google.com, soc@kernel.org,
devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org,
kernel-team@android.com, linux-serial@vger.kernel.org
Subject: Re: [PATCH v4 11/19] clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm support
Date: Tue, 21 Nov 2023 14:30:45 +0000 [thread overview]
Message-ID: <8f7430b4056092552acaa323250709ba1c2bf605.camel@linaro.org> (raw)
In-Reply-To: <20231120212037.911774-12-peter.griffin@linaro.org>
On Mon, 2023-11-20 at 21:20 +0000, Peter Griffin wrote:
> [...]
> + /* HSI2 */
> + MUX(CLK_MOUT_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 2),
> + MUX(CLK_MOUT_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 2),
> + MUX(CLK_MOUT_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd",
> + mout_cmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
> + 0, 2),
> + MUX(CLK_MOUT_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card",
> + mout_cmu_hsi2_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD,
> + 0, 2),
> + /* CSIS */
> + MUX(CLK_MOUT_CSIS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 2),
> + /* PDP */
> + MUX(CLK_MOUT_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 2),
> + /* PDP */
you have the /* PDP */ commend twice here.
> + MUX(CLK_MOUT_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p,
> + CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 2),
> + /* IPP */
> + MUX(CLK_MOUT_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 2),
> + /* G3AA */
> + MUX(CLK_MOUT_G3AA, "mout_cmu_g3aa_g3aa", mout_cmu_g3aa_g3aa_p,
> + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 2),
> + /* ITP */
> + MUX(CLK_MOUT_ITP, "mout_cmu_itp_bus", mout_cmu_itp_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 2),
> + /* DNS */
> + MUX(CLK_MOUT_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 2),
> + /* TNR */
> + MUX(CLK_MOUT_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 2),
> + /* MCSC*/
> + MUX(CLK_MOUT_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p,
> + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 2),
> + MUX(CLK_MOUT_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p,
> + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 2),
> + /* GDC */
> + MUX(CLK_MOUT_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p,
> + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 2),
> + MUX(CLK_MOUT_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p,
> + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 2),
> + MUX(CLK_MOUT_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p,
> + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 2),
> + /* MFC */
> + MUX(CLK_MOUT_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p,
> + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
> + /* DDRPHY0/1/2/3 */
> + MUX(CLK_MOUT_MIF_SWITCH, "mout_cmu_mif_switch", mout_cmu_mif_switch_p,
> + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 2),
> + /* MIF0/1/2/3 */
> + MUX(CLK_MOUT_MIF_BUS, "mout_cmu_mif_busp", mout_cmu_mif_busp_p,
> + CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
> + /* MISC */
> + MUX(CLK_MOUT_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2),
> + MUX(CLK_MOUT_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p,
> + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2),
> + /* PERI0 */
> + MUX(CLK_MOUT_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
> + MUX(CLK_MOUT_PERIC0_BUS, "mout_cmu_peric0_bus", mout_cmu_peric0_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
> + /* PERI1 */
> + MUX(CLK_MOUT_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
> + MUX(CLK_MOUT_PERIC1_BUS, "mout_cmu_peric1_bus", mout_cmu_peric1_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
> + /* TPU */
> + MUX(CLK_MOUT_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 2),
> + MUX(CLK_MOUT_TPU_TPUCTL, "mout_cmu_tpu_tpuctl", mout_cmu_tpu_tpuctl_p,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 2),
> + MUX(CLK_MOUT_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 2),
> + MUX(CLK_MOUT_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2),
> + /* BO */
> + MUX(CLK_MOUT_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 2),
> +};
> +
> +static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {
> + /* CMU_TOP_PURECLKCOMP */
> + DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
> + CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
> + DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
> + CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
> + DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "mout_shared0_pll",
> + CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 2),
> + DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
> + CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
> + DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
> + CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
> + DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
> + CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
> + DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "mout_shared1_pll",
> + CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
> + DIV(CLK_DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll",
> + CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
> + DIV(CLK_DOUT_SHARED3_DIV2, "dout_shared3_div2", "mout_shared3_pll",
> + CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),
> + /* BUS0 */
> + DIV(CLK_DOUT_BUS0_BUS, "dout_cmu_bus0_bus_div", "gout_cmu_bus0_bus",
> + CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
> + DIV(CLK_DOUT_CMU_BOOST, "dout_cmu_boost", "gout_cmu_cmu_boost",
> + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
> + /* BUS1 */
> + DIV(CLK_DOUT_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus",
> + CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
> + /* BUS2 */
> + DIV(CLK_DOUT_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus",
> + CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4),
> + /* CORE */
> + DIV(CLK_DOUT_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
> + CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
> + /* EH */
> + DIV(CLK_DOUT_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus",
> + CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4),
> + /* CPUCL{0,1,2,} */
> + DIV(CLK_DOUT_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch",
> + "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
> + DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch",
> + "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
> + DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch",
> + "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
> + DIV(CLK_DOUT_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", "gout_cmu_cpucl0_dbg",
> + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
> + DIV(CLK_DOUT_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",
> + CLK_CON_DIV_CLKCMU_HPM, 0, 2),
> + /* G3D */
> + DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_switch", "gout_cmu_g3d_switch",
> + CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
> + DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
> + CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),
> +
accidental extra empty line
> + DIV(CLK_DOUT_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb",
> + CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
> + /* DPU */
> + DIV(CLK_DOUT_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus",
> + CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4),
> + /* DISP */
> + DIV(CLK_DOUT_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus",
> + CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4),
> + /* G2D */
> + DIV(CLK_DOUT_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",
> + CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
> + DIV(CLK_DOUT_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl",
> + CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
> + /* HSI0 */
> + DIV(CLK_DOUT_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd",
> + "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5),
> + DIV(CLK_DOUT_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus",
> + CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
> + DIV(CLK_DOUT_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", "gout_cmu_hsi0_dpgtc",
> + CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4),
> + /* TODO register exists but all lower bits are reserved */
> + DIV(CLK_DOUT_HSI0_USBDPDGB, "dout_cmu_hsi0_usbdpdbg",
> + "gout_cmu_hsi0_usbdpdbg", CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, 0, 0),
> + /* HSI1 */
> + DIV(CLK_DOUT_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
> + CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4),
> + DIV(CLK_DOUT_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",
> + CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3),
> + /* HSI2 */
> + DIV(CLK_DOUT_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
> + CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
> + DIV(CLK_DOUT_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",
> + CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3),
> + DIV(CLK_DOUT_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd",
> + "gout_cmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4),
> + DIV(CLK_DOUT_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card",
> + "gout_cmu_hsi2_mmc_card", CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9),
> + /* CSIS */
> + DIV(CLK_DOUT_CSIS, "dout_cmu_csis_bus", "gout_cmu_csis_bus",
> + CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
> + /* PDP */
> + DIV(CLK_DOUT_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus",
> + CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4),
> + DIV(CLK_DOUT_PDP_VRA, "dout_cmu_pdp_vra", "gout_cmu_pdp_vra",
> + CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4),
> + /* IPP */
> + DIV(CLK_DOUT_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
> + CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
> + /* G3AA */
> + DIV(CLK_DOUT_G3AA, "dout_cmu_g3aa_g3aa", "gout_cmu_g3aa_g3aa",
> + CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),
> + /* ITP */
> + DIV(CLK_DOUT_ITP, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
> + CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
> + /* DNS */
> + DIV(CLK_DOUT_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus",
> + CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
> + /* TNR */
> + DIV(CLK_DOUT_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus",
> + CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
> + /* MCSC*/
> + DIV(CLK_DOUT_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc",
> + CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4),
> + DIV(CLK_DOUT_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc",
> + CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4),
> + /* GDC */
> + DIV(CLK_DOUT_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc",
> + CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4),
> + DIV(CLK_DOUT_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0",
> + CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4),
> + DIV(CLK_DOUT_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1",
> + CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4),
> + /* MFC */
> + DIV(CLK_DOUT_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc",
> + CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
> + /* MIF0/1/2/3 */
> + DIV(CLK_DOUT_MIF_BUS, "dout_cmu_mif_busp", "gout_cmu_mif_busp",
> + CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
> + /* MISC */
> + DIV(CLK_DOUT_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus",
> + CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4),
> + DIV(CLK_DOUT_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss",
> + CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4),
> + /* PERI0 */
> + DIV(CLK_DOUT_PERIC0_BUS, "dout_cmu_peric0_bus", "gout_cmu_peric0_bus",
> + CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
> + DIV(CLK_DOUT_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip",
> + CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
> + /* PERI1 */
> + DIV(CLK_DOUT_PERIC1_BUS, "dout_cmu_peric1_bus", "gout_cmu_peric1_bus",
> + CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
> + DIV(CLK_DOUT_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip",
> + CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
> + /* TPU */
> + DIV(CLK_DOUT_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu",
> + CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4),
> + DIV(CLK_DOUT_TPU_TPUCTL, "dout_cmu_tpu_tpuctl", "gout_cmu_tpu_tpuctl",
> + CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4),
> + DIV(CLK_DOUT_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus",
> + CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4),
> + DIV(CLK_DOUT_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart",
> + CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4),
> + /* BO */
> + DIV(CLK_DOUT_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus",
> + CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4),
> +};
> +
> +static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {
> + /* BUS0 */
> + GATE(CLK_GOUT_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
> + CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0),
> + /* BUS1 */
> + GATE(CLK_GOUT_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
> + CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0),
> + /* BUS2 */
> + GATE(CLK_GOUT_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus",
> + CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0),
> + /* CORE */
> + GATE(CLK_GOUT_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
> + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
> + /* EH */
> + GATE(CLK_GOUT_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus",
> + CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0),
> + /* CPUCL{0,1,2,} */
> + GATE(CLK_GOUT_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch",
> + "mout_cmu_cpucl2_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
> + 21, 0, 0),
> + GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch",
> + "mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
> + 21, 0, 0),
> + GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch",
> + "mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
> + 21, 0, 0),
> + GATE(CLK_GOUT_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", "mout_cmu_cpucl0_dbg",
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
> + CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
> + /* G3D */
> + GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_switch", "mout_cmu_g3d_switch",
> + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
> + GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd",
> + CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0),
> + GATE(CLK_GOUT_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb",
> + CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0),
> + /* DPU */
> + GATE(CLK_GOUT_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
> + CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0),
> + /* DISP */
> + GATE(CLK_GOUT_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus",
> + CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0),
> + /* G2D */
> + GATE(CLK_GOUT_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
> + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
> + GATE(CLK_GOUT_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
> + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
> + /* HSI0 */
> + GATE(CLK_GOUT_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd",
> + "mout_cmu_hsi0_usb31drd", CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
> + 21, 0, 0),
> + GATE(CLK_GOUT_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus",
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", "mout_cmu_hsi0_dpgtc",
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 21, 0, 0),
> + GATE(CLK_GOUT_HSI0_USBDPDGB, "gout_cmu_hsi0_usbdpdbg",
> + "mout_cmu_hsi0_usbdpdbg", CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,
> + 21, 0, 0),
> + /* HSI1 */
> + GATE(CLK_GOUT_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
> + CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie",
> + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0),
> + /* HSI2 */
> + GATE(CLK_GOUT_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie",
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0),
> + GATE(CLK_GOUT_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd",
> + "mout_cmu_hsi2_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,
> + 21, 0, 0),
> + GATE(CLK_GOUT_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card",
> + "mout_cmu_hsi2_mmc_card", CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,
> + 21, 0, 0),
> + /* CSIS */
> + GATE(CLK_GOUT_CSIS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
> + CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
> + /* PDP */
> + GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
> + CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
> +
and here
Cheers,
Andre'
next prev parent reply other threads:[~2023-11-21 14:30 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-20 21:20 [PATCH v4 00/19] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board Peter Griffin
2023-11-20 21:20 ` [PATCH v4 01/19] dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible Peter Griffin
2023-11-20 21:20 ` [PATCH v4 02/19] dt-bindings: clock: Add Google gs101 clock management unit bindings Peter Griffin
2023-11-21 8:41 ` André Draszik
2023-11-20 21:20 ` [PATCH v4 03/19] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101 Peter Griffin
2023-11-20 21:20 ` [PATCH v4 04/19] dt-bindings: watchdog: Document Google gs101 watchdog bindings Peter Griffin
2023-11-20 21:20 ` [PATCH v4 05/19] dt-bindings: arm: google: Add bindings for Google ARM platforms Peter Griffin
2023-11-20 21:20 ` [PATCH v4 06/19] dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible Peter Griffin
2023-11-20 21:20 ` [PATCH v4 07/19] dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible Peter Griffin
2023-11-22 19:11 ` Krzysztof Kozlowski
2023-11-22 19:15 ` Krzysztof Kozlowski
2023-11-20 21:20 ` [PATCH v4 08/19] dt-bindings: serial: samsung: Add google-gs101-uart compatible Peter Griffin
2023-11-20 21:20 ` [PATCH v4 09/19] dt-bindings: serial: samsung: Make samsung,uart-fifosize required property Peter Griffin
2023-11-20 23:15 ` Rob Herring
2023-11-21 15:16 ` Rob Herring
2023-11-21 17:15 ` Peter Griffin
2023-11-22 7:49 ` Krzysztof Kozlowski
2023-11-22 8:42 ` Peter Griffin
2023-11-20 21:20 ` [PATCH v4 10/19] clk: samsung: clk-pll: Add support for pll_{0516,0517,518} Peter Griffin
2023-11-20 21:20 ` [PATCH v4 11/19] clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm support Peter Griffin
2023-11-21 8:41 ` André Draszik
2023-11-21 9:21 ` Peter Griffin
2023-11-24 22:16 ` Peter Griffin
2023-11-21 14:30 ` André Draszik [this message]
2023-11-24 22:03 ` Peter Griffin
2023-11-20 21:20 ` [PATCH v4 12/19] pinctrl: samsung: Add filter selection support for alive banks Peter Griffin
2023-11-20 21:20 ` [PATCH v4 13/19] pinctrl: samsung: Add gs101 SoC pinctrl configuration Peter Griffin
2023-11-20 21:20 ` [PATCH v4 14/19] watchdog: s3c2410_wdt: Add support for Google gs101 SoC Peter Griffin
2023-11-20 21:20 ` [PATCH v4 15/19] watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bit Peter Griffin
2023-11-20 21:59 ` Guenter Roeck
2023-11-20 22:45 ` Peter Griffin
2023-11-20 23:03 ` Guenter Roeck
2023-11-20 23:20 ` Peter Griffin
2023-11-20 23:31 ` Guenter Roeck
2023-11-21 17:52 ` Sam Protsenko
2023-11-21 18:10 ` Guenter Roeck
2023-11-22 7:53 ` Krzysztof Kozlowski
2023-11-22 8:20 ` Peter Griffin
2023-11-20 21:20 ` [PATCH v4 16/19] tty: serial: samsung: Add gs101 compatible and common fifoszdt_serial_drv_data Peter Griffin
2023-11-23 19:47 ` Greg KH
2023-11-20 21:20 ` [PATCH v4 17/19] arm64: dts: exynos: google: Add initial Google gs101 SoC support Peter Griffin
2023-11-21 13:53 ` Peter Griffin
2023-11-20 21:20 ` [PATCH v4 18/19] arm64: dts: exynos: google: Add initial Oriole/pixel 6 board support Peter Griffin
2023-11-21 18:39 ` Sam Protsenko
2023-12-01 12:01 ` Peter Griffin
2023-11-20 21:20 ` [PATCH v4 19/19] MAINTAINERS: add entry for Google Tensor SoC Peter Griffin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=8f7430b4056092552acaa323250709ba1c2bf605.camel@linaro.org \
--to=andre.draszik@linaro.org \
--cc=alim.akhtar@samsung.com \
--cc=arnd@arndb.de \
--cc=catalin.marinas@arm.com \
--cc=conor+dt@kernel.org \
--cc=cw00.choi@samsung.com \
--cc=devicetree@vger.kernel.org \
--cc=gregkh@linuxfoundation.org \
--cc=jirislaby@kernel.org \
--cc=kernel-team@android.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linus.walleij@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-samsung-soc@vger.kernel.org \
--cc=linux-serial@vger.kernel.org \
--cc=linux-watchdog@vger.kernel.org \
--cc=linux@roeck-us.net \
--cc=mturquette@baylibre.com \
--cc=olof@lixom.net \
--cc=peter.griffin@linaro.org \
--cc=robh+dt@kernel.org \
--cc=s.nawrocki@samsung.com \
--cc=saravanak@google.com \
--cc=sboyd@kernel.org \
--cc=semen.protsenko@linaro.org \
--cc=soc@kernel.org \
--cc=tomasz.figa@gmail.com \
--cc=tudor.ambarus@linaro.org \
--cc=will@kernel.org \
--cc=willmcvicker@google.com \
--cc=wim@linux-watchdog.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).