* [PATCH v2 01/19] ath11k: PCI changes to support WCN6750
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
@ 2022-01-16 12:46 ` Manikanta Pubbisetty
2022-01-16 12:46 ` [PATCH v2 02/19] ath11k: Refactor PCI code to support hybrid bus devices Manikanta Pubbisetty
` (18 subsequent siblings)
19 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:46 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
In order to support hybrid bus devices like WCN6750, it is
required to move certain PCI definitions to the header file.
As a result, add ATH11K_PCI_* prefix to these definitions.
Also, change the PCI APIs that are required to enable WCN6750
from static to extern.
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/pci.c | 108 +++++++++++++++-------------------
drivers/net/wireless/ath/ath11k/pci.h | 35 +++++++++++
2 files changed, 84 insertions(+), 59 deletions(-)
diff --git a/drivers/net/wireless/ath/ath11k/pci.c b/drivers/net/wireless/ath/ath11k/pci.c
index d73b522..9a50cba 100644
--- a/drivers/net/wireless/ath/ath11k/pci.c
+++ b/drivers/net/wireless/ath/ath11k/pci.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/module.h>
@@ -18,24 +19,11 @@
#define ATH11K_PCI_DMA_MASK 32
#define ATH11K_PCI_IRQ_CE0_OFFSET 3
-#define ATH11K_PCI_IRQ_DP_OFFSET 14
-
-#define WINDOW_ENABLE_BIT 0x40000000
-#define WINDOW_REG_ADDRESS 0x310c
-#define WINDOW_VALUE_MASK GENMASK(24, 19)
-#define WINDOW_START 0x80000
-#define WINDOW_RANGE_MASK GENMASK(18, 0)
#define TCSR_SOC_HW_VERSION 0x0224
#define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
#define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
-/* BAR0 + 4k is always accessible, and no
- * need to force wakeup.
- * 4K - 32 = 0xFE0
- */
-#define ACCESS_ALWAYS_OFF 0xFE0
-
#define QCA6390_DEVICE_ID 0x1101
#define QCN9074_DEVICE_ID 0x1104
#define WCN6855_DEVICE_ID 0x1103
@@ -147,27 +135,30 @@ static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offse
{
struct ath11k_base *ab = ab_pci->ab;
- u32 window = FIELD_GET(WINDOW_VALUE_MASK, offset);
+ u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
lockdep_assert_held(&ab_pci->window_lock);
if (window != ab_pci->register_window) {
- iowrite32(WINDOW_ENABLE_BIT | window,
- ab->mem + WINDOW_REG_ADDRESS);
- ioread32(ab->mem + WINDOW_REG_ADDRESS);
+ iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
+ ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
+ ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
ab_pci->register_window = window;
}
}
static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci)
{
- u32 umac_window = FIELD_GET(WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET);
- u32 ce_window = FIELD_GET(WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE);
+ u32 umac_window;
+ u32 ce_window;
u32 window;
+ umac_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET);
+ ce_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE);
window = (umac_window << 12) | (ce_window << 6);
- iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS);
+ iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
+ ab_pci->ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
}
static inline u32 ath11k_pci_get_window_start(struct ath11k_base *ab,
@@ -176,13 +167,13 @@ static inline u32 ath11k_pci_get_window_start(struct ath11k_base *ab,
u32 window_start;
/* If offset lies within DP register range, use 3rd window */
- if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK)
- window_start = 3 * WINDOW_START;
+ if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
+ window_start = 3 * ATH11K_PCI_WINDOW_START;
/* If offset lies within CE register range, use 2nd window */
- else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK)
- window_start = 2 * WINDOW_START;
+ else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < ATH11K_PCI_WINDOW_RANGE_MASK)
+ window_start = 2 * ATH11K_PCI_WINDOW_START;
else
- window_start = WINDOW_START;
+ window_start = ATH11K_PCI_WINDOW_START;
return window_start;
}
@@ -197,32 +188,32 @@ void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value)
*/
if (ab->hw_params.wakeup_mhi &&
test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
- offset >= ACCESS_ALWAYS_OFF)
+ offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
- if (offset < WINDOW_START) {
+ if (offset < ATH11K_PCI_WINDOW_START) {
iowrite32(value, ab->mem + offset);
} else {
if (ab->bus_params.static_window_map)
window_start = ath11k_pci_get_window_start(ab, offset);
else
- window_start = WINDOW_START;
+ window_start = ATH11K_PCI_WINDOW_START;
- if (window_start == WINDOW_START) {
+ if (window_start == ATH11K_PCI_WINDOW_START) {
spin_lock_bh(&ab_pci->window_lock);
ath11k_pci_select_window(ab_pci, offset);
iowrite32(value, ab->mem + window_start +
- (offset & WINDOW_RANGE_MASK));
+ (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
spin_unlock_bh(&ab_pci->window_lock);
} else {
iowrite32(value, ab->mem + window_start +
- (offset & WINDOW_RANGE_MASK));
+ (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
}
}
if (ab->hw_params.wakeup_mhi &&
test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
- offset >= ACCESS_ALWAYS_OFF)
+ offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
}
@@ -236,32 +227,32 @@ u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset)
*/
if (ab->hw_params.wakeup_mhi &&
test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
- offset >= ACCESS_ALWAYS_OFF)
+ offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
- if (offset < WINDOW_START) {
+ if (offset < ATH11K_PCI_WINDOW_START) {
val = ioread32(ab->mem + offset);
} else {
if (ab->bus_params.static_window_map)
window_start = ath11k_pci_get_window_start(ab, offset);
else
- window_start = WINDOW_START;
+ window_start = ATH11K_PCI_WINDOW_START;
- if (window_start == WINDOW_START) {
+ if (window_start == ATH11K_PCI_WINDOW_START) {
spin_lock_bh(&ab_pci->window_lock);
ath11k_pci_select_window(ab_pci, offset);
val = ioread32(ab->mem + window_start +
- (offset & WINDOW_RANGE_MASK));
+ (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
spin_unlock_bh(&ab_pci->window_lock);
} else {
val = ioread32(ab->mem + window_start +
- (offset & WINDOW_RANGE_MASK));
+ (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
}
}
if (ab->hw_params.wakeup_mhi &&
test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
- offset >= ACCESS_ALWAYS_OFF)
+ offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
return val;
@@ -470,8 +461,8 @@ int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector)
return pci_irq_vector(pci_dev, vector);
}
-static void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
- u32 *msi_addr_hi)
+void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
+ u32 *msi_addr_hi)
{
struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
struct pci_dev *pci_dev = to_pci_dev(ab->dev);
@@ -515,8 +506,7 @@ int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ab_pci, char *user_nam
return -EINVAL;
}
-static void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id,
- u32 *msi_idx)
+void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx)
{
u32 i, msi_data_idx;
@@ -532,9 +522,9 @@ static void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id,
*msi_idx = msi_data_idx;
}
-static int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
- int *num_vectors, u32 *user_base_data,
- u32 *base_vector)
+int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
+ int *num_vectors, u32 *user_base_data,
+ u32 *base_vector)
{
struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
@@ -557,7 +547,7 @@ static void ath11k_pci_free_ext_irq(struct ath11k_base *ab)
}
}
-static void ath11k_pci_free_irq(struct ath11k_base *ab)
+void ath11k_pci_free_irq(struct ath11k_base *ab)
{
int i, irq_idx;
@@ -706,7 +696,7 @@ static void ath11k_pci_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp)
enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
}
-static void ath11k_pci_ext_irq_enable(struct ath11k_base *ab)
+void ath11k_pci_ext_irq_enable(struct ath11k_base *ab)
{
int i;
@@ -737,7 +727,7 @@ static void ath11k_pci_sync_ext_irqs(struct ath11k_base *ab)
}
}
-static void ath11k_pci_ext_irq_disable(struct ath11k_base *ab)
+void ath11k_pci_ext_irq_disable(struct ath11k_base *ab)
{
__ath11k_pci_ext_irq_disable(ab);
ath11k_pci_sync_ext_irqs(ab);
@@ -850,8 +840,8 @@ static int ath11k_pci_ext_irq_config(struct ath11k_base *ab)
return 0;
}
-static int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
- const struct cpumask *m)
+int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
+ const struct cpumask *m)
{
if (test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
return 0;
@@ -859,7 +849,7 @@ static int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
return irq_set_affinity_hint(ab_pci->pdev->irq, m);
}
-static int ath11k_pci_config_irq(struct ath11k_base *ab)
+int ath11k_pci_config_irq(struct ath11k_base *ab)
{
struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
struct ath11k_ce_pipe *ce_pipe;
@@ -935,7 +925,7 @@ static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab)
&cfg->shadow_reg_v2_len);
}
-static void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab)
+void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab)
{
int i;
@@ -1147,7 +1137,7 @@ static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci)
set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags);
}
-static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
+void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
{
if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags))
pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
@@ -1230,20 +1220,20 @@ static void ath11k_pci_kill_tasklets(struct ath11k_base *ab)
}
}
-static void ath11k_pci_ce_irq_disable_sync(struct ath11k_base *ab)
+void ath11k_pci_ce_irq_disable_sync(struct ath11k_base *ab)
{
ath11k_pci_ce_irqs_disable(ab);
ath11k_pci_sync_ce_irqs(ab);
ath11k_pci_kill_tasklets(ab);
}
-static void ath11k_pci_stop(struct ath11k_base *ab)
+void ath11k_pci_stop(struct ath11k_base *ab)
{
ath11k_pci_ce_irq_disable_sync(ab);
ath11k_ce_cleanup_pipes(ab);
}
-static int ath11k_pci_start(struct ath11k_base *ab)
+int ath11k_pci_start(struct ath11k_base *ab)
{
struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
@@ -1273,8 +1263,8 @@ static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab)
ath11k_pci_ce_irq_disable_sync(ab);
}
-static int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
- u8 *ul_pipe, u8 *dl_pipe)
+int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
+ u8 *ul_pipe, u8 *dl_pipe)
{
const struct service_to_pipe *entry;
bool ul_set = false, dl_set = false;
diff --git a/drivers/net/wireless/ath/ath11k/pci.h b/drivers/net/wireless/ath/ath11k/pci.h
index 61d67b2..4869384 100644
--- a/drivers/net/wireless/ath/ath11k/pci.h
+++ b/drivers/net/wireless/ath/ath11k/pci.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
/*
* Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _ATH11K_PCI_H
#define _ATH11K_PCI_H
@@ -52,6 +53,21 @@
#define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c
#define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4
+#define ATH11K_PCI_IRQ_CE0_OFFSET 3
+#define ATH11K_PCI_IRQ_DP_OFFSET 14
+
+#define ATH11K_PCI_WINDOW_ENABLE_BIT 0x40000000
+#define ATH11K_PCI_WINDOW_REG_ADDRESS 0x310c
+#define ATH11K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19)
+#define ATH11K_PCI_WINDOW_START 0x80000
+#define ATH11K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0)
+
+/* BAR0 + 4k is always accessible, and no
+ * need to force wakeup.
+ * 4K - 32 = 0xFE0
+ */
+#define ATH11K_PCI_ACCESS_ALWAYS_OFF 0xFE0
+
struct ath11k_msi_user {
char *name;
int num_vectors;
@@ -103,5 +119,24 @@ int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ar_pci, char *user_nam
int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector);
void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value);
u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset);
+void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
+ u32 *msi_addr_hi);
+void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx);
+void ath11k_pci_free_irq(struct ath11k_base *ab);
+int ath11k_pci_config_irq(struct ath11k_base *ab);
+void ath11k_pci_ext_irq_enable(struct ath11k_base *ab);
+void ath11k_pci_ext_irq_disable(struct ath11k_base *ab);
+void ath11k_pci_stop(struct ath11k_base *ab);
+int ath11k_pci_start(struct ath11k_base *ab);
+int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
+ u8 *ul_pipe, u8 *dl_pipe);
+void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab);
+void ath11k_pci_ce_irq_disable_sync(struct ath11k_base *ab);
+int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
+ int *num_vectors, u32 *user_base_data,
+ u32 *base_vector);
+void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci);
+int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
+ const struct cpumask *m);
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 02/19] ath11k: Refactor PCI code to support hybrid bus devices
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
2022-01-16 12:46 ` [PATCH v2 01/19] ath11k: PCI changes to support WCN6750 Manikanta Pubbisetty
@ 2022-01-16 12:46 ` Manikanta Pubbisetty
2022-01-28 10:16 ` Kalle Valo
2022-01-28 12:13 ` Kalle Valo
2022-01-16 12:46 ` [PATCH v2 03/19] ath11k: Choose MSI config based on HW revision Manikanta Pubbisetty
` (17 subsequent siblings)
19 siblings, 2 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:46 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
Unlike other ATH11K PCIe devices which are enumerated by APSS
processor (Application Processor SubSystem), WCN6750 gets
enumerated by the WPSS Q6 processor (Wireless Processor SubSystem);
In simple terms, though WCN6750 is PCIe device, it is not attached
to the APSS processor, APSS will not know of such a device being
present in the system and therefore WCN6750 will be registered as
a platform device to the kernel core like other supported AHB
devices.
WCN6750 uses both AHB and PCI APIs for it's operation, it uses
AHB APIs for device probe/boot and PCI APIs for device setup
and register accesses; Because of this nature, it is referred
as a hybrid bus device.
Refactor PCI code to support hybrid bus devices like WCN6750.
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/Makefile | 2 +-
drivers/net/wireless/ath/ath11k/mhi.c | 6 +-
drivers/net/wireless/ath/ath11k/pci.c | 734 +----------------------------
drivers/net/wireless/ath/ath11k/pci.h | 41 --
drivers/net/wireless/ath/ath11k/pci_cmn.c | 743 ++++++++++++++++++++++++++++++
drivers/net/wireless/ath/ath11k/pci_cmn.h | 53 +++
6 files changed, 803 insertions(+), 776 deletions(-)
create mode 100644 drivers/net/wireless/ath/ath11k/pci_cmn.c
create mode 100644 drivers/net/wireless/ath/ath11k/pci_cmn.h
diff --git a/drivers/net/wireless/ath/ath11k/Makefile b/drivers/net/wireless/ath/ath11k/Makefile
index c1fce41..71376da 100644
--- a/drivers/net/wireless/ath/ath11k/Makefile
+++ b/drivers/net/wireless/ath/ath11k/Makefile
@@ -29,7 +29,7 @@ obj-$(CONFIG_ATH11K_AHB) += ath11k_ahb.o
ath11k_ahb-y += ahb.o
obj-$(CONFIG_ATH11K_PCI) += ath11k_pci.o
-ath11k_pci-y += mhi.o pci.o
+ath11k_pci-y += mhi.o pci.o pci_cmn.o
# for tracing framework to find trace.h
CFLAGS_trace.o := -I$(src)
diff --git a/drivers/net/wireless/ath/ath11k/mhi.c b/drivers/net/wireless/ath/ath11k/mhi.c
index cccaa34..21b8cfd 100644
--- a/drivers/net/wireless/ath/ath11k/mhi.c
+++ b/drivers/net/wireless/ath/ath11k/mhi.c
@@ -1,5 +1,8 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
-/* Copyright (c) 2020 The Linux Foundation. All rights reserved. */
+/*
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
#include <linux/msi.h>
#include <linux/pci.h>
@@ -11,6 +14,7 @@
#include "debug.h"
#include "mhi.h"
#include "pci.h"
+#include "pci_cmn.h"
#define MHI_TIMEOUT_DEFAULT_MS 90000
diff --git a/drivers/net/wireless/ath/ath11k/pci.c b/drivers/net/wireless/ath/ath11k/pci.c
index 9a50cba..81ee647 100644
--- a/drivers/net/wireless/ath/ath11k/pci.c
+++ b/drivers/net/wireless/ath/ath11k/pci.c
@@ -14,6 +14,7 @@
#include "hif.h"
#include "mhi.h"
#include "debug.h"
+#include "pci_cmn.h"
#define ATH11K_PCI_BAR_NUM 0
#define ATH11K_PCI_DMA_MASK 32
@@ -77,76 +78,6 @@ static const struct ath11k_msi_config msi_config_one_msi = {
},
};
-static const char *irq_name[ATH11K_IRQ_NUM_MAX] = {
- "bhi",
- "mhi-er0",
- "mhi-er1",
- "ce0",
- "ce1",
- "ce2",
- "ce3",
- "ce4",
- "ce5",
- "ce6",
- "ce7",
- "ce8",
- "ce9",
- "ce10",
- "ce11",
- "host2wbm-desc-feed",
- "host2reo-re-injection",
- "host2reo-command",
- "host2rxdma-monitor-ring3",
- "host2rxdma-monitor-ring2",
- "host2rxdma-monitor-ring1",
- "reo2ost-exception",
- "wbm2host-rx-release",
- "reo2host-status",
- "reo2host-destination-ring4",
- "reo2host-destination-ring3",
- "reo2host-destination-ring2",
- "reo2host-destination-ring1",
- "rxdma2host-monitor-destination-mac3",
- "rxdma2host-monitor-destination-mac2",
- "rxdma2host-monitor-destination-mac1",
- "ppdu-end-interrupts-mac3",
- "ppdu-end-interrupts-mac2",
- "ppdu-end-interrupts-mac1",
- "rxdma2host-monitor-status-ring-mac3",
- "rxdma2host-monitor-status-ring-mac2",
- "rxdma2host-monitor-status-ring-mac1",
- "host2rxdma-host-buf-ring-mac3",
- "host2rxdma-host-buf-ring-mac2",
- "host2rxdma-host-buf-ring-mac1",
- "rxdma2host-destination-ring-mac3",
- "rxdma2host-destination-ring-mac2",
- "rxdma2host-destination-ring-mac1",
- "host2tcl-input-ring4",
- "host2tcl-input-ring3",
- "host2tcl-input-ring2",
- "host2tcl-input-ring1",
- "wbm2host-tx-completions-ring3",
- "wbm2host-tx-completions-ring2",
- "wbm2host-tx-completions-ring1",
- "tcl2host-status-ring",
-};
-
-static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
-{
- struct ath11k_base *ab = ab_pci->ab;
-
- u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
-
- lockdep_assert_held(&ab_pci->window_lock);
-
- if (window != ab_pci->register_window) {
- iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
- ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
- ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
- ab_pci->register_window = window;
- }
-}
-
static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci)
{
u32 umac_window;
@@ -161,103 +92,6 @@ static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci)
ab_pci->ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
}
-static inline u32 ath11k_pci_get_window_start(struct ath11k_base *ab,
- u32 offset)
-{
- u32 window_start;
-
- /* If offset lies within DP register range, use 3rd window */
- if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
- window_start = 3 * ATH11K_PCI_WINDOW_START;
- /* If offset lies within CE register range, use 2nd window */
- else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < ATH11K_PCI_WINDOW_RANGE_MASK)
- window_start = 2 * ATH11K_PCI_WINDOW_START;
- else
- window_start = ATH11K_PCI_WINDOW_START;
-
- return window_start;
-}
-
-void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value)
-{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
- u32 window_start;
-
- /* for offset beyond BAR + 4K - 32, may
- * need to wakeup MHI to access.
- */
- if (ab->hw_params.wakeup_mhi &&
- test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
- offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
- mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
-
- if (offset < ATH11K_PCI_WINDOW_START) {
- iowrite32(value, ab->mem + offset);
- } else {
- if (ab->bus_params.static_window_map)
- window_start = ath11k_pci_get_window_start(ab, offset);
- else
- window_start = ATH11K_PCI_WINDOW_START;
-
- if (window_start == ATH11K_PCI_WINDOW_START) {
- spin_lock_bh(&ab_pci->window_lock);
- ath11k_pci_select_window(ab_pci, offset);
- iowrite32(value, ab->mem + window_start +
- (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
- spin_unlock_bh(&ab_pci->window_lock);
- } else {
- iowrite32(value, ab->mem + window_start +
- (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
- }
- }
-
- if (ab->hw_params.wakeup_mhi &&
- test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
- offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
- mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
-}
-
-u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset)
-{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
- u32 val, window_start;
-
- /* for offset beyond BAR + 4K - 32, may
- * need to wakeup MHI to access.
- */
- if (ab->hw_params.wakeup_mhi &&
- test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
- offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
- mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
-
- if (offset < ATH11K_PCI_WINDOW_START) {
- val = ioread32(ab->mem + offset);
- } else {
- if (ab->bus_params.static_window_map)
- window_start = ath11k_pci_get_window_start(ab, offset);
- else
- window_start = ATH11K_PCI_WINDOW_START;
-
- if (window_start == ATH11K_PCI_WINDOW_START) {
- spin_lock_bh(&ab_pci->window_lock);
- ath11k_pci_select_window(ab_pci, offset);
- val = ioread32(ab->mem + window_start +
- (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
- spin_unlock_bh(&ab_pci->window_lock);
- } else {
- val = ioread32(ab->mem + window_start +
- (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
- }
- }
-
- if (ab->hw_params.wakeup_mhi &&
- test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
- offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
- mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
-
- return val;
-}
-
static void ath11k_pci_soc_global_reset(struct ath11k_base *ab)
{
u32 val, delay;
@@ -454,462 +288,6 @@ static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on)
ath11k_mhi_set_mhictrl_reset(ab);
}
-int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector)
-{
- struct pci_dev *pci_dev = to_pci_dev(dev);
-
- return pci_irq_vector(pci_dev, vector);
-}
-
-void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
- u32 *msi_addr_hi)
-{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
- struct pci_dev *pci_dev = to_pci_dev(ab->dev);
-
- pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO,
- msi_addr_lo);
-
- if (test_bit(ATH11K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) {
- pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI,
- msi_addr_hi);
- } else {
- *msi_addr_hi = 0;
- }
-}
-
-int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ab_pci, char *user_name,
- int *num_vectors, u32 *user_base_data,
- u32 *base_vector)
-{
- struct ath11k_base *ab = ab_pci->ab;
- const struct ath11k_msi_config *msi_config = ab_pci->msi_config;
- int idx;
-
- for (idx = 0; idx < msi_config->total_users; idx++) {
- if (strcmp(user_name, msi_config->users[idx].name) == 0) {
- *num_vectors = msi_config->users[idx].num_vectors;
- *base_vector = msi_config->users[idx].base_vector;
- *user_base_data = *base_vector + ab_pci->msi_ep_base_data;
-
- ath11k_dbg(ab, ATH11K_DBG_PCI,
- "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n",
- user_name, *num_vectors, *user_base_data,
- *base_vector);
-
- return 0;
- }
- }
-
- ath11k_err(ab, "Failed to find MSI assignment for %s!\n", user_name);
-
- return -EINVAL;
-}
-
-void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx)
-{
- u32 i, msi_data_idx;
-
- for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) {
- if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
- continue;
-
- if (ce_id == i)
- break;
-
- msi_data_idx++;
- }
- *msi_idx = msi_data_idx;
-}
-
-int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
- int *num_vectors, u32 *user_base_data,
- u32 *base_vector)
-{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
-
- return ath11k_pci_get_user_msi_assignment(ab_pci, user_name,
- num_vectors, user_base_data,
- base_vector);
-}
-
-static void ath11k_pci_free_ext_irq(struct ath11k_base *ab)
-{
- int i, j;
-
- for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
- struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
-
- for (j = 0; j < irq_grp->num_irq; j++)
- free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);
-
- netif_napi_del(&irq_grp->napi);
- }
-}
-
-void ath11k_pci_free_irq(struct ath11k_base *ab)
-{
- int i, irq_idx;
-
- for (i = 0; i < ab->hw_params.ce_count; i++) {
- if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
- continue;
- irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
- free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);
- }
-
- ath11k_pci_free_ext_irq(ab);
-}
-
-static void ath11k_pci_ce_irq_enable(struct ath11k_base *ab, u16 ce_id)
-{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
- u32 irq_idx;
-
- /* In case of one MSI vector, we handle irq enable/disable in a
- * uniform way since we only have one irq
- */
- if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
- return;
-
- irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id;
- enable_irq(ab->irq_num[irq_idx]);
-}
-
-static void ath11k_pci_ce_irq_disable(struct ath11k_base *ab, u16 ce_id)
-{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
- u32 irq_idx;
-
- /* In case of one MSI vector, we handle irq enable/disable in a
- * uniform way since we only have one irq
- */
- if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
- return;
-
- irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id;
- disable_irq_nosync(ab->irq_num[irq_idx]);
-}
-
-static void ath11k_pci_ce_irqs_disable(struct ath11k_base *ab)
-{
- int i;
-
- clear_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
-
- for (i = 0; i < ab->hw_params.ce_count; i++) {
- if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
- continue;
- ath11k_pci_ce_irq_disable(ab, i);
- }
-}
-
-static void ath11k_pci_sync_ce_irqs(struct ath11k_base *ab)
-{
- int i;
- int irq_idx;
-
- for (i = 0; i < ab->hw_params.ce_count; i++) {
- if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
- continue;
-
- irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
- synchronize_irq(ab->irq_num[irq_idx]);
- }
-}
-
-static void ath11k_pci_ce_tasklet(struct tasklet_struct *t)
-{
- struct ath11k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq);
- int irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num;
-
- ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);
-
- enable_irq(ce_pipe->ab->irq_num[irq_idx]);
-}
-
-static irqreturn_t ath11k_pci_ce_interrupt_handler(int irq, void *arg)
-{
- struct ath11k_ce_pipe *ce_pipe = arg;
- struct ath11k_base *ab = ce_pipe->ab;
- int irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num;
-
- if (!test_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags))
- return IRQ_HANDLED;
-
- /* last interrupt received for this CE */
- ce_pipe->timestamp = jiffies;
-
- disable_irq_nosync(ab->irq_num[irq_idx]);
-
- tasklet_schedule(&ce_pipe->intr_tq);
-
- return IRQ_HANDLED;
-}
-
-static void ath11k_pci_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp)
-{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(irq_grp->ab);
- int i;
-
- /* In case of one MSI vector, we handle irq enable/disable
- * in a uniform way since we only have one irq
- */
- if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
- return;
-
- for (i = 0; i < irq_grp->num_irq; i++)
- disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
-}
-
-static void __ath11k_pci_ext_irq_disable(struct ath11k_base *sc)
-{
- int i;
-
- clear_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &sc->dev_flags);
-
- for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
- struct ath11k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i];
-
- ath11k_pci_ext_grp_disable(irq_grp);
-
- if (irq_grp->napi_enabled) {
- napi_synchronize(&irq_grp->napi);
- napi_disable(&irq_grp->napi);
- irq_grp->napi_enabled = false;
- }
- }
-}
-
-static void ath11k_pci_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp)
-{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(irq_grp->ab);
- int i;
-
- /* In case of one MSI vector, we handle irq enable/disable in a
- * uniform way since we only have one irq
- */
- if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
- return;
-
- for (i = 0; i < irq_grp->num_irq; i++)
- enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
-}
-
-void ath11k_pci_ext_irq_enable(struct ath11k_base *ab)
-{
- int i;
-
- set_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags);
-
- for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
- struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
-
- if (!irq_grp->napi_enabled) {
- napi_enable(&irq_grp->napi);
- irq_grp->napi_enabled = true;
- }
- ath11k_pci_ext_grp_enable(irq_grp);
- }
-}
-
-static void ath11k_pci_sync_ext_irqs(struct ath11k_base *ab)
-{
- int i, j, irq_idx;
-
- for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
- struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
-
- for (j = 0; j < irq_grp->num_irq; j++) {
- irq_idx = irq_grp->irqs[j];
- synchronize_irq(ab->irq_num[irq_idx]);
- }
- }
-}
-
-void ath11k_pci_ext_irq_disable(struct ath11k_base *ab)
-{
- __ath11k_pci_ext_irq_disable(ab);
- ath11k_pci_sync_ext_irqs(ab);
-}
-
-static int ath11k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget)
-{
- struct ath11k_ext_irq_grp *irq_grp = container_of(napi,
- struct ath11k_ext_irq_grp,
- napi);
- struct ath11k_base *ab = irq_grp->ab;
- int work_done;
- int i;
-
- work_done = ath11k_dp_service_srng(ab, irq_grp, budget);
- if (work_done < budget) {
- napi_complete_done(napi, work_done);
- for (i = 0; i < irq_grp->num_irq; i++)
- enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
- }
-
- if (work_done > budget)
- work_done = budget;
-
- return work_done;
-}
-
-static irqreturn_t ath11k_pci_ext_interrupt_handler(int irq, void *arg)
-{
- struct ath11k_ext_irq_grp *irq_grp = arg;
- struct ath11k_base *ab = irq_grp->ab;
- int i;
-
- if (!test_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags))
- return IRQ_HANDLED;
-
- ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq:%d\n", irq);
-
- /* last interrupt received for this group */
- irq_grp->timestamp = jiffies;
-
- for (i = 0; i < irq_grp->num_irq; i++)
- disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
-
- napi_schedule(&irq_grp->napi);
-
- return IRQ_HANDLED;
-}
-
-static int ath11k_pci_ext_irq_config(struct ath11k_base *ab)
-{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
- int i, j, ret, num_vectors = 0;
- u32 user_base_data = 0, base_vector = 0;
-
- ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab), "DP",
- &num_vectors,
- &user_base_data,
- &base_vector);
- if (ret < 0)
- return ret;
-
- for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
- struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
- u32 num_irq = 0;
-
- irq_grp->ab = ab;
- irq_grp->grp_id = i;
- init_dummy_netdev(&irq_grp->napi_ndev);
- netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
- ath11k_pci_ext_grp_napi_poll, NAPI_POLL_WEIGHT);
-
- if (ab->hw_params.ring_mask->tx[i] ||
- ab->hw_params.ring_mask->rx[i] ||
- ab->hw_params.ring_mask->rx_err[i] ||
- ab->hw_params.ring_mask->rx_wbm_rel[i] ||
- ab->hw_params.ring_mask->reo_status[i] ||
- ab->hw_params.ring_mask->rxdma2host[i] ||
- ab->hw_params.ring_mask->host2rxdma[i] ||
- ab->hw_params.ring_mask->rx_mon_status[i]) {
- num_irq = 1;
- }
-
- irq_grp->num_irq = num_irq;
- irq_grp->irqs[0] = ATH11K_PCI_IRQ_DP_OFFSET + i;
-
- for (j = 0; j < irq_grp->num_irq; j++) {
- int irq_idx = irq_grp->irqs[j];
- int vector = (i % num_vectors) + base_vector;
- int irq = ath11k_pci_get_msi_irq(ab->dev, vector);
-
- ab->irq_num[irq_idx] = irq;
-
- ath11k_dbg(ab, ATH11K_DBG_PCI,
- "irq:%d group:%d\n", irq, i);
-
- irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
- ret = request_irq(irq, ath11k_pci_ext_interrupt_handler,
- ab_pci->irq_flags,
- "DP_EXT_IRQ", irq_grp);
- if (ret) {
- ath11k_err(ab, "failed request irq %d: %d\n",
- vector, ret);
- return ret;
- }
- }
- ath11k_pci_ext_grp_disable(irq_grp);
- }
-
- return 0;
-}
-
-int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
- const struct cpumask *m)
-{
- if (test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
- return 0;
-
- return irq_set_affinity_hint(ab_pci->pdev->irq, m);
-}
-
-int ath11k_pci_config_irq(struct ath11k_base *ab)
-{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
- struct ath11k_ce_pipe *ce_pipe;
- u32 msi_data_start;
- u32 msi_data_count, msi_data_idx;
- u32 msi_irq_start;
- unsigned int msi_data;
- int irq, i, ret, irq_idx;
-
- ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab),
- "CE", &msi_data_count,
- &msi_data_start, &msi_irq_start);
- if (ret)
- return ret;
-
- ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));
- if (ret) {
- ath11k_err(ab, "failed to set irq affinity %d\n", ret);
- return ret;
- }
-
- /* Configure CE irqs */
- for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) {
- if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
- continue;
-
- msi_data = (msi_data_idx % msi_data_count) + msi_irq_start;
- irq = ath11k_pci_get_msi_irq(ab->dev, msi_data);
- ce_pipe = &ab->ce.ce_pipe[i];
-
- irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
-
- tasklet_setup(&ce_pipe->intr_tq, ath11k_pci_ce_tasklet);
-
- ret = request_irq(irq, ath11k_pci_ce_interrupt_handler,
- ab_pci->irq_flags, irq_name[irq_idx],
- ce_pipe);
- if (ret) {
- ath11k_err(ab, "failed to request irq %d: %d\n",
- irq_idx, ret);
- goto err_irq_affinity_cleanup;
- }
-
- ab->irq_num[irq_idx] = irq;
- msi_data_idx++;
-
- ath11k_pci_ce_irq_disable(ab, i);
- }
-
- ret = ath11k_pci_ext_irq_config(ab);
- if (ret)
- goto err_irq_affinity_cleanup;
-
- return 0;
-
-err_irq_affinity_cleanup:
- ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
- return ret;
-}
-
static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab)
{
struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
@@ -925,19 +303,6 @@ static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab)
&cfg->shadow_reg_v2_len);
}
-void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab)
-{
- int i;
-
- set_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
-
- for (i = 0; i < ab->hw_params.ce_count; i++) {
- if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
- continue;
- ath11k_pci_ce_irq_enable(ab, i);
- }
-}
-
static void ath11k_pci_msi_config(struct ath11k_pci *ab_pci, bool enable)
{
struct pci_dev *dev = ab_pci->pdev;
@@ -1137,13 +502,6 @@ static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci)
set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags);
}
-void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
-{
- if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags))
- pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
- ab_pci->link_ctl);
-}
-
static int ath11k_pci_power_up(struct ath11k_base *ab)
{
struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
@@ -1206,53 +564,6 @@ static int ath11k_pci_hif_resume(struct ath11k_base *ab)
return 0;
}
-static void ath11k_pci_kill_tasklets(struct ath11k_base *ab)
-{
- int i;
-
- for (i = 0; i < ab->hw_params.ce_count; i++) {
- struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
-
- if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
- continue;
-
- tasklet_kill(&ce_pipe->intr_tq);
- }
-}
-
-void ath11k_pci_ce_irq_disable_sync(struct ath11k_base *ab)
-{
- ath11k_pci_ce_irqs_disable(ab);
- ath11k_pci_sync_ce_irqs(ab);
- ath11k_pci_kill_tasklets(ab);
-}
-
-void ath11k_pci_stop(struct ath11k_base *ab)
-{
- ath11k_pci_ce_irq_disable_sync(ab);
- ath11k_ce_cleanup_pipes(ab);
-}
-
-int ath11k_pci_start(struct ath11k_base *ab)
-{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
-
- set_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
-
- /* TODO: for now don't restore ASPM in case of single MSI
- * vector as MHI register reading in M2 causes system hang.
- */
- if (test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
- ath11k_pci_aspm_restore(ab_pci);
- else
- ath11k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n");
-
- ath11k_pci_ce_irqs_enable(ab);
- ath11k_ce_rx_post_buf(ab);
-
- return 0;
-}
-
static void ath11k_pci_hif_ce_irq_enable(struct ath11k_base *ab)
{
ath11k_pci_ce_irqs_enable(ab);
@@ -1263,49 +574,6 @@ static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab)
ath11k_pci_ce_irq_disable_sync(ab);
}
-int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
- u8 *ul_pipe, u8 *dl_pipe)
-{
- const struct service_to_pipe *entry;
- bool ul_set = false, dl_set = false;
- int i;
-
- for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) {
- entry = &ab->hw_params.svc_to_ce_map[i];
-
- if (__le32_to_cpu(entry->service_id) != service_id)
- continue;
-
- switch (__le32_to_cpu(entry->pipedir)) {
- case PIPEDIR_NONE:
- break;
- case PIPEDIR_IN:
- WARN_ON(dl_set);
- *dl_pipe = __le32_to_cpu(entry->pipenum);
- dl_set = true;
- break;
- case PIPEDIR_OUT:
- WARN_ON(ul_set);
- *ul_pipe = __le32_to_cpu(entry->pipenum);
- ul_set = true;
- break;
- case PIPEDIR_INOUT:
- WARN_ON(dl_set);
- WARN_ON(ul_set);
- *dl_pipe = __le32_to_cpu(entry->pipenum);
- *ul_pipe = __le32_to_cpu(entry->pipenum);
- dl_set = true;
- ul_set = true;
- break;
- }
- }
-
- if (WARN_ON(!ul_set || !dl_set))
- return -ENOENT;
-
- return 0;
-}
-
static const struct ath11k_hif_ops ath11k_pci_hif_ops = {
.start = ath11k_pci_start,
.stop = ath11k_pci_stop,
diff --git a/drivers/net/wireless/ath/ath11k/pci.h b/drivers/net/wireless/ath/ath11k/pci.h
index 4869384..35c8152 100644
--- a/drivers/net/wireless/ath/ath11k/pci.h
+++ b/drivers/net/wireless/ath/ath11k/pci.h
@@ -53,21 +53,6 @@
#define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c
#define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4
-#define ATH11K_PCI_IRQ_CE0_OFFSET 3
-#define ATH11K_PCI_IRQ_DP_OFFSET 14
-
-#define ATH11K_PCI_WINDOW_ENABLE_BIT 0x40000000
-#define ATH11K_PCI_WINDOW_REG_ADDRESS 0x310c
-#define ATH11K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19)
-#define ATH11K_PCI_WINDOW_START 0x80000
-#define ATH11K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0)
-
-/* BAR0 + 4k is always accessible, and no
- * need to force wakeup.
- * 4K - 32 = 0xFE0
- */
-#define ATH11K_PCI_ACCESS_ALWAYS_OFF 0xFE0
-
struct ath11k_msi_user {
char *name;
int num_vectors;
@@ -113,30 +98,4 @@ static inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab)
return (struct ath11k_pci *)ab->drv_priv;
}
-int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ar_pci, char *user_name,
- int *num_vectors, u32 *user_base_data,
- u32 *base_vector);
-int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector);
-void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value);
-u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset);
-void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
- u32 *msi_addr_hi);
-void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx);
-void ath11k_pci_free_irq(struct ath11k_base *ab);
-int ath11k_pci_config_irq(struct ath11k_base *ab);
-void ath11k_pci_ext_irq_enable(struct ath11k_base *ab);
-void ath11k_pci_ext_irq_disable(struct ath11k_base *ab);
-void ath11k_pci_stop(struct ath11k_base *ab);
-int ath11k_pci_start(struct ath11k_base *ab);
-int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
- u8 *ul_pipe, u8 *dl_pipe);
-void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab);
-void ath11k_pci_ce_irq_disable_sync(struct ath11k_base *ab);
-int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
- int *num_vectors, u32 *user_base_data,
- u32 *base_vector);
-void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci);
-int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
- const struct cpumask *m);
-
#endif
diff --git a/drivers/net/wireless/ath/ath11k/pci_cmn.c b/drivers/net/wireless/ath/ath11k/pci_cmn.c
new file mode 100644
index 0000000..0e3a98b
--- /dev/null
+++ b/drivers/net/wireless/ath/ath11k/pci_cmn.c
@@ -0,0 +1,743 @@
+// SPDX-License-Identifier: BSD-3-Clause-Clear
+/*
+ * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/pci.h>
+#include "core.h"
+#include "pci_cmn.h"
+#include "debug.h"
+
+static const char *irq_name[ATH11K_IRQ_NUM_MAX] = {
+ "bhi",
+ "mhi-er0",
+ "mhi-er1",
+ "ce0",
+ "ce1",
+ "ce2",
+ "ce3",
+ "ce4",
+ "ce5",
+ "ce6",
+ "ce7",
+ "ce8",
+ "ce9",
+ "ce10",
+ "ce11",
+ "host2wbm-desc-feed",
+ "host2reo-re-injection",
+ "host2reo-command",
+ "host2rxdma-monitor-ring3",
+ "host2rxdma-monitor-ring2",
+ "host2rxdma-monitor-ring1",
+ "reo2ost-exception",
+ "wbm2host-rx-release",
+ "reo2host-status",
+ "reo2host-destination-ring4",
+ "reo2host-destination-ring3",
+ "reo2host-destination-ring2",
+ "reo2host-destination-ring1",
+ "rxdma2host-monitor-destination-mac3",
+ "rxdma2host-monitor-destination-mac2",
+ "rxdma2host-monitor-destination-mac1",
+ "ppdu-end-interrupts-mac3",
+ "ppdu-end-interrupts-mac2",
+ "ppdu-end-interrupts-mac1",
+ "rxdma2host-monitor-status-ring-mac3",
+ "rxdma2host-monitor-status-ring-mac2",
+ "rxdma2host-monitor-status-ring-mac1",
+ "host2rxdma-host-buf-ring-mac3",
+ "host2rxdma-host-buf-ring-mac2",
+ "host2rxdma-host-buf-ring-mac1",
+ "rxdma2host-destination-ring-mac3",
+ "rxdma2host-destination-ring-mac2",
+ "rxdma2host-destination-ring-mac1",
+ "host2tcl-input-ring4",
+ "host2tcl-input-ring3",
+ "host2tcl-input-ring2",
+ "host2tcl-input-ring1",
+ "wbm2host-tx-completions-ring3",
+ "wbm2host-tx-completions-ring2",
+ "wbm2host-tx-completions-ring1",
+ "tcl2host-status-ring",
+};
+
+void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
+{
+ if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags))
+ pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
+ ab_pci->link_ctl);
+}
+
+static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
+{
+ struct ath11k_base *ab = ab_pci->ab;
+
+ u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
+
+ lockdep_assert_held(&ab_pci->window_lock);
+
+ if (window != ab_pci->register_window) {
+ iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
+ ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
+ ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
+ ab_pci->register_window = window;
+ }
+}
+
+static inline u32 ath11k_pci_get_window_start(struct ath11k_base *ab,
+ u32 offset)
+{
+ u32 window_start;
+
+ /* If offset lies within DP register range, use 3rd window */
+ if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
+ window_start = 3 * ATH11K_PCI_WINDOW_START;
+ /* If offset lies within CE register range, use 2nd window */
+ else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < ATH11K_PCI_WINDOW_RANGE_MASK)
+ window_start = 2 * ATH11K_PCI_WINDOW_START;
+ else
+ window_start = ATH11K_PCI_WINDOW_START;
+
+ return window_start;
+}
+
+void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value)
+{
+ struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
+ u32 window_start;
+
+ /* for offset beyond BAR + 4K - 32, may
+ * need to wakeup MHI to access.
+ */
+ if (ab->hw_params.wakeup_mhi &&
+ test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
+ offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
+ mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
+
+ if (offset < ATH11K_PCI_WINDOW_START) {
+ iowrite32(value, ab->mem + offset);
+ } else {
+ if (ab->bus_params.static_window_map)
+ window_start = ath11k_pci_get_window_start(ab, offset);
+ else
+ window_start = ATH11K_PCI_WINDOW_START;
+
+ if (window_start == ATH11K_PCI_WINDOW_START) {
+ spin_lock_bh(&ab_pci->window_lock);
+ ath11k_pci_select_window(ab_pci, offset);
+ iowrite32(value, ab->mem + window_start +
+ (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
+ spin_unlock_bh(&ab_pci->window_lock);
+ } else {
+ iowrite32(value, ab->mem + window_start +
+ (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
+ }
+ }
+
+ if (ab->hw_params.wakeup_mhi &&
+ test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
+ offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
+ mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
+}
+
+u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset)
+{
+ struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
+ u32 val, window_start;
+
+ /* for offset beyond BAR + 4K - 32, may
+ * need to wakeup MHI to access.
+ */
+ if (ab->hw_params.wakeup_mhi &&
+ test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
+ offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
+ mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
+
+ if (offset < ATH11K_PCI_WINDOW_START) {
+ val = ioread32(ab->mem + offset);
+ } else {
+ if (ab->bus_params.static_window_map)
+ window_start = ath11k_pci_get_window_start(ab, offset);
+ else
+ window_start = ATH11K_PCI_WINDOW_START;
+
+ if (window_start == ATH11K_PCI_WINDOW_START) {
+ spin_lock_bh(&ab_pci->window_lock);
+ ath11k_pci_select_window(ab_pci, offset);
+ val = ioread32(ab->mem + window_start +
+ (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
+ spin_unlock_bh(&ab_pci->window_lock);
+ } else {
+ val = ioread32(ab->mem + window_start +
+ (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
+ }
+ }
+
+ if (ab->hw_params.wakeup_mhi &&
+ test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
+ offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
+ mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
+
+ return val;
+}
+
+int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector)
+{
+ struct pci_dev *pci_dev = to_pci_dev(dev);
+
+ return pci_irq_vector(pci_dev, vector);
+}
+
+void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
+ u32 *msi_addr_hi)
+{
+ struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
+ struct pci_dev *pci_dev = to_pci_dev(ab->dev);
+
+ pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO,
+ msi_addr_lo);
+
+ if (test_bit(ATH11K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) {
+ pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI,
+ msi_addr_hi);
+ } else {
+ *msi_addr_hi = 0;
+ }
+}
+
+int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ab_pci, char *user_name,
+ int *num_vectors, u32 *user_base_data,
+ u32 *base_vector)
+{
+ struct ath11k_base *ab = ab_pci->ab;
+ const struct ath11k_msi_config *msi_config = ab_pci->msi_config;
+ int idx;
+
+ for (idx = 0; idx < msi_config->total_users; idx++) {
+ if (strcmp(user_name, msi_config->users[idx].name) == 0) {
+ *num_vectors = msi_config->users[idx].num_vectors;
+ *base_vector = msi_config->users[idx].base_vector;
+ *user_base_data = *base_vector + ab_pci->msi_ep_base_data;
+
+ ath11k_dbg(ab, ATH11K_DBG_PCI,
+ "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n",
+ user_name, *num_vectors, *user_base_data,
+ *base_vector);
+
+ return 0;
+ }
+ }
+
+ ath11k_err(ab, "Failed to find MSI assignment for %s!\n", user_name);
+
+ return -EINVAL;
+}
+
+void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx)
+{
+ u32 i, msi_data_idx;
+
+ for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) {
+ if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
+ continue;
+
+ if (ce_id == i)
+ break;
+
+ msi_data_idx++;
+ }
+ *msi_idx = msi_data_idx;
+}
+
+int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
+ int *num_vectors, u32 *user_base_data,
+ u32 *base_vector)
+{
+ struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
+
+ return ath11k_pci_get_user_msi_assignment(ab_pci, user_name,
+ num_vectors, user_base_data,
+ base_vector);
+}
+
+static void ath11k_pci_free_ext_irq(struct ath11k_base *ab)
+{
+ int i, j;
+
+ for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
+ struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
+
+ for (j = 0; j < irq_grp->num_irq; j++)
+ free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);
+
+ netif_napi_del(&irq_grp->napi);
+ }
+}
+
+void ath11k_pci_free_irq(struct ath11k_base *ab)
+{
+ int i, irq_idx;
+
+ for (i = 0; i < ab->hw_params.ce_count; i++) {
+ if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
+ continue;
+ irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
+ free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);
+ }
+
+ ath11k_pci_free_ext_irq(ab);
+}
+
+static void ath11k_pci_ce_irq_enable(struct ath11k_base *ab, u16 ce_id)
+{
+ struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
+ u32 irq_idx;
+
+ /* In case of one MSI vector, we handle irq enable/disable in a
+ * uniform way since we only have one irq
+ */
+ if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
+ return;
+
+ irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id;
+ enable_irq(ab->irq_num[irq_idx]);
+}
+
+static void ath11k_pci_ce_irq_disable(struct ath11k_base *ab, u16 ce_id)
+{
+ struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
+ u32 irq_idx;
+
+ /* In case of one MSI vector, we handle irq enable/disable in a
+ * uniform way since we only have one irq
+ */
+ if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
+ return;
+
+ irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id;
+ disable_irq_nosync(ab->irq_num[irq_idx]);
+}
+
+static void ath11k_pci_ce_irqs_disable(struct ath11k_base *ab)
+{
+ int i;
+
+ clear_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
+
+ for (i = 0; i < ab->hw_params.ce_count; i++) {
+ if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
+ continue;
+ ath11k_pci_ce_irq_disable(ab, i);
+ }
+}
+
+static void ath11k_pci_sync_ce_irqs(struct ath11k_base *ab)
+{
+ int i;
+ int irq_idx;
+
+ for (i = 0; i < ab->hw_params.ce_count; i++) {
+ if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
+ continue;
+
+ irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
+ synchronize_irq(ab->irq_num[irq_idx]);
+ }
+}
+
+static void ath11k_pci_ce_tasklet(struct tasklet_struct *t)
+{
+ struct ath11k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq);
+ int irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num;
+
+ ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);
+
+ enable_irq(ce_pipe->ab->irq_num[irq_idx]);
+}
+
+static irqreturn_t ath11k_pci_ce_interrupt_handler(int irq, void *arg)
+{
+ struct ath11k_ce_pipe *ce_pipe = arg;
+ struct ath11k_base *ab = ce_pipe->ab;
+ int irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num;
+
+ if (!test_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags))
+ return IRQ_HANDLED;
+
+ /* last interrupt received for this CE */
+ ce_pipe->timestamp = jiffies;
+
+ disable_irq_nosync(ab->irq_num[irq_idx]);
+
+ tasklet_schedule(&ce_pipe->intr_tq);
+
+ return IRQ_HANDLED;
+}
+
+static void ath11k_pci_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp)
+{
+ struct ath11k_pci *ab_pci = ath11k_pci_priv(irq_grp->ab);
+ int i;
+
+ /* In case of one MSI vector, we handle irq enable/disable
+ * in a uniform way since we only have one irq
+ */
+ if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
+ return;
+
+ for (i = 0; i < irq_grp->num_irq; i++)
+ disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
+}
+
+static void __ath11k_pci_ext_irq_disable(struct ath11k_base *sc)
+{
+ int i;
+
+ clear_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &sc->dev_flags);
+
+ for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
+ struct ath11k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i];
+
+ ath11k_pci_ext_grp_disable(irq_grp);
+
+ if (irq_grp->napi_enabled) {
+ napi_synchronize(&irq_grp->napi);
+ napi_disable(&irq_grp->napi);
+ irq_grp->napi_enabled = false;
+ }
+ }
+}
+
+static void ath11k_pci_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp)
+{
+ struct ath11k_pci *ab_pci = ath11k_pci_priv(irq_grp->ab);
+ int i;
+
+ /* In case of one MSI vector, we handle irq enable/disable in a
+ * uniform way since we only have one irq
+ */
+ if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
+ return;
+
+ for (i = 0; i < irq_grp->num_irq; i++)
+ enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
+}
+
+void ath11k_pci_ext_irq_enable(struct ath11k_base *ab)
+{
+ int i;
+
+ set_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags);
+
+ for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
+ struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
+
+ if (!irq_grp->napi_enabled) {
+ napi_enable(&irq_grp->napi);
+ irq_grp->napi_enabled = true;
+ }
+ ath11k_pci_ext_grp_enable(irq_grp);
+ }
+}
+
+static void ath11k_pci_sync_ext_irqs(struct ath11k_base *ab)
+{
+ int i, j, irq_idx;
+
+ for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
+ struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
+
+ for (j = 0; j < irq_grp->num_irq; j++) {
+ irq_idx = irq_grp->irqs[j];
+ synchronize_irq(ab->irq_num[irq_idx]);
+ }
+ }
+}
+
+void ath11k_pci_ext_irq_disable(struct ath11k_base *ab)
+{
+ __ath11k_pci_ext_irq_disable(ab);
+ ath11k_pci_sync_ext_irqs(ab);
+}
+
+static int ath11k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget)
+{
+ struct ath11k_ext_irq_grp *irq_grp = container_of(napi,
+ struct ath11k_ext_irq_grp,
+ napi);
+ struct ath11k_base *ab = irq_grp->ab;
+ int work_done;
+ int i;
+
+ work_done = ath11k_dp_service_srng(ab, irq_grp, budget);
+ if (work_done < budget) {
+ napi_complete_done(napi, work_done);
+ for (i = 0; i < irq_grp->num_irq; i++)
+ enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
+ }
+
+ if (work_done > budget)
+ work_done = budget;
+
+ return work_done;
+}
+
+static irqreturn_t ath11k_pci_ext_interrupt_handler(int irq, void *arg)
+{
+ struct ath11k_ext_irq_grp *irq_grp = arg;
+ struct ath11k_base *ab = irq_grp->ab;
+ int i;
+
+ if (!test_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags))
+ return IRQ_HANDLED;
+
+ ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq:%d\n", irq);
+
+ /* last interrupt received for this group */
+ irq_grp->timestamp = jiffies;
+
+ for (i = 0; i < irq_grp->num_irq; i++)
+ disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
+
+ napi_schedule(&irq_grp->napi);
+
+ return IRQ_HANDLED;
+}
+
+static int ath11k_pci_ext_irq_config(struct ath11k_base *ab)
+{
+ struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
+ int i, j, ret, num_vectors = 0;
+ u32 user_base_data = 0, base_vector = 0;
+
+ ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab), "DP",
+ &num_vectors,
+ &user_base_data,
+ &base_vector);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
+ struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
+ u32 num_irq = 0;
+
+ irq_grp->ab = ab;
+ irq_grp->grp_id = i;
+ init_dummy_netdev(&irq_grp->napi_ndev);
+ netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
+ ath11k_pci_ext_grp_napi_poll, NAPI_POLL_WEIGHT);
+
+ if (ab->hw_params.ring_mask->tx[i] ||
+ ab->hw_params.ring_mask->rx[i] ||
+ ab->hw_params.ring_mask->rx_err[i] ||
+ ab->hw_params.ring_mask->rx_wbm_rel[i] ||
+ ab->hw_params.ring_mask->reo_status[i] ||
+ ab->hw_params.ring_mask->rxdma2host[i] ||
+ ab->hw_params.ring_mask->host2rxdma[i] ||
+ ab->hw_params.ring_mask->rx_mon_status[i]) {
+ num_irq = 1;
+ }
+
+ irq_grp->num_irq = num_irq;
+ irq_grp->irqs[0] = ATH11K_PCI_IRQ_DP_OFFSET + i;
+
+ for (j = 0; j < irq_grp->num_irq; j++) {
+ int irq_idx = irq_grp->irqs[j];
+ int vector = (i % num_vectors) + base_vector;
+ int irq = ath11k_pci_get_msi_irq(ab->dev, vector);
+
+ ab->irq_num[irq_idx] = irq;
+
+ ath11k_dbg(ab, ATH11K_DBG_PCI,
+ "irq:%d group:%d\n", irq, i);
+
+ irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
+ ret = request_irq(irq, ath11k_pci_ext_interrupt_handler,
+ ab_pci->irq_flags,
+ "DP_EXT_IRQ", irq_grp);
+ if (ret) {
+ ath11k_err(ab, "failed request irq %d: %d\n",
+ vector, ret);
+ return ret;
+ }
+ }
+ ath11k_pci_ext_grp_disable(irq_grp);
+ }
+
+ return 0;
+}
+
+int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
+ const struct cpumask *m)
+{
+ if (test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
+ return 0;
+
+ return irq_set_affinity_hint(ab_pci->pdev->irq, m);
+}
+
+int ath11k_pci_config_irq(struct ath11k_base *ab)
+{
+ struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
+ struct ath11k_ce_pipe *ce_pipe;
+ u32 msi_data_start;
+ u32 msi_data_count, msi_data_idx;
+ u32 msi_irq_start;
+ unsigned int msi_data;
+ int irq, i, ret, irq_idx;
+
+ ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab),
+ "CE", &msi_data_count,
+ &msi_data_start, &msi_irq_start);
+ if (ret)
+ return ret;
+
+ ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));
+ if (ret) {
+ ath11k_err(ab, "failed to set irq affinity %d\n", ret);
+ return ret;
+ }
+
+ /* Configure CE irqs */
+ for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) {
+ if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
+ continue;
+
+ msi_data = (msi_data_idx % msi_data_count) + msi_irq_start;
+ irq = ath11k_pci_get_msi_irq(ab->dev, msi_data);
+ ce_pipe = &ab->ce.ce_pipe[i];
+
+ irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
+
+ tasklet_setup(&ce_pipe->intr_tq, ath11k_pci_ce_tasklet);
+
+ ret = request_irq(irq, ath11k_pci_ce_interrupt_handler,
+ ab_pci->irq_flags, irq_name[irq_idx],
+ ce_pipe);
+ if (ret) {
+ ath11k_err(ab, "failed to request irq %d: %d\n",
+ irq_idx, ret);
+ goto err_irq_affinity_cleanup;
+ }
+
+ ab->irq_num[irq_idx] = irq;
+ msi_data_idx++;
+
+ ath11k_pci_ce_irq_disable(ab, i);
+ }
+
+ ret = ath11k_pci_ext_irq_config(ab);
+ if (ret)
+ goto err_irq_affinity_cleanup;
+
+ return 0;
+
+err_irq_affinity_cleanup:
+ ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
+ return ret;
+}
+
+void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab)
+{
+ int i;
+
+ set_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
+
+ for (i = 0; i < ab->hw_params.ce_count; i++) {
+ if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
+ continue;
+ ath11k_pci_ce_irq_enable(ab, i);
+ }
+}
+
+static void ath11k_pci_kill_tasklets(struct ath11k_base *ab)
+{
+ int i;
+
+ for (i = 0; i < ab->hw_params.ce_count; i++) {
+ struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
+
+ if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
+ continue;
+
+ tasklet_kill(&ce_pipe->intr_tq);
+ }
+}
+
+void ath11k_pci_ce_irq_disable_sync(struct ath11k_base *ab)
+{
+ ath11k_pci_ce_irqs_disable(ab);
+ ath11k_pci_sync_ce_irqs(ab);
+ ath11k_pci_kill_tasklets(ab);
+}
+
+void ath11k_pci_stop(struct ath11k_base *ab)
+{
+ ath11k_pci_ce_irq_disable_sync(ab);
+ ath11k_ce_cleanup_pipes(ab);
+}
+
+int ath11k_pci_start(struct ath11k_base *ab)
+{
+ struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
+
+ set_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
+
+ /* TODO: for now don't restore ASPM in case of single MSI
+ * vector as MHI register reading in M2 causes system hang.
+ */
+ if (test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
+ ath11k_pci_aspm_restore(ab_pci);
+ else
+ ath11k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n");
+
+ ath11k_pci_ce_irqs_enable(ab);
+ ath11k_ce_rx_post_buf(ab);
+
+ return 0;
+}
+
+int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
+ u8 *ul_pipe, u8 *dl_pipe)
+{
+ const struct service_to_pipe *entry;
+ bool ul_set = false, dl_set = false;
+ int i;
+
+ for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) {
+ entry = &ab->hw_params.svc_to_ce_map[i];
+
+ if (__le32_to_cpu(entry->service_id) != service_id)
+ continue;
+
+ switch (__le32_to_cpu(entry->pipedir)) {
+ case PIPEDIR_NONE:
+ break;
+ case PIPEDIR_IN:
+ WARN_ON(dl_set);
+ *dl_pipe = __le32_to_cpu(entry->pipenum);
+ dl_set = true;
+ break;
+ case PIPEDIR_OUT:
+ WARN_ON(ul_set);
+ *ul_pipe = __le32_to_cpu(entry->pipenum);
+ ul_set = true;
+ break;
+ case PIPEDIR_INOUT:
+ WARN_ON(dl_set);
+ WARN_ON(ul_set);
+ *dl_pipe = __le32_to_cpu(entry->pipenum);
+ *ul_pipe = __le32_to_cpu(entry->pipenum);
+ dl_set = true;
+ ul_set = true;
+ break;
+ }
+ }
+
+ if (WARN_ON(!ul_set || !dl_set))
+ return -ENOENT;
+
+ return 0;
+}
diff --git a/drivers/net/wireless/ath/ath11k/pci_cmn.h b/drivers/net/wireless/ath/ath11k/pci_cmn.h
new file mode 100644
index 0000000..5fb1cf1
--- /dev/null
+++ b/drivers/net/wireless/ath/ath11k/pci_cmn.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: BSD-3-Clause-Clear */
+/*
+ * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _ATH11K_PCI_CMN_H
+#define _ATH11K_PCI_CMN_H
+
+#include "core.h"
+#include "pci.h"
+
+#define ATH11K_PCI_IRQ_CE0_OFFSET 3
+#define ATH11K_PCI_IRQ_DP_OFFSET 14
+
+#define ATH11K_PCI_WINDOW_ENABLE_BIT 0x40000000
+#define ATH11K_PCI_WINDOW_REG_ADDRESS 0x310c
+#define ATH11K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19)
+#define ATH11K_PCI_WINDOW_START 0x80000
+#define ATH11K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0)
+
+/* BAR0 + 4k is always accessible, and no
+ * need to force wakeup.
+ * 4K - 32 = 0xFE0
+ */
+#define ATH11K_PCI_ACCESS_ALWAYS_OFF 0xFE0
+
+int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ar_pci, char *user_name,
+ int *num_vectors, u32 *user_base_data,
+ u32 *base_vector);
+int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector);
+void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value);
+u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset);
+void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
+ u32 *msi_addr_hi);
+void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx);
+void ath11k_pci_free_irq(struct ath11k_base *ab);
+int ath11k_pci_config_irq(struct ath11k_base *ab);
+void ath11k_pci_ext_irq_enable(struct ath11k_base *ab);
+void ath11k_pci_ext_irq_disable(struct ath11k_base *ab);
+void ath11k_pci_stop(struct ath11k_base *ab);
+int ath11k_pci_start(struct ath11k_base *ab);
+int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
+ u8 *ul_pipe, u8 *dl_pipe);
+void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab);
+void ath11k_pci_ce_irq_disable_sync(struct ath11k_base *ab);
+int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
+ int *num_vectors, u32 *user_base_data,
+ u32 *base_vector);
+void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci);
+int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
+ const struct cpumask *m);
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCH v2 02/19] ath11k: Refactor PCI code to support hybrid bus devices
2022-01-16 12:46 ` [PATCH v2 02/19] ath11k: Refactor PCI code to support hybrid bus devices Manikanta Pubbisetty
@ 2022-01-28 10:16 ` Kalle Valo
2022-02-25 5:50 ` Manikanta Pubbisetty
2022-01-28 12:13 ` Kalle Valo
1 sibling, 1 reply; 49+ messages in thread
From: Kalle Valo @ 2022-01-28 10:16 UTC (permalink / raw)
To: Manikanta Pubbisetty; +Cc: ath11k, linux-wireless, devicetree, robh
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
> Unlike other ATH11K PCIe devices which are enumerated by APSS
> processor (Application Processor SubSystem), WCN6750 gets
> enumerated by the WPSS Q6 processor (Wireless Processor SubSystem);
> In simple terms, though WCN6750 is PCIe device, it is not attached
> to the APSS processor, APSS will not know of such a device being
> present in the system and therefore WCN6750 will be registered as
> a platform device to the kernel core like other supported AHB
> devices.
>
> WCN6750 uses both AHB and PCI APIs for it's operation, it uses
> AHB APIs for device probe/boot and PCI APIs for device setup
> and register accesses; Because of this nature, it is referred
> as a hybrid bus device.
>
> Refactor PCI code to support hybrid bus devices like WCN6750.
>
> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>
> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
[...]
> --- a/drivers/net/wireless/ath/ath11k/Makefile
> +++ b/drivers/net/wireless/ath/ath11k/Makefile
> @@ -29,7 +29,7 @@ obj-$(CONFIG_ATH11K_AHB) += ath11k_ahb.o
> ath11k_ahb-y += ahb.o
>
> obj-$(CONFIG_ATH11K_PCI) += ath11k_pci.o
> -ath11k_pci-y += mhi.o pci.o
> +ath11k_pci-y += mhi.o pci.o pci_cmn.o
So the end result looks like this:
obj-$(CONFIG_ATH11K_AHB) += ath11k_ahb.o
ath11k_ahb-y += ahb.o pci_cmn.o
obj-$(CONFIG_ATH11K_PCI) += ath11k_pci.o
ath11k_pci-y += mhi.o pci.o pci_cmn.o
Linking pci_cmn.o to both ath11k_pci.ko and ath11k_ahb.ko looks wrong.
Does that even compile if ath11k is linked to the kernel, eg. with
allyesconfig?
One way to solve is to link pci_cmn.o to ath11k.ko. But for another
approach, for a long time I have been thinking about what's the point to
have separate ath11k_pci.ko and ath11k_ahb.ko modules?,They are very
small anyway compared to ath11k.ko. So my ideais that should we have
just one ath11k.ko module, it contains all AHB and PCI code as well, and
ath11k_pci.ko and ath11k_ahb.ko would not be created anymore. It would
simplify things a bit, especially here.
Thoughts?
--
https://patchwork.kernel.org/project/linux-wireless/list/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 02/19] ath11k: Refactor PCI code to support hybrid bus devices
2022-01-28 10:16 ` Kalle Valo
@ 2022-02-25 5:50 ` Manikanta Pubbisetty
2022-03-08 6:00 ` Manikanta Pubbisetty
0 siblings, 1 reply; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-02-25 5:50 UTC (permalink / raw)
To: Kalle Valo; +Cc: ath11k, linux-wireless, devicetree, robh
On 1/28/2022 3:46 PM, Kalle Valo wrote:
> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>
>> Unlike other ATH11K PCIe devices which are enumerated by APSS
>> processor (Application Processor SubSystem), WCN6750 gets
>> enumerated by the WPSS Q6 processor (Wireless Processor SubSystem);
>> In simple terms, though WCN6750 is PCIe device, it is not attached
>> to the APSS processor, APSS will not know of such a device being
>> present in the system and therefore WCN6750 will be registered as
>> a platform device to the kernel core like other supported AHB
>> devices.
>>
>> WCN6750 uses both AHB and PCI APIs for it's operation, it uses
>> AHB APIs for device probe/boot and PCI APIs for device setup
>> and register accesses; Because of this nature, it is referred
>> as a hybrid bus device.
>>
>> Refactor PCI code to support hybrid bus devices like WCN6750.
>>
>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>
>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>
> [...]
>
>> --- a/drivers/net/wireless/ath/ath11k/Makefile
>> +++ b/drivers/net/wireless/ath/ath11k/Makefile
>> @@ -29,7 +29,7 @@ obj-$(CONFIG_ATH11K_AHB) += ath11k_ahb.o
>> ath11k_ahb-y += ahb.o
>>
>> obj-$(CONFIG_ATH11K_PCI) += ath11k_pci.o
>> -ath11k_pci-y += mhi.o pci.o
>> +ath11k_pci-y += mhi.o pci.o pci_cmn.o
>
> So the end result looks like this:
>
> obj-$(CONFIG_ATH11K_AHB) += ath11k_ahb.o
> ath11k_ahb-y += ahb.o pci_cmn.o
>
> obj-$(CONFIG_ATH11K_PCI) += ath11k_pci.o
> ath11k_pci-y += mhi.o pci.o pci_cmn.o
>
> Linking pci_cmn.o to both ath11k_pci.ko and ath11k_ahb.ko looks wrong.
> Does that even compile if ath11k is linked to the kernel, eg. with
> allyesconfig?
>
I did try compiling the kernel with allyesconfig after your comment,
compilation went through without any hiccups.
> One way to solve is to link pci_cmn.o to ath11k.ko. But for another
> approach, for a long time I have been thinking about what's the point to
> have separate ath11k_pci.ko and ath11k_ahb.ko modules?,They are very
> small anyway compared to ath11k.ko. So my ideais that should we have
> just one ath11k.ko module, it contains all AHB and PCI code as well, and
> ath11k_pci.ko and ath11k_ahb.ko would not be created anymore. It would
> simplify things a bit, especially here.
>
> Thoughts?
>
I see some concerns going with single module combining both AHB and PCI
modules into ath11k.ko
1) AHB and PCI drivers make use of completely different kernel
frameworks, for example AHB driver needs remoteproc APIs for booting and
require CONFIG_REMOTEPROC to be compiled in to the kernel. Similarly,
PCI driver needs MHI APIs and also dependent on CONFIG_PCI. Both MHI and
PCI bus frameworks need to be compiled for PCI to work. If we club all
of this into single module, I see that unnecessarily additional modules
will be compiled into the kernel which IMO is not so good idea.
2) Secondly, there is high chance of writing bad code all over the
driver. For example, there are chances that developers put AHB/PCI
specific code all over the driver creating a big mess.
Though this can be avoided with stringent code review, but why to
give the chance.
Though AHB and PCI drivers are smaller in size, IMHO let AHB and PCI be
independent drivers, code looks cleaner and properly segregated by
keeping them as it is today.
Regarding the compilation of PCI common code, shall we move it into
ath11k.ko? What is your opinion on this.
Thanks,
Manikanta
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 02/19] ath11k: Refactor PCI code to support hybrid bus devices
2022-02-25 5:50 ` Manikanta Pubbisetty
@ 2022-03-08 6:00 ` Manikanta Pubbisetty
0 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-03-08 6:00 UTC (permalink / raw)
To: Kalle Valo; +Cc: ath11k, linux-wireless, devicetree, robh
On 2/25/2022 11:20 AM, Manikanta Pubbisetty wrote:
> On 1/28/2022 3:46 PM, Kalle Valo wrote:
>> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>>
>>> Unlike other ATH11K PCIe devices which are enumerated by APSS
>>> processor (Application Processor SubSystem), WCN6750 gets
>>> enumerated by the WPSS Q6 processor (Wireless Processor SubSystem);
>>> In simple terms, though WCN6750 is PCIe device, it is not attached
>>> to the APSS processor, APSS will not know of such a device being
>>> present in the system and therefore WCN6750 will be registered as
>>> a platform device to the kernel core like other supported AHB
>>> devices.
>>>
>>> WCN6750 uses both AHB and PCI APIs for it's operation, it uses
>>> AHB APIs for device probe/boot and PCI APIs for device setup
>>> and register accesses; Because of this nature, it is referred
>>> as a hybrid bus device.
>>>
>>> Refactor PCI code to support hybrid bus devices like WCN6750.
>>>
>>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>>> Tested-on: WCN6855 hw2.0 PCI
>>> WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>>
>>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>>
>> [...]
>>
>>> --- a/drivers/net/wireless/ath/ath11k/Makefile
>>> +++ b/drivers/net/wireless/ath/ath11k/Makefile
>>> @@ -29,7 +29,7 @@ obj-$(CONFIG_ATH11K_AHB) += ath11k_ahb.o
>>> ath11k_ahb-y += ahb.o
>>> obj-$(CONFIG_ATH11K_PCI) += ath11k_pci.o
>>> -ath11k_pci-y += mhi.o pci.o
>>> +ath11k_pci-y += mhi.o pci.o pci_cmn.o
>>
>> So the end result looks like this:
>>
>> obj-$(CONFIG_ATH11K_AHB) += ath11k_ahb.o
>> ath11k_ahb-y += ahb.o pci_cmn.o
>>
>> obj-$(CONFIG_ATH11K_PCI) += ath11k_pci.o
>> ath11k_pci-y += mhi.o pci.o pci_cmn.o
>>
>> Linking pci_cmn.o to both ath11k_pci.ko and ath11k_ahb.ko looks wrong.
>> Does that even compile if ath11k is linked to the kernel, eg. with
>> allyesconfig?
>>
>
> I did try compiling the kernel with allyesconfig after your comment,
> compilation went through without any hiccups.
>
>> One way to solve is to link pci_cmn.o to ath11k.ko. But for another
>> approach, for a long time I have been thinking about what's the point to
>> have separate ath11k_pci.ko and ath11k_ahb.ko modules?,They are very
>> small anyway compared to ath11k.ko. So my ideais that should we have
>> just one ath11k.ko module, it contains all AHB and PCI code as well, and
>> ath11k_pci.ko and ath11k_ahb.ko would not be created anymore. It would
>> simplify things a bit, especially here.
>>
>> Thoughts?
>>
>
> I see some concerns going with single module combining both AHB and PCI
> modules into ath11k.ko
>
> 1) AHB and PCI drivers make use of completely different kernel
> frameworks, for example AHB driver needs remoteproc APIs for booting and
> require CONFIG_REMOTEPROC to be compiled in to the kernel. Similarly,
> PCI driver needs MHI APIs and also dependent on CONFIG_PCI. Both MHI and
> PCI bus frameworks need to be compiled for PCI to work. If we club all
> of this into single module, I see that unnecessarily additional modules
> will be compiled into the kernel which IMO is not so good idea.
>
>
> 2) Secondly, there is high chance of writing bad code all over the
> driver. For example, there are chances that developers put AHB/PCI
> specific code all over the driver creating a big mess.
> Though this can be avoided with stringent code review, but why to
> give the chance.
>
> Though AHB and PCI drivers are smaller in size, IMHO let AHB and PCI be
> independent drivers, code looks cleaner and properly segregated by
> keeping them as it is today.
>
> Regarding the compilation of PCI common code, shall we move it into
> ath11k.ko? What is your opinion on this.
>
Hi Kalle,
Any thoughts about the idea proposed?
Thanks,
Manikanta
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 02/19] ath11k: Refactor PCI code to support hybrid bus devices
2022-01-16 12:46 ` [PATCH v2 02/19] ath11k: Refactor PCI code to support hybrid bus devices Manikanta Pubbisetty
2022-01-28 10:16 ` Kalle Valo
@ 2022-01-28 12:13 ` Kalle Valo
2022-02-21 8:04 ` Manikanta Pubbisetty
1 sibling, 1 reply; 49+ messages in thread
From: Kalle Valo @ 2022-01-28 12:13 UTC (permalink / raw)
To: Manikanta Pubbisetty; +Cc: ath11k, linux-wireless, devicetree, robh
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
> Unlike other ATH11K PCIe devices which are enumerated by APSS
> processor (Application Processor SubSystem), WCN6750 gets
> enumerated by the WPSS Q6 processor (Wireless Processor SubSystem);
> In simple terms, though WCN6750 is PCIe device, it is not attached
> to the APSS processor, APSS will not know of such a device being
> present in the system and therefore WCN6750 will be registered as
> a platform device to the kernel core like other supported AHB
> devices.
>
> WCN6750 uses both AHB and PCI APIs for it's operation, it uses
> AHB APIs for device probe/boot and PCI APIs for device setup
> and register accesses; Because of this nature, it is referred
> as a hybrid bus device.
>
> Refactor PCI code to support hybrid bus devices like WCN6750.
>
> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>
> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
[...]
> --- /dev/null
> +++ b/drivers/net/wireless/ath/ath11k/pci_cmn.c
[...]
> +static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
> +{
> + struct ath11k_base *ab = ab_pci->ab;
> +
> + u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
> +
> + lockdep_assert_held(&ab_pci->window_lock);
> +
> + if (window != ab_pci->register_window) {
> + iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
> + ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
> + ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
> + ab_pci->register_window = window;
> + }
> +}
So the style used in ath11k is ath11k_<filename>_foo, so that a function
ath11k_pci_foo() should be in pci.c. This patch is now breaking that
style. Maybe pci_cmn.c should renamed to cpci.c, pcic.c or something
like that? Then the function prefix could be ath11k_cpci_, ath11k_pcic_
or similar.
--
https://patchwork.kernel.org/project/linux-wireless/list/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 02/19] ath11k: Refactor PCI code to support hybrid bus devices
2022-01-28 12:13 ` Kalle Valo
@ 2022-02-21 8:04 ` Manikanta Pubbisetty
2022-02-21 9:19 ` Kalle Valo
0 siblings, 1 reply; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-02-21 8:04 UTC (permalink / raw)
To: Kalle Valo; +Cc: ath11k, linux-wireless, devicetree, robh
On 1/28/2022 5:43 PM, Kalle Valo wrote:
> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>
>> Unlike other ATH11K PCIe devices which are enumerated by APSS
>> processor (Application Processor SubSystem), WCN6750 gets
>> enumerated by the WPSS Q6 processor (Wireless Processor SubSystem);
>> In simple terms, though WCN6750 is PCIe device, it is not attached
>> to the APSS processor, APSS will not know of such a device being
>> present in the system and therefore WCN6750 will be registered as
>> a platform device to the kernel core like other supported AHB
>> devices.
>>
>> WCN6750 uses both AHB and PCI APIs for it's operation, it uses
>> AHB APIs for device probe/boot and PCI APIs for device setup
>> and register accesses; Because of this nature, it is referred
>> as a hybrid bus device.
>>
>> Refactor PCI code to support hybrid bus devices like WCN6750.
>>
>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>
>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>
> [...]
>
>> --- /dev/null
>> +++ b/drivers/net/wireless/ath/ath11k/pci_cmn.c
>
> [...]
>
>> +static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
>> +{
>> + struct ath11k_base *ab = ab_pci->ab;
>> +
>> + u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
>> +
>> + lockdep_assert_held(&ab_pci->window_lock);
>> +
>> + if (window != ab_pci->register_window) {
>> + iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
>> + ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
>> + ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
>> + ab_pci->register_window = window;
>> + }
>> +}
>
> So the style used in ath11k is ath11k_<filename>_foo, so that a function
> ath11k_pci_foo() should be in pci.c. This patch is now breaking that
> style. Maybe pci_cmn.c should renamed to cpci.c, pcic.c or something
> like that? Then the function prefix could be ath11k_cpci_, ath11k_pcic_
> or similar.
>
Makes sense, pcic.c and ath11k_pcic_* looks better, I'll make these changes.
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 02/19] ath11k: Refactor PCI code to support hybrid bus devices
2022-02-21 8:04 ` Manikanta Pubbisetty
@ 2022-02-21 9:19 ` Kalle Valo
2022-02-21 10:19 ` Manikanta Pubbisetty
0 siblings, 1 reply; 49+ messages in thread
From: Kalle Valo @ 2022-02-21 9:19 UTC (permalink / raw)
To: Manikanta Pubbisetty; +Cc: ath11k, linux-wireless, devicetree, robh
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
> On 1/28/2022 5:43 PM, Kalle Valo wrote:
>> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>>
>>> Unlike other ATH11K PCIe devices which are enumerated by APSS
>>> processor (Application Processor SubSystem), WCN6750 gets
>>> enumerated by the WPSS Q6 processor (Wireless Processor SubSystem);
>>> In simple terms, though WCN6750 is PCIe device, it is not attached
>>> to the APSS processor, APSS will not know of such a device being
>>> present in the system and therefore WCN6750 will be registered as
>>> a platform device to the kernel core like other supported AHB
>>> devices.
>>>
>>> WCN6750 uses both AHB and PCI APIs for it's operation, it uses
>>> AHB APIs for device probe/boot and PCI APIs for device setup
>>> and register accesses; Because of this nature, it is referred
>>> as a hybrid bus device.
>>>
>>> Refactor PCI code to support hybrid bus devices like WCN6750.
>>>
>>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>>
>>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>>
>> [...]
>>
>>> --- /dev/null
>>> +++ b/drivers/net/wireless/ath/ath11k/pci_cmn.c
>>
>> [...]
>>
>>> +static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
>>> +{
>>> + struct ath11k_base *ab = ab_pci->ab;
>>> +
>>> + u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
>>> +
>>> + lockdep_assert_held(&ab_pci->window_lock);
>>> +
>>> + if (window != ab_pci->register_window) {
>>> + iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
>>> + ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
>>> + ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
>>> + ab_pci->register_window = window;
>>> + }
>>> +}
>>
>> So the style used in ath11k is ath11k_<filename>_foo, so that a function
>> ath11k_pci_foo() should be in pci.c. This patch is now breaking that
>> style. Maybe pci_cmn.c should renamed to cpci.c, pcic.c or something
>> like that? Then the function prefix could be ath11k_cpci_, ath11k_pcic_
>> or similar.
>>
>
> Makes sense, pcic.c and ath11k_pcic_* looks better, I'll make these changes.
Of course another possiblity, which I forgot to mention in my previous
email, is to keep pci_cmn.c filename but rename the functions to
ath11k_pci_cmn_foo(). Though don't know which one is better.
--
https://patchwork.kernel.org/project/linux-wireless/list/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 02/19] ath11k: Refactor PCI code to support hybrid bus devices
2022-02-21 9:19 ` Kalle Valo
@ 2022-02-21 10:19 ` Manikanta Pubbisetty
0 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-02-21 10:19 UTC (permalink / raw)
To: Kalle Valo; +Cc: ath11k, linux-wireless, devicetree, robh
On 2/21/2022 2:49 PM, Kalle Valo wrote:
> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>
>> On 1/28/2022 5:43 PM, Kalle Valo wrote:
>>> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>>>
>>>> Unlike other ATH11K PCIe devices which are enumerated by APSS
>>>> processor (Application Processor SubSystem), WCN6750 gets
>>>> enumerated by the WPSS Q6 processor (Wireless Processor SubSystem);
>>>> In simple terms, though WCN6750 is PCIe device, it is not attached
>>>> to the APSS processor, APSS will not know of such a device being
>>>> present in the system and therefore WCN6750 will be registered as
>>>> a platform device to the kernel core like other supported AHB
>>>> devices.
>>>>
>>>> WCN6750 uses both AHB and PCI APIs for it's operation, it uses
>>>> AHB APIs for device probe/boot and PCI APIs for device setup
>>>> and register accesses; Because of this nature, it is referred
>>>> as a hybrid bus device.
>>>>
>>>> Refactor PCI code to support hybrid bus devices like WCN6750.
>>>>
>>>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>>>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>>>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>>>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>>>
>>>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>>>
>>> [...]
>>>
>>>> --- /dev/null
>>>> +++ b/drivers/net/wireless/ath/ath11k/pci_cmn.c
>>>
>>> [...]
>>>
>>>> +static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
>>>> +{
>>>> + struct ath11k_base *ab = ab_pci->ab;
>>>> +
>>>> + u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
>>>> +
>>>> + lockdep_assert_held(&ab_pci->window_lock);
>>>> +
>>>> + if (window != ab_pci->register_window) {
>>>> + iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
>>>> + ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
>>>> + ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
>>>> + ab_pci->register_window = window;
>>>> + }
>>>> +}
>>>
>>> So the style used in ath11k is ath11k_<filename>_foo, so that a function
>>> ath11k_pci_foo() should be in pci.c. This patch is now breaking that
>>> style. Maybe pci_cmn.c should renamed to cpci.c, pcic.c or something
>>> like that? Then the function prefix could be ath11k_cpci_, ath11k_pcic_
>>> or similar.
>>>
>>
>> Makes sense, pcic.c and ath11k_pcic_* looks better, I'll make these changes.
>
> Of course another possiblity, which I forgot to mention in my previous
> email, is to keep pci_cmn.c filename but rename the functions to
> ath11k_pci_cmn_foo(). Though don't know which one is better.
>
I was contemplating on having ath11k_pci_cmn_* for a very long time; In
fact, in the patches which I worked on had the pci_cmn prefix for all
the APIs, I felt the prefix is long and dropped the idea :)
At least to me, pcic.c and ath11k_pcic* looked good.
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 03/19] ath11k: Choose MSI config based on HW revision
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
2022-01-16 12:46 ` [PATCH v2 01/19] ath11k: PCI changes to support WCN6750 Manikanta Pubbisetty
2022-01-16 12:46 ` [PATCH v2 02/19] ath11k: Refactor PCI code to support hybrid bus devices Manikanta Pubbisetty
@ 2022-01-16 12:46 ` Manikanta Pubbisetty
2022-01-16 12:47 ` [PATCH v2 04/19] ath11k: Refactor MSI logic Manikanta Pubbisetty
` (16 subsequent siblings)
19 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:46 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
Instead of selecting MSI config based on magic numbers, make
the assignment based on HW revision. The logic is similar to
the selection of HW params. This improves readability of the
code and also simplifies new additions.
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/pci.c | 31 ++++-------------
drivers/net/wireless/ath/ath11k/pci.h | 1 +
drivers/net/wireless/ath/ath11k/pci_cmn.c | 58 +++++++++++++++++++++++++++++++
drivers/net/wireless/ath/ath11k/pci_cmn.h | 1 +
4 files changed, 66 insertions(+), 25 deletions(-)
diff --git a/drivers/net/wireless/ath/ath11k/pci.c b/drivers/net/wireless/ath/ath11k/pci.c
index 81ee647..f8548f5 100644
--- a/drivers/net/wireless/ath/ath11k/pci.c
+++ b/drivers/net/wireless/ath/ath11k/pci.c
@@ -45,28 +45,6 @@ static const struct ath11k_bus_params ath11k_pci_bus_params = {
.fixed_mem_region = false,
};
-static const struct ath11k_msi_config ath11k_msi_config[] = {
- {
- .total_vectors = 32,
- .total_users = 4,
- .users = (struct ath11k_msi_user[]) {
- { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
- { .name = "CE", .num_vectors = 10, .base_vector = 3 },
- { .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
- { .name = "DP", .num_vectors = 18, .base_vector = 14 },
- },
- },
- {
- .total_vectors = 16,
- .total_users = 3,
- .users = (struct ath11k_msi_user[]) {
- { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
- { .name = "CE", .num_vectors = 5, .base_vector = 3 },
- { .name = "DP", .num_vectors = 8, .base_vector = 8 },
- },
- },
-};
-
static const struct ath11k_msi_config msi_config_one_msi = {
.total_vectors = 1,
.total_users = 4,
@@ -669,10 +647,8 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
ret = -EOPNOTSUPP;
goto err_pci_free_region;
}
- ab_pci->msi_config = &ath11k_msi_config[0];
break;
case QCN9074_DEVICE_ID:
- ab_pci->msi_config = &ath11k_msi_config[1];
ab->bus_params.static_window_map = true;
ab->hw_rev = ATH11K_HW_QCN9074_HW10;
break;
@@ -702,7 +678,6 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
ret = -EOPNOTSUPP;
goto err_pci_free_region;
}
- ab_pci->msi_config = &ath11k_msi_config[0];
break;
default:
dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
@@ -711,6 +686,12 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
goto err_pci_free_region;
}
+ ret = ath11k_pci_get_msi_config(ab);
+ if (ret) {
+ ath11k_err(ab, "failed to fetch msi config: %d\n", ret);
+ goto err_pci_free_region;
+ }
+
ret = ath11k_pci_alloc_msi(ab_pci);
if (ret) {
ath11k_err(ab, "failed to enable msi: %d\n", ret);
diff --git a/drivers/net/wireless/ath/ath11k/pci.h b/drivers/net/wireless/ath/ath11k/pci.h
index 35c8152..03868f3f 100644
--- a/drivers/net/wireless/ath/ath11k/pci.h
+++ b/drivers/net/wireless/ath/ath11k/pci.h
@@ -63,6 +63,7 @@ struct ath11k_msi_config {
int total_vectors;
int total_users;
struct ath11k_msi_user *users;
+ u16 hw_rev;
};
enum ath11k_pci_flags {
diff --git a/drivers/net/wireless/ath/ath11k/pci_cmn.c b/drivers/net/wireless/ath/ath11k/pci_cmn.c
index 0e3a98b..b5eca2d 100644
--- a/drivers/net/wireless/ath/ath11k/pci_cmn.c
+++ b/drivers/net/wireless/ath/ath11k/pci_cmn.c
@@ -63,6 +63,64 @@ static const char *irq_name[ATH11K_IRQ_NUM_MAX] = {
"tcl2host-status-ring",
};
+static const struct ath11k_msi_config ath11k_msi_config[] = {
+ {
+ .total_vectors = 32,
+ .total_users = 4,
+ .users = (struct ath11k_msi_user[]) {
+ { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
+ { .name = "CE", .num_vectors = 10, .base_vector = 3 },
+ { .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
+ { .name = "DP", .num_vectors = 18, .base_vector = 14 },
+ },
+ .hw_rev = ATH11K_HW_QCA6390_HW20,
+ },
+ {
+ .total_vectors = 16,
+ .total_users = 3,
+ .users = (struct ath11k_msi_user[]) {
+ { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
+ { .name = "CE", .num_vectors = 5, .base_vector = 3 },
+ { .name = "DP", .num_vectors = 8, .base_vector = 8 },
+ },
+ .hw_rev = ATH11K_HW_QCN9074_HW10,
+ },
+ {
+ .total_vectors = 32,
+ .total_users = 4,
+ .users = (struct ath11k_msi_user[]) {
+ { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
+ { .name = "CE", .num_vectors = 10, .base_vector = 3 },
+ { .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
+ { .name = "DP", .num_vectors = 18, .base_vector = 14 },
+ },
+ .hw_rev = ATH11K_HW_WCN6855_HW20,
+ },
+};
+
+int ath11k_pci_get_msi_config(struct ath11k_base *ab)
+{
+ struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
+ const struct ath11k_msi_config *msi_config;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ath11k_msi_config); i++) {
+ msi_config = &ath11k_msi_config[i];
+
+ if (msi_config->hw_rev == ab->hw_rev)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(ath11k_msi_config)) {
+ ath11k_err(ab, "failed to fetch msi config, unsupported hw version: 0x%x\n",
+ ab->hw_rev);
+ return -EINVAL;
+ }
+
+ ab_pci->msi_config = msi_config;
+ return 0;
+}
+
void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
{
if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags))
diff --git a/drivers/net/wireless/ath/ath11k/pci_cmn.h b/drivers/net/wireless/ath/ath11k/pci_cmn.h
index 5fb1cf1..f5916da 100644
--- a/drivers/net/wireless/ath/ath11k/pci_cmn.h
+++ b/drivers/net/wireless/ath/ath11k/pci_cmn.h
@@ -50,4 +50,5 @@ int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci);
int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
const struct cpumask *m);
+int ath11k_pci_get_msi_config(struct ath11k_base *ab);
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 04/19] ath11k: Refactor MSI logic
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
` (2 preceding siblings ...)
2022-01-16 12:46 ` [PATCH v2 03/19] ath11k: Choose MSI config based on HW revision Manikanta Pubbisetty
@ 2022-01-16 12:47 ` Manikanta Pubbisetty
2022-01-16 12:47 ` [PATCH v2 05/19] ath11k: Remove core PCI references from PCI common code Manikanta Pubbisetty
` (15 subsequent siblings)
19 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:47 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
Refactor MSI logic in order to support hybrid bus devices
like WCN6750.
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/core.h | 21 ++++++++++++++++
drivers/net/wireless/ath/ath11k/mhi.c | 3 +--
drivers/net/wireless/ath/ath11k/pci.c | 29 ++++++++++++++--------
drivers/net/wireless/ath/ath11k/pci.h | 16 ------------
drivers/net/wireless/ath/ath11k/pci_cmn.c | 41 ++++++-------------------------
drivers/net/wireless/ath/ath11k/pci_cmn.h | 5 +---
6 files changed, 50 insertions(+), 65 deletions(-)
diff --git a/drivers/net/wireless/ath/ath11k/core.h b/drivers/net/wireless/ath/ath11k/core.h
index 9e88ccc..bfa2a3a 100644
--- a/drivers/net/wireless/ath/ath11k/core.h
+++ b/drivers/net/wireless/ath/ath11k/core.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef ATH11K_CORE_H
@@ -693,6 +694,19 @@ struct ath11k_soc_dp_stats {
struct ath11k_dp_ring_bp_stats bp_stats;
};
+struct ath11k_msi_user {
+ char *name;
+ int num_vectors;
+ u32 base_vector;
+};
+
+struct ath11k_msi_config {
+ int total_vectors;
+ int total_users;
+ struct ath11k_msi_user *users;
+ u16 hw_rev;
+};
+
/* Master structure to hold the hw data which may be used in core module */
struct ath11k_base {
enum ath11k_hw_rev hw_rev;
@@ -805,6 +819,13 @@ struct ath11k_base {
u32 subsystem_device;
} id;
+ struct {
+ const struct ath11k_msi_config *msi_config;
+ u32 msi_ep_base_data;
+ u32 msi_addr_lo;
+ u32 msi_addr_hi;
+ } msi;
+
/* must be last */
u8 drv_priv[0] __aligned(sizeof(void *));
};
diff --git a/drivers/net/wireless/ath/ath11k/mhi.c b/drivers/net/wireless/ath/ath11k/mhi.c
index 21b8cfd..302b303 100644
--- a/drivers/net/wireless/ath/ath11k/mhi.c
+++ b/drivers/net/wireless/ath/ath11k/mhi.c
@@ -257,8 +257,7 @@ static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci)
int *irq;
unsigned int msi_data;
- ret = ath11k_pci_get_user_msi_assignment(ab_pci,
- "MHI", &num_vectors,
+ ret = ath11k_pci_get_user_msi_assignment(ab, "MHI", &num_vectors,
&user_base_data, &base_vector);
if (ret)
return ret;
diff --git a/drivers/net/wireless/ath/ath11k/pci.c b/drivers/net/wireless/ath/ath11k/pci.c
index f8548f5..a2f3be0 100644
--- a/drivers/net/wireless/ath/ath11k/pci.c
+++ b/drivers/net/wireless/ath/ath11k/pci.c
@@ -309,12 +309,13 @@ static void ath11k_pci_msi_disable(struct ath11k_pci *ab_pci)
static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci)
{
struct ath11k_base *ab = ab_pci->ab;
- const struct ath11k_msi_config *msi_config = ab_pci->msi_config;
+ const struct ath11k_msi_config *msi_config = ab->msi.msi_config;
+ struct pci_dev *pci_dev = ab_pci->pdev;
struct msi_desc *msi_desc;
int num_vectors;
int ret;
- num_vectors = pci_alloc_irq_vectors(ab_pci->pdev,
+ num_vectors = pci_alloc_irq_vectors(pci_dev,
msi_config->total_vectors,
msi_config->total_vectors,
PCI_IRQ_MSI);
@@ -331,7 +332,7 @@ static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci)
goto reset_msi_config;
}
clear_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags);
- ab_pci->msi_config = &msi_config_one_msi;
+ ab->msi.msi_config = &msi_config_one_msi;
ab_pci->irq_flags = IRQF_SHARED | IRQF_NOBALANCING;
ath11k_dbg(ab, ATH11K_DBG_PCI, "request MSI one vector\n");
}
@@ -346,11 +347,19 @@ static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci)
goto free_msi_vector;
}
- ab_pci->msi_ep_base_data = msi_desc->msg.data;
- if (msi_desc->msi_attrib.is_64)
- set_bit(ATH11K_PCI_FLAG_IS_MSI_64, &ab_pci->flags);
+ ab->msi.msi_ep_base_data = msi_desc->msg.data;
+
+ pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO,
+ &ab->msi.msi_addr_lo);
+
+ if (msi_desc->msi_attrib.is_64) {
+ pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI,
+ &ab->msi.msi_addr_hi);
+ } else {
+ ab->msi.msi_addr_hi = 0;
+ }
- ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data);
+ ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab->msi.msi_ep_base_data);
return 0;
@@ -377,10 +386,10 @@ static int ath11k_pci_config_msi_data(struct ath11k_pci *ab_pci)
return -EINVAL;
}
- ab_pci->msi_ep_base_data = msi_desc->msg.data;
+ ab_pci->ab->msi.msi_ep_base_data = msi_desc->msg.data;
ath11k_dbg(ab_pci->ab, ATH11K_DBG_PCI, "pci after request_irq msi_ep_base_data %d\n",
- ab_pci->msi_ep_base_data);
+ ab_pci->ab->msi.msi_ep_base_data);
return 0;
}
@@ -564,7 +573,7 @@ static const struct ath11k_hif_ops ath11k_pci_hif_ops = {
.irq_enable = ath11k_pci_ext_irq_enable,
.irq_disable = ath11k_pci_ext_irq_disable,
.get_msi_address = ath11k_pci_get_msi_address,
- .get_user_msi_vector = ath11k_get_user_msi_assignment,
+ .get_user_msi_vector = ath11k_pci_get_user_msi_assignment,
.map_service_to_pipe = ath11k_pci_map_service_to_pipe,
.ce_irq_enable = ath11k_pci_hif_ce_irq_enable,
.ce_irq_disable = ath11k_pci_hif_ce_irq_disable,
diff --git a/drivers/net/wireless/ath/ath11k/pci.h b/drivers/net/wireless/ath/ath11k/pci.h
index 03868f3f..694fcb4 100644
--- a/drivers/net/wireless/ath/ath11k/pci.h
+++ b/drivers/net/wireless/ath/ath11k/pci.h
@@ -53,22 +53,8 @@
#define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c
#define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4
-struct ath11k_msi_user {
- char *name;
- int num_vectors;
- u32 base_vector;
-};
-
-struct ath11k_msi_config {
- int total_vectors;
- int total_users;
- struct ath11k_msi_user *users;
- u16 hw_rev;
-};
-
enum ath11k_pci_flags {
ATH11K_PCI_FLAG_INIT_DONE,
- ATH11K_PCI_FLAG_IS_MSI_64,
ATH11K_PCI_ASPM_RESTORE,
ATH11K_PCI_FLAG_MULTI_MSI_VECTORS,
};
@@ -78,9 +64,7 @@ struct ath11k_pci {
struct ath11k_base *ab;
u16 dev_id;
char amss_path[100];
- u32 msi_ep_base_data;
struct mhi_controller *mhi_ctrl;
- const struct ath11k_msi_config *msi_config;
unsigned long mhi_state;
u32 register_window;
diff --git a/drivers/net/wireless/ath/ath11k/pci_cmn.c b/drivers/net/wireless/ath/ath11k/pci_cmn.c
index b5eca2d..f3142b1 100644
--- a/drivers/net/wireless/ath/ath11k/pci_cmn.c
+++ b/drivers/net/wireless/ath/ath11k/pci_cmn.c
@@ -100,7 +100,6 @@ static const struct ath11k_msi_config ath11k_msi_config[] = {
int ath11k_pci_get_msi_config(struct ath11k_base *ab)
{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
const struct ath11k_msi_config *msi_config;
int i;
@@ -117,7 +116,7 @@ int ath11k_pci_get_msi_config(struct ath11k_base *ab)
return -EINVAL;
}
- ab_pci->msi_config = msi_config;
+ ab->msi.msi_config = msi_config;
return 0;
}
@@ -251,33 +250,22 @@ int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector)
void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
u32 *msi_addr_hi)
{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
- struct pci_dev *pci_dev = to_pci_dev(ab->dev);
-
- pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO,
- msi_addr_lo);
-
- if (test_bit(ATH11K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) {
- pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI,
- msi_addr_hi);
- } else {
- *msi_addr_hi = 0;
- }
+ *msi_addr_lo = ab->msi.msi_addr_lo;
+ *msi_addr_hi = ab->msi.msi_addr_hi;
}
-int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ab_pci, char *user_name,
+int ath11k_pci_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
int *num_vectors, u32 *user_base_data,
u32 *base_vector)
{
- struct ath11k_base *ab = ab_pci->ab;
- const struct ath11k_msi_config *msi_config = ab_pci->msi_config;
+ const struct ath11k_msi_config *msi_config = ab->msi.msi_config;
int idx;
for (idx = 0; idx < msi_config->total_users; idx++) {
if (strcmp(user_name, msi_config->users[idx].name) == 0) {
*num_vectors = msi_config->users[idx].num_vectors;
*base_vector = msi_config->users[idx].base_vector;
- *user_base_data = *base_vector + ab_pci->msi_ep_base_data;
+ *user_base_data = *base_vector + ab->msi.msi_ep_base_data;
ath11k_dbg(ab, ATH11K_DBG_PCI,
"Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n",
@@ -309,17 +297,6 @@ void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx)
*msi_idx = msi_data_idx;
}
-int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
- int *num_vectors, u32 *user_base_data,
- u32 *base_vector)
-{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
-
- return ath11k_pci_get_user_msi_assignment(ab_pci, user_name,
- num_vectors, user_base_data,
- base_vector);
-}
-
static void ath11k_pci_free_ext_irq(struct ath11k_base *ab)
{
int i, j;
@@ -570,8 +547,7 @@ static int ath11k_pci_ext_irq_config(struct ath11k_base *ab)
int i, j, ret, num_vectors = 0;
u32 user_base_data = 0, base_vector = 0;
- ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab), "DP",
- &num_vectors,
+ ret = ath11k_pci_get_user_msi_assignment(ab, "DP", &num_vectors,
&user_base_data,
&base_vector);
if (ret < 0)
@@ -646,8 +622,7 @@ int ath11k_pci_config_irq(struct ath11k_base *ab)
unsigned int msi_data;
int irq, i, ret, irq_idx;
- ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab),
- "CE", &msi_data_count,
+ ret = ath11k_pci_get_user_msi_assignment(ab, "CE", &msi_data_count,
&msi_data_start, &msi_irq_start);
if (ret)
return ret;
diff --git a/drivers/net/wireless/ath/ath11k/pci_cmn.h b/drivers/net/wireless/ath/ath11k/pci_cmn.h
index f5916da..cc78c23 100644
--- a/drivers/net/wireless/ath/ath11k/pci_cmn.h
+++ b/drivers/net/wireless/ath/ath11k/pci_cmn.h
@@ -25,7 +25,7 @@
*/
#define ATH11K_PCI_ACCESS_ALWAYS_OFF 0xFE0
-int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ar_pci, char *user_name,
+int ath11k_pci_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
int *num_vectors, u32 *user_base_data,
u32 *base_vector);
int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector);
@@ -44,9 +44,6 @@ int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
u8 *ul_pipe, u8 *dl_pipe);
void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab);
void ath11k_pci_ce_irq_disable_sync(struct ath11k_base *ab);
-int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
- int *num_vectors, u32 *user_base_data,
- u32 *base_vector);
void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci);
int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
const struct cpumask *m);
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 05/19] ath11k: Remove core PCI references from PCI common code
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
` (3 preceding siblings ...)
2022-01-16 12:47 ` [PATCH v2 04/19] ath11k: Refactor MSI logic Manikanta Pubbisetty
@ 2022-01-16 12:47 ` Manikanta Pubbisetty
2022-01-28 10:20 ` Kalle Valo
2022-01-16 12:47 ` [PATCH v2 06/19] ath11k: Add HW params for WCN6750 Manikanta Pubbisetty
` (14 subsequent siblings)
19 siblings, 1 reply; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:47 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
Remove core PCI and ath11k PCI references(struct ath11k_pci)
from PCI common code. Since, PCI common code will be used
by hybrid bus devices, this code should be independent
from ATH11K PCI references and Linux core PCI references
like struct pci_dev.
Since this change introduces function callbacks for bus wakeup
and bus release operations, wakeup_mhi HW param is no longer
needed and hence it is removed completely. Alternatively, bus
wakeup/release ops for QCA9074 are initialized to NULL as
QCA9704 does not need bus wakeup/release for register accesses.
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/core.c | 6 --
drivers/net/wireless/ath/ath11k/core.h | 9 ++
drivers/net/wireless/ath/ath11k/hw.h | 1 -
drivers/net/wireless/ath/ath11k/mhi.c | 7 +-
drivers/net/wireless/ath/ath11k/pci.c | 130 ++++++++++++++++++++--
drivers/net/wireless/ath/ath11k/pci.h | 5 +-
drivers/net/wireless/ath/ath11k/pci_cmn.c | 174 +++++++++++-------------------
drivers/net/wireless/ath/ath11k/pci_cmn.h | 6 +-
8 files changed, 200 insertions(+), 138 deletions(-)
diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c
index 1ad77bd..90ac0b5 100644
--- a/drivers/net/wireless/ath/ath11k/core.c
+++ b/drivers/net/wireless/ath/ath11k/core.c
@@ -95,7 +95,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.hal_params = &ath11k_hw_hal_params_ipq8074,
.supports_dynamic_smps_6ghz = false,
.alloc_cacheable_memory = true,
- .wakeup_mhi = false,
.supports_rssi_stats = false,
.fw_wmi_diag_event = false,
},
@@ -159,7 +158,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.hal_params = &ath11k_hw_hal_params_ipq8074,
.supports_dynamic_smps_6ghz = false,
.alloc_cacheable_memory = true,
- .wakeup_mhi = false,
.supports_rssi_stats = false,
.fw_wmi_diag_event = false,
},
@@ -222,7 +220,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.hal_params = &ath11k_hw_hal_params_qca6390,
.supports_dynamic_smps_6ghz = false,
.alloc_cacheable_memory = false,
- .wakeup_mhi = true,
.supports_rssi_stats = true,
.fw_wmi_diag_event = true,
},
@@ -285,7 +282,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.hal_params = &ath11k_hw_hal_params_ipq8074,
.supports_dynamic_smps_6ghz = true,
.alloc_cacheable_memory = true,
- .wakeup_mhi = false,
.supports_rssi_stats = false,
.fw_wmi_diag_event = false,
},
@@ -348,7 +344,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.hal_params = &ath11k_hw_hal_params_qca6390,
.supports_dynamic_smps_6ghz = false,
.alloc_cacheable_memory = false,
- .wakeup_mhi = true,
.supports_rssi_stats = true,
.fw_wmi_diag_event = true,
},
@@ -410,7 +405,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.hal_params = &ath11k_hw_hal_params_qca6390,
.supports_dynamic_smps_6ghz = false,
.alloc_cacheable_memory = false,
- .wakeup_mhi = true,
.supports_rssi_stats = true,
.fw_wmi_diag_event = true,
},
diff --git a/drivers/net/wireless/ath/ath11k/core.h b/drivers/net/wireless/ath/ath11k/core.h
index bfa2a3a..9dd1904 100644
--- a/drivers/net/wireless/ath/ath11k/core.h
+++ b/drivers/net/wireless/ath/ath11k/core.h
@@ -205,6 +205,8 @@ enum ath11k_dev_flags {
ATH11K_FLAG_CE_IRQ_ENABLED,
ATH11K_FLAG_EXT_IRQ_ENABLED,
ATH11K_FLAG_FIXED_MEM_RGN,
+ ATH11K_FLAG_DEVICE_INIT_DONE,
+ ATH11K_FLAG_MULTI_MSI_VECTORS,
};
enum ath11k_monitor_flags {
@@ -651,6 +653,13 @@ struct ath11k_bus_params {
bool fixed_bdf_addr;
bool fixed_mem_region;
bool static_window_map;
+ struct {
+ void (*wakeup)(struct ath11k_base *ab);
+ void (*release)(struct ath11k_base *ab);
+ int (*get_msi_irq)(struct ath11k_base *ab, unsigned int vector);
+ void (*window_write32)(struct ath11k_base *ab, u32 offset, u32 value);
+ u32 (*window_read32)(struct ath11k_base *ab, u32 offset);
+ } ops;
};
/* IPQ8074 HW channel counters frequency value in hertz */
diff --git a/drivers/net/wireless/ath/ath11k/hw.h b/drivers/net/wireless/ath/ath11k/hw.h
index e06d392..ab258a0 100644
--- a/drivers/net/wireless/ath/ath11k/hw.h
+++ b/drivers/net/wireless/ath/ath11k/hw.h
@@ -189,7 +189,6 @@ struct ath11k_hw_params {
const struct ath11k_hw_hal_params *hal_params;
bool supports_dynamic_smps_6ghz;
bool alloc_cacheable_memory;
- bool wakeup_mhi;
bool supports_rssi_stats;
bool fw_wmi_diag_event;
};
diff --git a/drivers/net/wireless/ath/ath11k/mhi.c b/drivers/net/wireless/ath/ath11k/mhi.c
index 302b303..80a4877 100644
--- a/drivers/net/wireless/ath/ath11k/mhi.c
+++ b/drivers/net/wireless/ath/ath11k/mhi.c
@@ -272,11 +272,10 @@ static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci)
for (i = 0; i < num_vectors; i++) {
msi_data = base_vector;
- if (test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
+ if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
msi_data += i;
- irq[i] = ath11k_pci_get_msi_irq(ab->dev,
- msi_data);
+ irq[i] = ath11k_pci_get_msi_irq(ab, msi_data);
}
ab_pci->mhi_ctrl->irq = irq;
@@ -373,7 +372,7 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci)
return ret;
}
- if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
+ if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING;
if (test_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags)) {
diff --git a/drivers/net/wireless/ath/ath11k/pci.c b/drivers/net/wireless/ath/ath11k/pci.c
index a2f3be0..4f2fe72 100644
--- a/drivers/net/wireless/ath/ath11k/pci.c
+++ b/drivers/net/wireless/ath/ath11k/pci.c
@@ -38,11 +38,83 @@ static const struct pci_device_id ath11k_pci_id_table[] = {
MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table);
+static void ath11k_pci_bus_wake_up(struct ath11k_base *ab)
+{
+ struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
+
+ mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
+}
+
+static void ath11k_pci_bus_release(struct ath11k_base *ab)
+{
+ struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
+
+ mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
+}
+
+static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
+{
+ struct ath11k_base *ab = ab_pci->ab;
+
+ u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
+
+ lockdep_assert_held(&ab_pci->window_lock);
+
+ if (window != ab_pci->register_window) {
+ iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
+ ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
+ ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
+ ab_pci->register_window = window;
+ }
+}
+
+static void
+ath11k_pci_window_write32(struct ath11k_base *ab, u32 offset, u32 value)
+{
+ struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
+ u32 window_start = ATH11K_PCI_WINDOW_START;
+
+ spin_lock_bh(&ab_pci->window_lock);
+ ath11k_pci_select_window(ab_pci, offset);
+ iowrite32(value, ab->mem + window_start +
+ (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
+ spin_unlock_bh(&ab_pci->window_lock);
+}
+
+static u32 ath11k_pci_window_read32(struct ath11k_base *ab, u32 offset)
+{
+ struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
+ u32 window_start = ATH11K_PCI_WINDOW_START;
+ u32 val;
+
+ spin_lock_bh(&ab_pci->window_lock);
+ ath11k_pci_select_window(ab_pci, offset);
+ val = ioread32(ab->mem + window_start +
+ (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
+ spin_unlock_bh(&ab_pci->window_lock);
+
+ return val;
+}
+
+int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector)
+{
+ struct pci_dev *pci_dev = to_pci_dev(ab->dev);
+
+ return pci_irq_vector(pci_dev, vector);
+}
+
static const struct ath11k_bus_params ath11k_pci_bus_params = {
.mhi_support = true,
.m3_fw_support = true,
.fixed_bdf_addr = false,
.fixed_mem_region = false,
+ .ops = {
+ .wakeup = ath11k_pci_bus_wake_up,
+ .release = ath11k_pci_bus_release,
+ .get_msi_irq = ath11k_pci_get_msi_irq,
+ .window_write32 = ath11k_pci_window_write32,
+ .window_read32 = ath11k_pci_window_read32,
+ },
};
static const struct ath11k_msi_config msi_config_one_msi = {
@@ -320,8 +392,7 @@ static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci)
msi_config->total_vectors,
PCI_IRQ_MSI);
if (num_vectors == msi_config->total_vectors) {
- set_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags);
- ab_pci->irq_flags = IRQF_SHARED;
+ set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
} else {
num_vectors = pci_alloc_irq_vectors(ab_pci->pdev,
1,
@@ -331,9 +402,8 @@ static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci)
ret = -EINVAL;
goto reset_msi_config;
}
- clear_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags);
+ clear_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
ab->msi.msi_config = &msi_config_one_msi;
- ab_pci->irq_flags = IRQF_SHARED | IRQF_NOBALANCING;
ath11k_dbg(ab, ATH11K_DBG_PCI, "request MSI one vector\n");
}
ath11k_info(ab, "MSI vectors: %d\n", num_vectors);
@@ -489,13 +559,20 @@ static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci)
set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags);
}
+static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
+{
+ if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags))
+ pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
+ ab_pci->link_ctl);
+}
+
static int ath11k_pci_power_up(struct ath11k_base *ab)
{
struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
int ret;
ab_pci->register_window = 0;
- clear_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
+ clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
ath11k_pci_sw_reset(ab_pci->ab, true);
/* Disable ASPM during firmware download due to problems switching
@@ -529,7 +606,7 @@ static void ath11k_pci_power_down(struct ath11k_base *ab)
ath11k_pci_msi_disable(ab_pci);
ath11k_mhi_stop(ab_pci);
- clear_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
+ clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
ath11k_pci_sw_reset(ab_pci->ab, false);
}
@@ -561,6 +638,23 @@ static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab)
ath11k_pci_ce_irq_disable_sync(ab);
}
+static int ath11k_pci_start(struct ath11k_base *ab)
+{
+ struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
+
+ /* TODO: for now don't restore ASPM in case of single MSI
+ * vector as MHI register reading in M2 causes system hang.
+ */
+ if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
+ ath11k_pci_aspm_restore(ab_pci);
+ else
+ ath11k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n");
+
+ ath11k_pci_start_cmn(ab);
+
+ return 0;
+}
+
static const struct ath11k_hif_ops ath11k_pci_hif_ops = {
.start = ath11k_pci_start,
.stop = ath11k_pci_stop,
@@ -594,6 +688,15 @@ static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *
*major, *minor);
}
+static int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
+ const struct cpumask *m)
+{
+ if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab_pci->ab->dev_flags))
+ return 0;
+
+ return irq_set_affinity_hint(ab_pci->pdev->irq, m);
+}
+
static int ath11k_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *pci_dev)
{
@@ -659,6 +762,8 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
break;
case QCN9074_DEVICE_ID:
ab->bus_params.static_window_map = true;
+ ab->bus_params.ops.wakeup = NULL;
+ ab->bus_params.ops.release = NULL;
ab->hw_rev = ATH11K_HW_QCN9074_HW10;
break;
case WCN6855_DEVICE_ID:
@@ -735,6 +840,12 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
goto err_ce_free;
}
+ ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));
+ if (ret) {
+ ath11k_err(ab, "failed to set irq affinity %d\n", ret);
+ goto err_free_irq;
+ }
+
/* kernel may allocate a dummy vector before request_irq and
* then allocate a real vector when request_irq is called.
* So get msi_data here again to avoid spurious interrupt
@@ -743,16 +854,19 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
ret = ath11k_pci_config_msi_data(ab_pci);
if (ret) {
ath11k_err(ab, "failed to config msi_data: %d\n", ret);
- goto err_free_irq;
+ goto err_irq_affinity_cleanup;
}
ret = ath11k_core_init(ab);
if (ret) {
ath11k_err(ab, "failed to init core: %d\n", ret);
- goto err_free_irq;
+ goto err_irq_affinity_cleanup;
}
return 0;
+err_irq_affinity_cleanup:
+ ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
+
err_free_irq:
ath11k_pci_free_irq(ab);
diff --git a/drivers/net/wireless/ath/ath11k/pci.h b/drivers/net/wireless/ath/ath11k/pci.h
index 694fcb4..aec4609 100644
--- a/drivers/net/wireless/ath/ath11k/pci.h
+++ b/drivers/net/wireless/ath/ath11k/pci.h
@@ -54,9 +54,7 @@
#define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4
enum ath11k_pci_flags {
- ATH11K_PCI_FLAG_INIT_DONE,
ATH11K_PCI_ASPM_RESTORE,
- ATH11K_PCI_FLAG_MULTI_MSI_VECTORS,
};
struct ath11k_pci {
@@ -74,8 +72,6 @@ struct ath11k_pci {
/* enum ath11k_pci_flags */
unsigned long flags;
u16 link_ctl;
-
- unsigned long irq_flags;
};
static inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab)
@@ -83,4 +79,5 @@ static inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab)
return (struct ath11k_pci *)ab->drv_priv;
}
+int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector);
#endif
diff --git a/drivers/net/wireless/ath/ath11k/pci_cmn.c b/drivers/net/wireless/ath/ath11k/pci_cmn.c
index f3142b1..a5b84b5 100644
--- a/drivers/net/wireless/ath/ath11k/pci_cmn.c
+++ b/drivers/net/wireless/ath/ath11k/pci_cmn.c
@@ -4,7 +4,6 @@
* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
-#include <linux/pci.h>
#include "core.h"
#include "pci_cmn.h"
#include "debug.h"
@@ -120,29 +119,6 @@ int ath11k_pci_get_msi_config(struct ath11k_base *ab)
return 0;
}
-void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
-{
- if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags))
- pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
- ab_pci->link_ctl);
-}
-
-static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
-{
- struct ath11k_base *ab = ab_pci->ab;
-
- u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
-
- lockdep_assert_held(&ab_pci->window_lock);
-
- if (window != ab_pci->register_window) {
- iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
- ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
- ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
- ab_pci->register_window = window;
- }
-}
-
static inline u32 ath11k_pci_get_window_start(struct ath11k_base *ab,
u32 offset)
{
@@ -162,16 +138,15 @@ static inline u32 ath11k_pci_get_window_start(struct ath11k_base *ab,
void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value)
{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
u32 window_start;
/* for offset beyond BAR + 4K - 32, may
- * need to wakeup MHI to access.
+ * need to wakeup the device to access.
*/
- if (ab->hw_params.wakeup_mhi &&
- test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
- offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
- mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
+ if (test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
+ offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF &&
+ ab->bus_params.ops.wakeup)
+ ab->bus_params.ops.wakeup(ab);
if (offset < ATH11K_PCI_WINDOW_START) {
iowrite32(value, ab->mem + offset);
@@ -181,36 +156,32 @@ void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value)
else
window_start = ATH11K_PCI_WINDOW_START;
- if (window_start == ATH11K_PCI_WINDOW_START) {
- spin_lock_bh(&ab_pci->window_lock);
- ath11k_pci_select_window(ab_pci, offset);
- iowrite32(value, ab->mem + window_start +
- (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
- spin_unlock_bh(&ab_pci->window_lock);
+ if (window_start == ATH11K_PCI_WINDOW_START &&
+ ab->bus_params.ops.window_write32) {
+ ab->bus_params.ops.window_write32(ab, offset, value);
} else {
iowrite32(value, ab->mem + window_start +
(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
}
}
- if (ab->hw_params.wakeup_mhi &&
- test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
- offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
- mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
+ if (test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
+ offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF &&
+ ab->bus_params.ops.release)
+ ab->bus_params.ops.release(ab);
}
u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset)
{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
u32 val, window_start;
/* for offset beyond BAR + 4K - 32, may
- * need to wakeup MHI to access.
+ * need to wakeup the device to access.
*/
- if (ab->hw_params.wakeup_mhi &&
- test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
- offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
- mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
+ if (test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
+ offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF &&
+ ab->bus_params.ops.wakeup)
+ ab->bus_params.ops.wakeup(ab);
if (offset < ATH11K_PCI_WINDOW_START) {
val = ioread32(ab->mem + offset);
@@ -220,33 +191,23 @@ u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset)
else
window_start = ATH11K_PCI_WINDOW_START;
- if (window_start == ATH11K_PCI_WINDOW_START) {
- spin_lock_bh(&ab_pci->window_lock);
- ath11k_pci_select_window(ab_pci, offset);
- val = ioread32(ab->mem + window_start +
- (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
- spin_unlock_bh(&ab_pci->window_lock);
+ if (window_start == ATH11K_PCI_WINDOW_START &&
+ ab->bus_params.ops.window_read32) {
+ val = ab->bus_params.ops.window_read32(ab, offset);
} else {
val = ioread32(ab->mem + window_start +
(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
}
}
- if (ab->hw_params.wakeup_mhi &&
- test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
- offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
- mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
+ if (test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
+ offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF &&
+ ab->bus_params.ops.release)
+ ab->bus_params.ops.release(ab);
return val;
}
-int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector)
-{
- struct pci_dev *pci_dev = to_pci_dev(dev);
-
- return pci_irq_vector(pci_dev, vector);
-}
-
void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
u32 *msi_addr_hi)
{
@@ -327,13 +288,12 @@ void ath11k_pci_free_irq(struct ath11k_base *ab)
static void ath11k_pci_ce_irq_enable(struct ath11k_base *ab, u16 ce_id)
{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
u32 irq_idx;
/* In case of one MSI vector, we handle irq enable/disable in a
* uniform way since we only have one irq
*/
- if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
+ if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
return;
irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id;
@@ -342,13 +302,12 @@ static void ath11k_pci_ce_irq_enable(struct ath11k_base *ab, u16 ce_id)
static void ath11k_pci_ce_irq_disable(struct ath11k_base *ab, u16 ce_id)
{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
u32 irq_idx;
/* In case of one MSI vector, we handle irq enable/disable in a
* uniform way since we only have one irq
*/
- if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
+ if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
return;
irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id;
@@ -413,13 +372,13 @@ static irqreturn_t ath11k_pci_ce_interrupt_handler(int irq, void *arg)
static void ath11k_pci_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp)
{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(irq_grp->ab);
+ struct ath11k_base *ab = irq_grp->ab;
int i;
/* In case of one MSI vector, we handle irq enable/disable
* in a uniform way since we only have one irq
*/
- if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
+ if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
return;
for (i = 0; i < irq_grp->num_irq; i++)
@@ -447,13 +406,13 @@ static void __ath11k_pci_ext_irq_disable(struct ath11k_base *sc)
static void ath11k_pci_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp)
{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(irq_grp->ab);
+ struct ath11k_base *ab = irq_grp->ab;
int i;
/* In case of one MSI vector, we handle irq enable/disable in a
* uniform way since we only have one irq
*/
- if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
+ if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
return;
for (i = 0; i < irq_grp->num_irq; i++)
@@ -541,11 +500,22 @@ static irqreturn_t ath11k_pci_ext_interrupt_handler(int irq, void *arg)
return IRQ_HANDLED;
}
+static int
+ath11k_pci_get_msi_irq_cmn(struct ath11k_base *ab, unsigned int vector)
+{
+ if (!ab->bus_params.ops.get_msi_irq) {
+ WARN_ONCE(1, "get_msi_irq bus op not defined");
+ return -EOPNOTSUPP;
+ }
+
+ return ab->bus_params.ops.get_msi_irq(ab, vector);
+}
+
static int ath11k_pci_ext_irq_config(struct ath11k_base *ab)
{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
int i, j, ret, num_vectors = 0;
u32 user_base_data = 0, base_vector = 0;
+ unsigned long irq_flags;
ret = ath11k_pci_get_user_msi_assignment(ab, "DP", &num_vectors,
&user_base_data,
@@ -553,6 +523,10 @@ static int ath11k_pci_ext_irq_config(struct ath11k_base *ab)
if (ret < 0)
return ret;
+ irq_flags = IRQF_SHARED;
+ if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
+ irq_flags |= IRQF_NOBALANCING;
+
for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
u32 num_irq = 0;
@@ -580,7 +554,10 @@ static int ath11k_pci_ext_irq_config(struct ath11k_base *ab)
for (j = 0; j < irq_grp->num_irq; j++) {
int irq_idx = irq_grp->irqs[j];
int vector = (i % num_vectors) + base_vector;
- int irq = ath11k_pci_get_msi_irq(ab->dev, vector);
+ int irq = ath11k_pci_get_msi_irq_cmn(ab, vector);
+
+ if (irq < 0)
+ return irq;
ab->irq_num[irq_idx] = irq;
@@ -589,8 +566,7 @@ static int ath11k_pci_ext_irq_config(struct ath11k_base *ab)
irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
ret = request_irq(irq, ath11k_pci_ext_interrupt_handler,
- ab_pci->irq_flags,
- "DP_EXT_IRQ", irq_grp);
+ irq_flags, "DP_EXT_IRQ", irq_grp);
if (ret) {
ath11k_err(ab, "failed request irq %d: %d\n",
vector, ret);
@@ -603,35 +579,24 @@ static int ath11k_pci_ext_irq_config(struct ath11k_base *ab)
return 0;
}
-int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
- const struct cpumask *m)
-{
- if (test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
- return 0;
-
- return irq_set_affinity_hint(ab_pci->pdev->irq, m);
-}
-
int ath11k_pci_config_irq(struct ath11k_base *ab)
{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
struct ath11k_ce_pipe *ce_pipe;
u32 msi_data_start;
u32 msi_data_count, msi_data_idx;
u32 msi_irq_start;
unsigned int msi_data;
int irq, i, ret, irq_idx;
+ unsigned long irq_flags;
ret = ath11k_pci_get_user_msi_assignment(ab, "CE", &msi_data_count,
&msi_data_start, &msi_irq_start);
if (ret)
return ret;
- ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));
- if (ret) {
- ath11k_err(ab, "failed to set irq affinity %d\n", ret);
- return ret;
- }
+ irq_flags = IRQF_SHARED;
+ if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
+ irq_flags |= IRQF_NOBALANCING;
/* Configure CE irqs */
for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) {
@@ -639,7 +604,10 @@ int ath11k_pci_config_irq(struct ath11k_base *ab)
continue;
msi_data = (msi_data_idx % msi_data_count) + msi_irq_start;
- irq = ath11k_pci_get_msi_irq(ab->dev, msi_data);
+ irq = ath11k_pci_get_msi_irq_cmn(ab, msi_data);
+ if (irq < 0)
+ return irq;
+
ce_pipe = &ab->ce.ce_pipe[i];
irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
@@ -647,12 +615,12 @@ int ath11k_pci_config_irq(struct ath11k_base *ab)
tasklet_setup(&ce_pipe->intr_tq, ath11k_pci_ce_tasklet);
ret = request_irq(irq, ath11k_pci_ce_interrupt_handler,
- ab_pci->irq_flags, irq_name[irq_idx],
+ irq_flags, irq_name[irq_idx],
ce_pipe);
if (ret) {
ath11k_err(ab, "failed to request irq %d: %d\n",
irq_idx, ret);
- goto err_irq_affinity_cleanup;
+ return ret;
}
ab->irq_num[irq_idx] = irq;
@@ -663,13 +631,9 @@ int ath11k_pci_config_irq(struct ath11k_base *ab)
ret = ath11k_pci_ext_irq_config(ab);
if (ret)
- goto err_irq_affinity_cleanup;
+ return ret;
return 0;
-
-err_irq_affinity_cleanup:
- ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
- return ret;
}
void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab)
@@ -712,19 +676,9 @@ void ath11k_pci_stop(struct ath11k_base *ab)
ath11k_ce_cleanup_pipes(ab);
}
-int ath11k_pci_start(struct ath11k_base *ab)
+int ath11k_pci_start_cmn(struct ath11k_base *ab)
{
- struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
-
- set_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
-
- /* TODO: for now don't restore ASPM in case of single MSI
- * vector as MHI register reading in M2 causes system hang.
- */
- if (test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
- ath11k_pci_aspm_restore(ab_pci);
- else
- ath11k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n");
+ set_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
ath11k_pci_ce_irqs_enable(ab);
ath11k_ce_rx_post_buf(ab);
diff --git a/drivers/net/wireless/ath/ath11k/pci_cmn.h b/drivers/net/wireless/ath/ath11k/pci_cmn.h
index cc78c23..8f99be7 100644
--- a/drivers/net/wireless/ath/ath11k/pci_cmn.h
+++ b/drivers/net/wireless/ath/ath11k/pci_cmn.h
@@ -28,7 +28,6 @@
int ath11k_pci_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
int *num_vectors, u32 *user_base_data,
u32 *base_vector);
-int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector);
void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value);
u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset);
void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
@@ -39,13 +38,10 @@ int ath11k_pci_config_irq(struct ath11k_base *ab);
void ath11k_pci_ext_irq_enable(struct ath11k_base *ab);
void ath11k_pci_ext_irq_disable(struct ath11k_base *ab);
void ath11k_pci_stop(struct ath11k_base *ab);
-int ath11k_pci_start(struct ath11k_base *ab);
+int ath11k_pci_start_cmn(struct ath11k_base *ab);
int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
u8 *ul_pipe, u8 *dl_pipe);
void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab);
void ath11k_pci_ce_irq_disable_sync(struct ath11k_base *ab);
-void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci);
-int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
- const struct cpumask *m);
int ath11k_pci_get_msi_config(struct ath11k_base *ab);
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCH v2 05/19] ath11k: Remove core PCI references from PCI common code
2022-01-16 12:47 ` [PATCH v2 05/19] ath11k: Remove core PCI references from PCI common code Manikanta Pubbisetty
@ 2022-01-28 10:20 ` Kalle Valo
2022-01-28 10:37 ` Kalle Valo
2022-02-21 6:55 ` Manikanta Pubbisetty
0 siblings, 2 replies; 49+ messages in thread
From: Kalle Valo @ 2022-01-28 10:20 UTC (permalink / raw)
To: Manikanta Pubbisetty; +Cc: ath11k, linux-wireless, devicetree, robh
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
> Remove core PCI and ath11k PCI references(struct ath11k_pci)
> from PCI common code. Since, PCI common code will be used
> by hybrid bus devices, this code should be independent
> from ATH11K PCI references and Linux core PCI references
> like struct pci_dev.
>
> Since this change introduces function callbacks for bus wakeup
> and bus release operations, wakeup_mhi HW param is no longer
> needed and hence it is removed completely. Alternatively, bus
> wakeup/release ops for QCA9074 are initialized to NULL as
> QCA9704 does not need bus wakeup/release for register accesses.
>
> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>
> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
[...]
> @@ -651,6 +653,13 @@ struct ath11k_bus_params {
> bool fixed_bdf_addr;
> bool fixed_mem_region;
> bool static_window_map;
> + struct {
> + void (*wakeup)(struct ath11k_base *ab);
> + void (*release)(struct ath11k_base *ab);
> + int (*get_msi_irq)(struct ath11k_base *ab, unsigned int vector);
> + void (*window_write32)(struct ath11k_base *ab, u32 offset, u32 value);
> + u32 (*window_read32)(struct ath11k_base *ab, u32 offset);
> + } ops;
> };
Please don't use bus_params for this, I'm starting to suspect that we
actually need to remove struct ath11k_bus_params altogether. It would be
cleaner to have separate 'struct ath11k_pci_ops' or something like that.
--
https://patchwork.kernel.org/project/linux-wireless/list/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 05/19] ath11k: Remove core PCI references from PCI common code
2022-01-28 10:20 ` Kalle Valo
@ 2022-01-28 10:37 ` Kalle Valo
2022-02-21 7:07 ` Manikanta Pubbisetty
2022-02-21 6:55 ` Manikanta Pubbisetty
1 sibling, 1 reply; 49+ messages in thread
From: Kalle Valo @ 2022-01-28 10:37 UTC (permalink / raw)
To: Manikanta Pubbisetty; +Cc: ath11k, linux-wireless, devicetree, robh
Kalle Valo <kvalo@kernel.org> writes:
> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>
>> Remove core PCI and ath11k PCI references(struct ath11k_pci)
>> from PCI common code. Since, PCI common code will be used
>> by hybrid bus devices, this code should be independent
>> from ATH11K PCI references and Linux core PCI references
>> like struct pci_dev.
>>
>> Since this change introduces function callbacks for bus wakeup
>> and bus release operations, wakeup_mhi HW param is no longer
>> needed and hence it is removed completely. Alternatively, bus
>> wakeup/release ops for QCA9074 are initialized to NULL as
>> QCA9704 does not need bus wakeup/release for register accesses.
>>
>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>
>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>
> [...]
>
>> @@ -651,6 +653,13 @@ struct ath11k_bus_params {
>> bool fixed_bdf_addr;
>> bool fixed_mem_region;
>> bool static_window_map;
>> + struct {
>> + void (*wakeup)(struct ath11k_base *ab);
>> + void (*release)(struct ath11k_base *ab);
>> + int (*get_msi_irq)(struct ath11k_base *ab, unsigned int vector);
>> + void (*window_write32)(struct ath11k_base *ab, u32 offset, u32 value);
>> + u32 (*window_read32)(struct ath11k_base *ab, u32 offset);
>> + } ops;
>> };
>
> Please don't use bus_params for this, I'm starting to suspect that we
> actually need to remove struct ath11k_bus_params altogether. It would be
> cleaner to have separate 'struct ath11k_pci_ops' or something like that.
And after looking at this more it seems .get_msi_irq is the only
function which actually has two different implementations. The other
four are either run or not run, there's no difference in the
implementation. So would it be cleaner to have a some sort check within
the function for these other four, instead using function pointers?
--
https://patchwork.kernel.org/project/linux-wireless/list/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 05/19] ath11k: Remove core PCI references from PCI common code
2022-01-28 10:37 ` Kalle Valo
@ 2022-02-21 7:07 ` Manikanta Pubbisetty
2022-02-21 9:21 ` Kalle Valo
0 siblings, 1 reply; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-02-21 7:07 UTC (permalink / raw)
To: Kalle Valo; +Cc: ath11k, linux-wireless, devicetree, robh
On 1/28/2022 4:07 PM, Kalle Valo wrote:
> Kalle Valo <kvalo@kernel.org> writes:
>
>> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>>
>>> Remove core PCI and ath11k PCI references(struct ath11k_pci)
>>> from PCI common code. Since, PCI common code will be used
>>> by hybrid bus devices, this code should be independent
>>> from ATH11K PCI references and Linux core PCI references
>>> like struct pci_dev.
>>>
>>> Since this change introduces function callbacks for bus wakeup
>>> and bus release operations, wakeup_mhi HW param is no longer
>>> needed and hence it is removed completely. Alternatively, bus
>>> wakeup/release ops for QCA9074 are initialized to NULL as
>>> QCA9704 does not need bus wakeup/release for register accesses.
>>>
>>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>>
>>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>>
>> [...]
>>
>>> @@ -651,6 +653,13 @@ struct ath11k_bus_params {
>>> bool fixed_bdf_addr;
>>> bool fixed_mem_region;
>>> bool static_window_map;
>>> + struct {
>>> + void (*wakeup)(struct ath11k_base *ab);
>>> + void (*release)(struct ath11k_base *ab);
>>> + int (*get_msi_irq)(struct ath11k_base *ab, unsigned int vector);
>>> + void (*window_write32)(struct ath11k_base *ab, u32 offset, u32 value);
>>> + u32 (*window_read32)(struct ath11k_base *ab, u32 offset);
>>> + } ops;
>>> };
>>
>> Please don't use bus_params for this, I'm starting to suspect that we
>> actually need to remove struct ath11k_bus_params altogether. It would be
>> cleaner to have separate 'struct ath11k_pci_ops' or something like that.
>
> And after looking at this more it seems .get_msi_irq is the only
> function which actually has two different implementations. The other
> four are either run or not run, there's no difference in the
> implementation. So would it be cleaner to have a some sort check within
> the function for these other four, instead using function pointers?
>
WCN6750 has it's own wakeup() and release(), I'll send that patch
separately. QCN9074 doesn't need wakeup() and release() functions.
The intention of the patch was to remove all Linux and ATH11K PCI
reference like struct pci_dev and ath11k_pci in the common code.
TBH, WCN6750 doesn't need these references since it is a AHB device
in ATH11K. If we have these references in common code, first thing is
the code will look kind of messed up and another aspect is we need to
enable CONFIG_PCI unnecessarily. This was the reason behind defining
other two callbacks window_write32() and read32().
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 05/19] ath11k: Remove core PCI references from PCI common code
2022-02-21 7:07 ` Manikanta Pubbisetty
@ 2022-02-21 9:21 ` Kalle Valo
0 siblings, 0 replies; 49+ messages in thread
From: Kalle Valo @ 2022-02-21 9:21 UTC (permalink / raw)
To: Manikanta Pubbisetty; +Cc: ath11k, linux-wireless, devicetree, robh
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
> On 1/28/2022 4:07 PM, Kalle Valo wrote:
>> Kalle Valo <kvalo@kernel.org> writes:
>>
>>> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>>>
>>>> Remove core PCI and ath11k PCI references(struct ath11k_pci)
>>>> from PCI common code. Since, PCI common code will be used
>>>> by hybrid bus devices, this code should be independent
>>>> from ATH11K PCI references and Linux core PCI references
>>>> like struct pci_dev.
>>>>
>>>> Since this change introduces function callbacks for bus wakeup
>>>> and bus release operations, wakeup_mhi HW param is no longer
>>>> needed and hence it is removed completely. Alternatively, bus
>>>> wakeup/release ops for QCA9074 are initialized to NULL as
>>>> QCA9704 does not need bus wakeup/release for register accesses.
>>>>
>>>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>>>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>>>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>>>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>>>
>>>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>>>
>>> [...]
>>>
>>>> @@ -651,6 +653,13 @@ struct ath11k_bus_params {
>>>> bool fixed_bdf_addr;
>>>> bool fixed_mem_region;
>>>> bool static_window_map;
>>>> + struct {
>>>> + void (*wakeup)(struct ath11k_base *ab);
>>>> + void (*release)(struct ath11k_base *ab);
>>>> + int (*get_msi_irq)(struct ath11k_base *ab, unsigned int vector);
>>>> + void (*window_write32)(struct ath11k_base *ab, u32 offset, u32 value);
>>>> + u32 (*window_read32)(struct ath11k_base *ab, u32 offset);
>>>> + } ops;
>>>> };
>>>
>>> Please don't use bus_params for this, I'm starting to suspect that we
>>> actually need to remove struct ath11k_bus_params altogether. It would be
>>> cleaner to have separate 'struct ath11k_pci_ops' or something like that.
>>
>> And after looking at this more it seems .get_msi_irq is the only
>> function which actually has two different implementations. The other
>> four are either run or not run, there's no difference in the
>> implementation. So would it be cleaner to have a some sort check within
>> the function for these other four, instead using function pointers?
>>
>
> WCN6750 has it's own wakeup() and release(), I'll send that patch
> separately. QCN9074 doesn't need wakeup() and release() functions.
>
> The intention of the patch was to remove all Linux and ATH11K PCI
> reference like struct pci_dev and ath11k_pci in the common code.
> TBH, WCN6750 doesn't need these references since it is a AHB device
> in ATH11K. If we have these references in common code, first thing is
> the code will look kind of messed up and another aspect is we need to
> enable CONFIG_PCI unnecessarily. This was the reason behind defining
> other two callbacks window_write32() and read32().
Ah, makes sense.
--
https://patchwork.kernel.org/project/linux-wireless/list/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 05/19] ath11k: Remove core PCI references from PCI common code
2022-01-28 10:20 ` Kalle Valo
2022-01-28 10:37 ` Kalle Valo
@ 2022-02-21 6:55 ` Manikanta Pubbisetty
2022-02-21 9:17 ` Kalle Valo
1 sibling, 1 reply; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-02-21 6:55 UTC (permalink / raw)
To: Kalle Valo; +Cc: ath11k, linux-wireless, devicetree, robh
On 1/28/2022 3:50 PM, Kalle Valo wrote:
> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>
>> Remove core PCI and ath11k PCI references(struct ath11k_pci)
>> from PCI common code. Since, PCI common code will be used
>> by hybrid bus devices, this code should be independent
>> from ATH11K PCI references and Linux core PCI references
>> like struct pci_dev.
>>
>> Since this change introduces function callbacks for bus wakeup
>> and bus release operations, wakeup_mhi HW param is no longer
>> needed and hence it is removed completely. Alternatively, bus
>> wakeup/release ops for QCA9074 are initialized to NULL as
>> QCA9704 does not need bus wakeup/release for register accesses.
>>
>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>
>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>
> [...]
>
>> @@ -651,6 +653,13 @@ struct ath11k_bus_params {
>> bool fixed_bdf_addr;
>> bool fixed_mem_region;
>> bool static_window_map;
>> + struct {
>> + void (*wakeup)(struct ath11k_base *ab);
>> + void (*release)(struct ath11k_base *ab);
>> + int (*get_msi_irq)(struct ath11k_base *ab, unsigned int vector);
>> + void (*window_write32)(struct ath11k_base *ab, u32 offset, u32 value);
>> + u32 (*window_read32)(struct ath11k_base *ab, u32 offset);
>> + } ops;
>> };
>
> Please don't use bus_params for this, I'm starting to suspect that we
> actually need to remove struct ath11k_bus_params altogether. It would be
> cleaner to have separate 'struct ath11k_pci_ops' or something like that.
>
Sure, something like 'struct ath11k_bus_ops' in ath11k_base struct would
be appropriate.
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 05/19] ath11k: Remove core PCI references from PCI common code
2022-02-21 6:55 ` Manikanta Pubbisetty
@ 2022-02-21 9:17 ` Kalle Valo
2022-02-21 10:08 ` Manikanta Pubbisetty
0 siblings, 1 reply; 49+ messages in thread
From: Kalle Valo @ 2022-02-21 9:17 UTC (permalink / raw)
To: Manikanta Pubbisetty; +Cc: ath11k, linux-wireless, devicetree, robh
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
> On 1/28/2022 3:50 PM, Kalle Valo wrote:
>> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>>
>>> Remove core PCI and ath11k PCI references(struct ath11k_pci)
>>> from PCI common code. Since, PCI common code will be used
>>> by hybrid bus devices, this code should be independent
>>> from ATH11K PCI references and Linux core PCI references
>>> like struct pci_dev.
>>>
>>> Since this change introduces function callbacks for bus wakeup
>>> and bus release operations, wakeup_mhi HW param is no longer
>>> needed and hence it is removed completely. Alternatively, bus
>>> wakeup/release ops for QCA9074 are initialized to NULL as
>>> QCA9704 does not need bus wakeup/release for register accesses.
>>>
>>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>>
>>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>>
>> [...]
>>
>>> @@ -651,6 +653,13 @@ struct ath11k_bus_params {
>>> bool fixed_bdf_addr;
>>> bool fixed_mem_region;
>>> bool static_window_map;
>>> + struct {
>>> + void (*wakeup)(struct ath11k_base *ab);
>>> + void (*release)(struct ath11k_base *ab);
>>> + int (*get_msi_irq)(struct ath11k_base *ab, unsigned int vector);
>>> + void (*window_write32)(struct ath11k_base *ab, u32 offset, u32 value);
>>> + u32 (*window_read32)(struct ath11k_base *ab, u32 offset);
>>> + } ops;
>>> };
>>
>> Please don't use bus_params for this, I'm starting to suspect that we
>> actually need to remove struct ath11k_bus_params altogether. It would be
>> cleaner to have separate 'struct ath11k_pci_ops' or something like that.
>>
>
> Sure, something like 'struct ath11k_bus_ops' in ath11k_base struct
> would be appropriate.
But we have 'struct ath11k_hif_ops' already, and that's basically
ath11k_bus_ops with a confusing name :) (IIRC HIF means Host InterFace,
or something like that.) So having both ath11k_bus_ops and
ath11k_hif_ops would become even more confusing.
You are basically abstracting out PCI functionality, that's why I
suggested ath11k_pci_ops. But yeah, naming is hard :)
--
https://patchwork.kernel.org/project/linux-wireless/list/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 05/19] ath11k: Remove core PCI references from PCI common code
2022-02-21 9:17 ` Kalle Valo
@ 2022-02-21 10:08 ` Manikanta Pubbisetty
0 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-02-21 10:08 UTC (permalink / raw)
To: Kalle Valo; +Cc: ath11k, linux-wireless, devicetree, robh
On 2/21/2022 2:47 PM, Kalle Valo wrote:
> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>
>> On 1/28/2022 3:50 PM, Kalle Valo wrote:
>>> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>>>
>>>> Remove core PCI and ath11k PCI references(struct ath11k_pci)
>>>> from PCI common code. Since, PCI common code will be used
>>>> by hybrid bus devices, this code should be independent
>>>> from ATH11K PCI references and Linux core PCI references
>>>> like struct pci_dev.
>>>>
>>>> Since this change introduces function callbacks for bus wakeup
>>>> and bus release operations, wakeup_mhi HW param is no longer
>>>> needed and hence it is removed completely. Alternatively, bus
>>>> wakeup/release ops for QCA9074 are initialized to NULL as
>>>> QCA9704 does not need bus wakeup/release for register accesses.
>>>>
>>>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>>>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>>>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>>>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>>>
>>>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>>>
>>> [...]
>>>
>>>> @@ -651,6 +653,13 @@ struct ath11k_bus_params {
>>>> bool fixed_bdf_addr;
>>>> bool fixed_mem_region;
>>>> bool static_window_map;
>>>> + struct {
>>>> + void (*wakeup)(struct ath11k_base *ab);
>>>> + void (*release)(struct ath11k_base *ab);
>>>> + int (*get_msi_irq)(struct ath11k_base *ab, unsigned int vector);
>>>> + void (*window_write32)(struct ath11k_base *ab, u32 offset, u32 value);
>>>> + u32 (*window_read32)(struct ath11k_base *ab, u32 offset);
>>>> + } ops;
>>>> };
>>>
>>> Please don't use bus_params for this, I'm starting to suspect that we
>>> actually need to remove struct ath11k_bus_params altogether. It would be
>>> cleaner to have separate 'struct ath11k_pci_ops' or something like that.
>>>
>>
>> Sure, something like 'struct ath11k_bus_ops' in ath11k_base struct
>> would be appropriate.
>
> But we have 'struct ath11k_hif_ops' already, and that's basically
> ath11k_bus_ops with a confusing name :) (IIRC HIF means Host InterFace,
> or something like that.) So having both ath11k_bus_ops and
> ath11k_hif_ops would become even more confusing.
>
> You are basically abstracting out PCI functionality, that's why I
> suggested ath11k_pci_ops. But yeah, naming is hard :)
>
Hmmm, makes sense :)
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 06/19] ath11k: Add HW params for WCN6750
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
` (4 preceding siblings ...)
2022-01-16 12:47 ` [PATCH v2 05/19] ath11k: Remove core PCI references from PCI common code Manikanta Pubbisetty
@ 2022-01-16 12:47 ` Manikanta Pubbisetty
2022-01-16 12:47 ` [PATCH v2 07/19] ath11k: Add bus " Manikanta Pubbisetty
` (13 subsequent siblings)
19 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:47 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
Add HW params for WCN6750. It is similar to the HW params
of QCA6390 with few differences wrt DP APIs and register
offsets.
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/core.c | 58 ++++++++++++++++++++++++++++++++++
drivers/net/wireless/ath/ath11k/core.h | 1 +
drivers/net/wireless/ath/ath11k/qmi.h | 2 ++
3 files changed, 61 insertions(+)
diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c
index 90ac0b5..3acc3e4 100644
--- a/drivers/net/wireless/ath/ath11k/core.c
+++ b/drivers/net/wireless/ath/ath11k/core.c
@@ -408,6 +408,64 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.supports_rssi_stats = true,
.fw_wmi_diag_event = true,
},
+ {
+ .name = "wcn6750 hw1.0",
+ .hw_rev = ATH11K_HW_WCN6750_HW10,
+ .fw = {
+ .dir = "WCN6750/hw1.0",
+ .board_size = 256 * 1024,
+ .cal_offset = 128 * 1024,
+ },
+ .max_radios = 1,
+ .bdf_addr = 0x4B0C0000,
+ .ring_mask = &ath11k_hw_ring_mask_qca6390,
+ .internal_sleep_clock = false,
+ .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750,
+ .host_ce_config = ath11k_host_ce_config_qca6390,
+ .ce_count = 9,
+ .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
+ .target_ce_count = 9,
+ .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
+ .svc_to_ce_map_len = 14,
+ .rfkill_pin = 0,
+ .rfkill_cfg = 0,
+ .rfkill_on_level = 0,
+ .single_pdev_only = true,
+ .rxdma1_enable = false,
+ .num_rxmda_per_pdev = 1,
+ .rx_mac_buf_ring = true,
+ .vdev_start_delay = true,
+ .htt_peer_map_v2 = false,
+
+ .spectral = {
+ .fft_sz = 0,
+ .fft_pad_sz = 0,
+ .summary_pad_sz = 0,
+ .fft_hdr_len = 0,
+ .max_fft_bins = 0,
+ },
+
+ .interface_modes = BIT(NL80211_IFTYPE_STATION) |
+ BIT(NL80211_IFTYPE_AP),
+ .supports_monitor = false,
+ .supports_shadow_regs = true,
+ .idle_ps = true,
+ .supports_sta_ps = true,
+ .cold_boot_calib = false,
+ .fw_mem_mode = 0,
+ .num_vdevs = 16 + 1,
+ .num_peers = 512,
+ .supports_suspend = false,
+ .supports_regdb = true,
+ .fix_l1ss = true,
+ .credit_flow = true,
+ .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
+ .hal_params = &ath11k_hw_hal_params_qca6390,
+ .supports_dynamic_smps_6ghz = false,
+ .alloc_cacheable_memory = false,
+ .supports_rssi_stats = true,
+ .fw_wmi_diag_event = false,
+ },
};
int ath11k_core_suspend(struct ath11k_base *ab)
diff --git a/drivers/net/wireless/ath/ath11k/core.h b/drivers/net/wireless/ath/ath11k/core.h
index 9dd1904..803d977 100644
--- a/drivers/net/wireless/ath/ath11k/core.h
+++ b/drivers/net/wireless/ath/ath11k/core.h
@@ -119,6 +119,7 @@ enum ath11k_hw_rev {
ATH11K_HW_QCN9074_HW10,
ATH11K_HW_WCN6855_HW20,
ATH11K_HW_WCN6855_HW21,
+ ATH11K_HW_WCN6750_HW10,
};
enum ath11k_firmware_mode {
diff --git a/drivers/net/wireless/ath/ath11k/qmi.h b/drivers/net/wireless/ath/ath11k/qmi.h
index ba2eff4..404dbf8 100644
--- a/drivers/net/wireless/ath/ath11k/qmi.h
+++ b/drivers/net/wireless/ath/ath11k/qmi.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef ATH11K_QMI_H
@@ -20,6 +21,7 @@
#define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390 0x01
#define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074 0x02
#define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074 0x07
+#define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750 0x03
#define ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32
#define ATH11K_QMI_RESP_LEN_MAX 8192
#define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 07/19] ath11k: Add bus params for WCN6750
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
` (5 preceding siblings ...)
2022-01-16 12:47 ` [PATCH v2 06/19] ath11k: Add HW params for WCN6750 Manikanta Pubbisetty
@ 2022-01-16 12:47 ` Manikanta Pubbisetty
2022-01-16 12:47 ` [PATCH v2 08/19] ath11k: Add register access logic " Manikanta Pubbisetty
` (12 subsequent siblings)
19 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:47 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
WCN6750 is a PCIe based solution that is attached to and enumerated
by the WPSS (Wireless Processor SubSystem) Q6 processor.
Though it is a PCIe device, since it is not attached to APSS processor
(Application Processor SubSystem), APSS will be unaware of such a decice
and hence it is registered to the APSS processor as a platform device(AHB).
Because of this hybrid nature, it is called as a hybrid bus device.
A new variable is defined in bus params to indicate the hybrid nature.
Add bus params for WCN6750.
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/ahb.c | 9 +++++++++
drivers/net/wireless/ath/ath11k/ahb.h | 2 ++
drivers/net/wireless/ath/ath11k/core.h | 1 +
3 files changed, 12 insertions(+)
diff --git a/drivers/net/wireless/ath/ath11k/ahb.c b/drivers/net/wireless/ath/ath11k/ahb.c
index 3fb0aa0..6167d4f 100644
--- a/drivers/net/wireless/ath/ath11k/ahb.c
+++ b/drivers/net/wireless/ath/ath11k/ahb.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/module.h>
@@ -35,6 +36,14 @@ static const struct ath11k_bus_params ath11k_ahb_bus_params = {
.fixed_mem_region = true,
};
+const struct ath11k_bus_params ath11k_hybrid_bus_params = {
+ .mhi_support = false,
+ .m3_fw_support = false,
+ .fixed_bdf_addr = false,
+ .fixed_mem_region = false,
+ .hybrid_bus_type = true,
+};
+
#define ATH11K_IRQ_CE0_OFFSET 4
static const char *irq_name[ATH11K_IRQ_NUM_MAX] = {
diff --git a/drivers/net/wireless/ath/ath11k/ahb.h b/drivers/net/wireless/ath/ath11k/ahb.h
index 51e6e4a..a97f2dd 100644
--- a/drivers/net/wireless/ath/ath11k/ahb.h
+++ b/drivers/net/wireless/ath/ath11k/ahb.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef ATH11K_AHB_H
#define ATH11K_AHB_H
@@ -9,6 +10,7 @@
#define ATH11K_AHB_RECOVERY_TIMEOUT (3 * HZ)
struct ath11k_base;
+extern const struct ath11k_bus_params ath11k_hybrid_bus_params;
struct ath11k_ahb {
struct rproc *tgt_rproc;
diff --git a/drivers/net/wireless/ath/ath11k/core.h b/drivers/net/wireless/ath/ath11k/core.h
index 803d977..c6cd2de 100644
--- a/drivers/net/wireless/ath/ath11k/core.h
+++ b/drivers/net/wireless/ath/ath11k/core.h
@@ -654,6 +654,7 @@ struct ath11k_bus_params {
bool fixed_bdf_addr;
bool fixed_mem_region;
bool static_window_map;
+ bool hybrid_bus_type;
struct {
void (*wakeup)(struct ath11k_base *ab);
void (*release)(struct ath11k_base *ab);
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 08/19] ath11k: Add register access logic for WCN6750
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
` (6 preceding siblings ...)
2022-01-16 12:47 ` [PATCH v2 07/19] ath11k: Add bus " Manikanta Pubbisetty
@ 2022-01-16 12:47 ` Manikanta Pubbisetty
2022-01-16 12:47 ` [PATCH v2 09/19] ath11k: Fetch device information via QMI " Manikanta Pubbisetty
` (11 subsequent siblings)
19 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:47 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
WCN6750 uses static window mapping to access the HW registers.
Unlike QCN9074 which uses 2nd window for CE and 3rd window
for UMAC register accesses, WCN6750 uses 1st window for UMAC
and 2nd window for CE registers.
Code is refactored so that WCN6750 can use the existing
ath11k_pci_read/write() APIs for accessing the registers.
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/ahb.c | 3 +++
drivers/net/wireless/ath/ath11k/core.h | 2 ++
drivers/net/wireless/ath/ath11k/pci.c | 4 ++++
drivers/net/wireless/ath/ath11k/pci_cmn.c | 35 ++++++++++---------------------
4 files changed, 20 insertions(+), 24 deletions(-)
diff --git a/drivers/net/wireless/ath/ath11k/ahb.c b/drivers/net/wireless/ath/ath11k/ahb.c
index 6167d4f..ed3a439 100644
--- a/drivers/net/wireless/ath/ath11k/ahb.c
+++ b/drivers/net/wireless/ath/ath11k/ahb.c
@@ -42,6 +42,9 @@ const struct ath11k_bus_params ath11k_hybrid_bus_params = {
.fixed_bdf_addr = false,
.fixed_mem_region = false,
.hybrid_bus_type = true,
+ .static_window_map = true,
+ .dp_window_idx = 1,
+ .ce_window_idx = 2,
};
#define ATH11K_IRQ_CE0_OFFSET 4
diff --git a/drivers/net/wireless/ath/ath11k/core.h b/drivers/net/wireless/ath/ath11k/core.h
index c6cd2de..92c1ea1 100644
--- a/drivers/net/wireless/ath/ath11k/core.h
+++ b/drivers/net/wireless/ath/ath11k/core.h
@@ -655,6 +655,8 @@ struct ath11k_bus_params {
bool fixed_mem_region;
bool static_window_map;
bool hybrid_bus_type;
+ u8 dp_window_idx;
+ u8 ce_window_idx;
struct {
void (*wakeup)(struct ath11k_base *ab);
void (*release)(struct ath11k_base *ab);
diff --git a/drivers/net/wireless/ath/ath11k/pci.c b/drivers/net/wireless/ath/ath11k/pci.c
index 4f2fe72..07bfb86 100644
--- a/drivers/net/wireless/ath/ath11k/pci.c
+++ b/drivers/net/wireless/ath/ath11k/pci.c
@@ -765,6 +765,10 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
ab->bus_params.ops.wakeup = NULL;
ab->bus_params.ops.release = NULL;
ab->hw_rev = ATH11K_HW_QCN9074_HW10;
+
+ /* For QCN9074, CE: 2nd window, UMAC: 3rd window */
+ ab->bus_params.ce_window_idx = 2;
+ ab->bus_params.dp_window_idx = 3;
break;
case WCN6855_DEVICE_ID:
ab->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD;
diff --git a/drivers/net/wireless/ath/ath11k/pci_cmn.c b/drivers/net/wireless/ath/ath11k/pci_cmn.c
index a5b84b5..fede1d06d 100644
--- a/drivers/net/wireless/ath/ath11k/pci_cmn.c
+++ b/drivers/net/wireless/ath/ath11k/pci_cmn.c
@@ -122,16 +122,13 @@ int ath11k_pci_get_msi_config(struct ath11k_base *ab)
static inline u32 ath11k_pci_get_window_start(struct ath11k_base *ab,
u32 offset)
{
- u32 window_start;
+ u32 window_start = 0;
- /* If offset lies within DP register range, use 3rd window */
if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
- window_start = 3 * ATH11K_PCI_WINDOW_START;
- /* If offset lies within CE register range, use 2nd window */
- else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < ATH11K_PCI_WINDOW_RANGE_MASK)
- window_start = 2 * ATH11K_PCI_WINDOW_START;
- else
- window_start = ATH11K_PCI_WINDOW_START;
+ window_start = ab->bus_params.dp_window_idx * ATH11K_PCI_WINDOW_START;
+ else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) <
+ ATH11K_PCI_WINDOW_RANGE_MASK)
+ window_start = ab->bus_params.ce_window_idx * ATH11K_PCI_WINDOW_START;
return window_start;
}
@@ -151,17 +148,12 @@ void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value)
if (offset < ATH11K_PCI_WINDOW_START) {
iowrite32(value, ab->mem + offset);
} else {
- if (ab->bus_params.static_window_map)
+ if (ab->bus_params.static_window_map) {
window_start = ath11k_pci_get_window_start(ab, offset);
- else
- window_start = ATH11K_PCI_WINDOW_START;
-
- if (window_start == ATH11K_PCI_WINDOW_START &&
- ab->bus_params.ops.window_write32) {
- ab->bus_params.ops.window_write32(ab, offset, value);
- } else {
iowrite32(value, ab->mem + window_start +
(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
+ } else if (ab->bus_params.ops.window_write32) {
+ ab->bus_params.ops.window_write32(ab, offset, value);
}
}
@@ -186,17 +178,12 @@ u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset)
if (offset < ATH11K_PCI_WINDOW_START) {
val = ioread32(ab->mem + offset);
} else {
- if (ab->bus_params.static_window_map)
+ if (ab->bus_params.static_window_map) {
window_start = ath11k_pci_get_window_start(ab, offset);
- else
- window_start = ATH11K_PCI_WINDOW_START;
-
- if (window_start == ATH11K_PCI_WINDOW_START &&
- ab->bus_params.ops.window_read32) {
- val = ab->bus_params.ops.window_read32(ab, offset);
- } else {
val = ioread32(ab->mem + window_start +
(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
+ } else if (ab->bus_params.ops.window_read32) {
+ val = ab->bus_params.ops.window_read32(ab, offset);
}
}
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 09/19] ath11k: Fetch device information via QMI for WCN6750
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
` (7 preceding siblings ...)
2022-01-16 12:47 ` [PATCH v2 08/19] ath11k: Add register access logic " Manikanta Pubbisetty
@ 2022-01-16 12:47 ` Manikanta Pubbisetty
2022-01-16 12:47 ` [PATCH v2 10/19] ath11k: Add QMI changes " Manikanta Pubbisetty
` (10 subsequent siblings)
19 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:47 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
Since WPPS Q6 does the PCIe enumeration of WCN6750, device
information like BAR and BAR size is not known to the APPS
processor (Application Processor SubSystem). In order to
fetch these details, a QMI message called device info request
will be sent to the target. Therefore, add logic to fetch
BAR details from the target.
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/qmi.c | 144 ++++++++++++++++++++++++++++++++++
drivers/net/wireless/ath/ath11k/qmi.h | 24 +++++-
2 files changed, 164 insertions(+), 4 deletions(-)
diff --git a/drivers/net/wireless/ath/ath11k/qmi.c b/drivers/net/wireless/ath/ath11k/qmi.c
index 42c2ad3..ee59cb9 100644
--- a/drivers/net/wireless/ath/ath11k/qmi.c
+++ b/drivers/net/wireless/ath/ath11k/qmi.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/elf.h>
@@ -12,6 +13,8 @@
#include <linux/of_address.h>
#include <linux/ioport.h>
#include <linux/firmware.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
#define SLEEP_CLOCK_SELECT_INTERNAL_BIT 0x02
#define HOST_CSTATE_BIT 0x04
@@ -745,6 +748,68 @@ static struct qmi_elem_info qmi_wlanfw_cap_req_msg_v01_ei[] = {
},
};
+static struct qmi_elem_info qmi_wlanfw_device_info_req_msg_v01_ei[] = {
+ {
+ .data_type = QMI_EOTI,
+ .array_type = NO_ARRAY,
+ .tlv_type = QMI_COMMON_TLV_TYPE,
+ },
+};
+
+static struct qmi_elem_info qmi_wlfw_device_info_resp_msg_v01_ei[] = {
+ {
+ .data_type = QMI_STRUCT,
+ .elem_len = 1,
+ .elem_size = sizeof(struct qmi_response_type_v01),
+ .array_type = NO_ARRAY,
+ .tlv_type = 0x02,
+ .offset = offsetof(struct qmi_wlanfw_device_info_resp_msg_v01,
+ resp),
+ .ei_array = qmi_response_type_v01_ei,
+ },
+ {
+ .data_type = QMI_OPT_FLAG,
+ .elem_len = 1,
+ .elem_size = sizeof(u8),
+ .array_type = NO_ARRAY,
+ .tlv_type = 0x10,
+ .offset = offsetof(struct qmi_wlanfw_device_info_resp_msg_v01,
+ bar_addr_valid),
+ },
+ {
+ .data_type = QMI_UNSIGNED_8_BYTE,
+ .elem_len = 1,
+ .elem_size = sizeof(u64),
+ .array_type = NO_ARRAY,
+ .tlv_type = 0x10,
+ .offset = offsetof(struct qmi_wlanfw_device_info_resp_msg_v01,
+ bar_addr),
+ },
+ {
+ .data_type = QMI_OPT_FLAG,
+ .elem_len = 1,
+ .elem_size = sizeof(u8),
+ .array_type = NO_ARRAY,
+ .tlv_type = 0x11,
+ .offset = offsetof(struct qmi_wlanfw_device_info_resp_msg_v01,
+ bar_size_valid),
+ },
+ {
+ .data_type = QMI_UNSIGNED_4_BYTE,
+ .elem_len = 1,
+ .elem_size = sizeof(u32),
+ .array_type = NO_ARRAY,
+ .tlv_type = 0x11,
+ .offset = offsetof(struct qmi_wlanfw_device_info_resp_msg_v01,
+ bar_size),
+ },
+ {
+ .data_type = QMI_EOTI,
+ .array_type = NO_ARRAY,
+ .tlv_type = QMI_COMMON_TLV_TYPE,
+ },
+};
+
static struct qmi_elem_info qmi_wlanfw_rf_chip_info_s_v01_ei[] = {
{
.data_type = QMI_UNSIGNED_4_BYTE,
@@ -2001,6 +2066,79 @@ static int ath11k_qmi_assign_target_mem_chunk(struct ath11k_base *ab)
return 0;
}
+static int ath11k_qmi_request_device_info(struct ath11k_base *ab)
+{
+ struct qmi_wlanfw_device_info_req_msg_v01 req = {};
+ struct qmi_wlanfw_device_info_resp_msg_v01 resp = {};
+ struct qmi_txn txn;
+ void __iomem *bar_addr_va;
+ int ret;
+
+ /* device info message req is only sent for hybrid bus devices */
+ if (!ab->bus_params.hybrid_bus_type)
+ return 0;
+
+ ret = qmi_txn_init(&ab->qmi.handle, &txn,
+ qmi_wlfw_device_info_resp_msg_v01_ei, &resp);
+ if (ret < 0)
+ goto out;
+
+ ret = qmi_send_request(&ab->qmi.handle, NULL, &txn,
+ QMI_WLANFW_DEVICE_INFO_REQ_V01,
+ QMI_WLANFW_DEVICE_INFO_REQ_MSG_V01_MAX_LEN,
+ qmi_wlanfw_device_info_req_msg_v01_ei, &req);
+ if (ret < 0) {
+ qmi_txn_cancel(&txn);
+ ath11k_warn(ab, "qmi failed to send target device info request, err = %d\n",
+ ret);
+ goto out;
+ }
+
+ ret = qmi_txn_wait(&txn, msecs_to_jiffies(ATH11K_QMI_WLANFW_TIMEOUT_MS));
+ if (ret < 0) {
+ ath11k_warn(ab, "qmi failed target device info request %d\n", ret);
+ goto out;
+ }
+
+ if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
+ ath11k_warn(ab, "qmi device info req failed, result: %d, err: %d\n",
+ resp.resp.result, resp.resp.error);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (!resp.bar_addr_valid || !resp.bar_size_valid) {
+ ath11k_warn(ab, "qmi device info response invalid, result: %d, err: %d\n",
+ resp.resp.result, resp.resp.error);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (!resp.bar_addr ||
+ resp.bar_size != ATH11K_QMI_DEVICE_BAR_SIZE) {
+ ath11k_warn(ab, "qmi device info invalid addr and size, result: %d, err: %d\n",
+ resp.resp.result, resp.resp.error);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ bar_addr_va = devm_ioremap(ab->dev, resp.bar_addr, resp.bar_size);
+
+ if (!bar_addr_va) {
+ ath11k_warn(ab, "qmi device info ioremap failed\n");
+ ab->mem_len = 0;
+ ret = -EIO;
+ goto out;
+ }
+
+ ab->mem = bar_addr_va;
+ ab->mem_len = resp.bar_size;
+
+ return 0;
+out:
+ return ret;
+}
+
static int ath11k_qmi_request_target_cap(struct ath11k_base *ab)
{
struct qmi_wlanfw_cap_req_msg_v01 req;
@@ -2730,6 +2868,12 @@ static int ath11k_qmi_event_load_bdf(struct ath11k_qmi *qmi)
return ret;
}
+ ret = ath11k_qmi_request_device_info(ab);
+ if (ret < 0) {
+ ath11k_warn(ab, "failed to request qmi device info %d\n", ret);
+ return ret;
+ }
+
if (ab->hw_params.supports_regdb)
ath11k_qmi_load_bdf_qmi(ab, true);
diff --git a/drivers/net/wireless/ath/ath11k/qmi.h b/drivers/net/wireless/ath/ath11k/qmi.h
index 404dbf8..593d81ed 100644
--- a/drivers/net/wireless/ath/ath11k/qmi.h
+++ b/drivers/net/wireless/ath/ath11k/qmi.h
@@ -38,6 +38,8 @@
#define ATH11K_FIRMWARE_MODE_OFF 4
#define ATH11K_COLD_BOOT_FW_RESET_DELAY (40 * HZ)
+#define ATH11K_QMI_DEVICE_BAR_SIZE 0x200000
+
struct ath11k_base;
enum ath11k_qmi_file_type {
@@ -287,10 +289,12 @@ struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01 {
char placeholder;
};
-#define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0
-#define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 235
-#define QMI_WLANFW_CAP_REQ_V01 0x0024
-#define QMI_WLANFW_CAP_RESP_V01 0x0024
+#define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0
+#define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 235
+#define QMI_WLANFW_CAP_REQ_V01 0x0024
+#define QMI_WLANFW_CAP_RESP_V01 0x0024
+#define QMI_WLANFW_DEVICE_INFO_REQ_V01 0x004C
+#define QMI_WLANFW_DEVICE_INFO_REQ_MSG_V01_MAX_LEN 0
enum qmi_wlanfw_pipedir_enum_v01 {
QMI_WLFW_PIPEDIR_NONE_V01 = 0,
@@ -383,6 +387,18 @@ struct qmi_wlanfw_cap_req_msg_v01 {
char placeholder;
};
+struct qmi_wlanfw_device_info_req_msg_v01 {
+ char placeholder;
+};
+
+struct qmi_wlanfw_device_info_resp_msg_v01 {
+ struct qmi_response_type_v01 resp;
+ u64 bar_addr;
+ u32 bar_size;
+ u8 bar_addr_valid;
+ u8 bar_size_valid;
+};
+
#define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182
#define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7
#define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 10/19] ath11k: Add QMI changes for WCN6750
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
` (8 preceding siblings ...)
2022-01-16 12:47 ` [PATCH v2 09/19] ath11k: Fetch device information via QMI " Manikanta Pubbisetty
@ 2022-01-16 12:47 ` Manikanta Pubbisetty
2022-01-28 10:50 ` Kalle Valo
2022-01-16 12:47 ` [PATCH v2 11/19] ath11k: HAL changes to support WCN6750 Manikanta Pubbisetty
` (9 subsequent siblings)
19 siblings, 1 reply; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:47 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
In the case of WCN6750, FW doesn't request for DDR memory
via QMI, instead it uses a fixed 12MB reserved Memory region
in the DDR which is called as MSA region. As a result, QMI
message sequence is not same as other ath11k supported devices.
Also, M3 firmware will be bundled into the FW and will be
downloaded to the target as part of Q6 boot.
This is the QMI flow in the case of WCN6750,
1) QMI firmware indication REQ/RESP
2) QMI host capability REQ/RESP
3) QMI target capability REQ/RESP
4) QMI device info REQ/RESP
5) QMI BDF download
6) QMI FW ready
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/qmi.c | 73 +++++++++++++++++++++++------------
1 file changed, 48 insertions(+), 25 deletions(-)
diff --git a/drivers/net/wireless/ath/ath11k/qmi.c b/drivers/net/wireless/ath/ath11k/qmi.c
index ee59cb9..4745ff9 100644
--- a/drivers/net/wireless/ath/ath11k/qmi.c
+++ b/drivers/net/wireless/ath/ath11k/qmi.c
@@ -1793,10 +1793,6 @@ static int ath11k_qmi_fw_ind_register_send(struct ath11k_base *ab)
req->client_id = QMI_WLANFW_CLIENT_ID;
req->fw_ready_enable_valid = 1;
req->fw_ready_enable = 1;
- req->request_mem_enable_valid = 1;
- req->request_mem_enable = 1;
- req->fw_mem_ready_enable_valid = 1;
- req->fw_mem_ready_enable = 1;
req->cal_done_enable_valid = 1;
req->cal_done_enable = 1;
req->fw_init_done_enable_valid = 1;
@@ -1805,6 +1801,17 @@ static int ath11k_qmi_fw_ind_register_send(struct ath11k_base *ab)
req->pin_connect_result_enable_valid = 0;
req->pin_connect_result_enable = 0;
+ /* WCN6750 doesn't request for DDR memory via QMI,
+ * instead it uses a fixed 12MB reserved memory
+ * region in DDR.
+ */
+ if (!ab->bus_params.hybrid_bus_type) {
+ req->request_mem_enable_valid = 1;
+ req->request_mem_enable = 1;
+ req->fw_mem_ready_enable_valid = 1;
+ req->fw_mem_ready_enable = 1;
+ }
+
ret = qmi_txn_init(handle, &txn,
qmi_wlanfw_ind_register_resp_msg_v01_ei, resp);
if (ret < 0)
@@ -2490,6 +2497,13 @@ static int ath11k_qmi_wlanfw_m3_info_send(struct ath11k_base *ab)
struct qmi_txn txn;
int ret = 0;
+ /* In the case of WCN6750, M3 is bundled into the FW
+ * binary, and will be downloaded as part of Q6 boot.
+ */
+ if (!ab->bus_params.m3_fw_support &&
+ ab->bus_params.hybrid_bus_type)
+ return 0;
+
memset(&req, 0, sizeof(req));
memset(&resp, 0, sizeof(resp));
@@ -2821,27 +2835,6 @@ ath11k_qmi_driver_event_post(struct ath11k_qmi *qmi,
return 0;
}
-static int ath11k_qmi_event_server_arrive(struct ath11k_qmi *qmi)
-{
- struct ath11k_base *ab = qmi->ab;
- int ret;
-
- ret = ath11k_qmi_fw_ind_register_send(ab);
- if (ret < 0) {
- ath11k_warn(ab, "failed to send qmi firmware indication: %d\n",
- ret);
- return ret;
- }
-
- ret = ath11k_qmi_host_cap_send(ab);
- if (ret < 0) {
- ath11k_warn(ab, "failed to send qmi host cap: %d\n", ret);
- return ret;
- }
-
- return ret;
-}
-
static int ath11k_qmi_event_mem_request(struct ath11k_qmi *qmi)
{
struct ath11k_base *ab = qmi->ab;
@@ -2892,6 +2885,36 @@ static int ath11k_qmi_event_load_bdf(struct ath11k_qmi *qmi)
return ret;
}
+static int ath11k_qmi_event_server_arrive(struct ath11k_qmi *qmi)
+{
+ struct ath11k_base *ab = qmi->ab;
+ int ret;
+
+ ret = ath11k_qmi_fw_ind_register_send(ab);
+ if (ret < 0) {
+ ath11k_warn(ab, "failed to send qmi firmware indication: %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = ath11k_qmi_host_cap_send(ab);
+ if (ret < 0) {
+ ath11k_warn(ab, "failed to send qmi host cap: %d\n", ret);
+ return ret;
+ }
+
+ if (!ab->bus_params.hybrid_bus_type)
+ return ret;
+
+ ret = ath11k_qmi_event_load_bdf(qmi);
+ if (ret < 0) {
+ ath11k_warn(ab, "qmi failed to download BDF:%d\n", ret);
+ return ret;
+ }
+
+ return ret;
+}
+
static void ath11k_qmi_msg_mem_request_cb(struct qmi_handle *qmi_hdl,
struct sockaddr_qrtr *sq,
struct qmi_txn *txn,
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCH v2 10/19] ath11k: Add QMI changes for WCN6750
2022-01-16 12:47 ` [PATCH v2 10/19] ath11k: Add QMI changes " Manikanta Pubbisetty
@ 2022-01-28 10:50 ` Kalle Valo
2022-02-21 8:02 ` Manikanta Pubbisetty
0 siblings, 1 reply; 49+ messages in thread
From: Kalle Valo @ 2022-01-28 10:50 UTC (permalink / raw)
To: Manikanta Pubbisetty; +Cc: ath11k, linux-wireless, devicetree, robh
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
> In the case of WCN6750, FW doesn't request for DDR memory
> via QMI, instead it uses a fixed 12MB reserved Memory region
> in the DDR which is called as MSA region. As a result, QMI
> message sequence is not same as other ath11k supported devices.
>
> Also, M3 firmware will be bundled into the FW and will be
> downloaded to the target as part of Q6 boot.
>
> This is the QMI flow in the case of WCN6750,
>
> 1) QMI firmware indication REQ/RESP
> 2) QMI host capability REQ/RESP
> 3) QMI target capability REQ/RESP
> 4) QMI device info REQ/RESP
> 5) QMI BDF download
> 6) QMI FW ready
>
> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>
> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
[...]
> @@ -2490,6 +2497,13 @@ static int ath11k_qmi_wlanfw_m3_info_send(struct ath11k_base *ab)
> struct qmi_txn txn;
> int ret = 0;
>
> + /* In the case of WCN6750, M3 is bundled into the FW
> + * binary, and will be downloaded as part of Q6 boot.
> + */
> + if (!ab->bus_params.m3_fw_support &&
> + ab->bus_params.hybrid_bus_type)
> + return 0;
A check like this makes me think if it's just better to m3_fw_support to
ath11k_hw_params. That way you could disable m3 for WCN6750 via
hw_params.
--
https://patchwork.kernel.org/project/linux-wireless/list/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 10/19] ath11k: Add QMI changes for WCN6750
2022-01-28 10:50 ` Kalle Valo
@ 2022-02-21 8:02 ` Manikanta Pubbisetty
0 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-02-21 8:02 UTC (permalink / raw)
To: Kalle Valo; +Cc: ath11k, linux-wireless, devicetree, robh
On 1/28/2022 4:20 PM, Kalle Valo wrote:
> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>
>> In the case of WCN6750, FW doesn't request for DDR memory
>> via QMI, instead it uses a fixed 12MB reserved Memory region
>> in the DDR which is called as MSA region. As a result, QMI
>> message sequence is not same as other ath11k supported devices.
>>
>> Also, M3 firmware will be bundled into the FW and will be
>> downloaded to the target as part of Q6 boot.
>>
>> This is the QMI flow in the case of WCN6750,
>>
>> 1) QMI firmware indication REQ/RESP
>> 2) QMI host capability REQ/RESP
>> 3) QMI target capability REQ/RESP
>> 4) QMI device info REQ/RESP
>> 5) QMI BDF download
>> 6) QMI FW ready
>>
>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>
>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>
> [...]
>
>> @@ -2490,6 +2497,13 @@ static int ath11k_qmi_wlanfw_m3_info_send(struct ath11k_base *ab)
>> struct qmi_txn txn;
>> int ret = 0;
>>
>> + /* In the case of WCN6750, M3 is bundled into the FW
>> + * binary, and will be downloaded as part of Q6 boot.
>> + */
>> + if (!ab->bus_params.m3_fw_support &&
>> + ab->bus_params.hybrid_bus_type)
>> + return 0;
>
> A check like this makes me think if it's just better to m3_fw_support to
> ath11k_hw_params. That way you could disable m3 for WCN6750 via
> hw_params.
>
You are right, it's better to have a hw_param instead.
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 11/19] ath11k: HAL changes to support WCN6750
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
` (9 preceding siblings ...)
2022-01-16 12:47 ` [PATCH v2 10/19] ath11k: Add QMI changes " Manikanta Pubbisetty
@ 2022-01-16 12:47 ` Manikanta Pubbisetty
2022-01-16 12:47 ` [PATCH v2 12/19] ath11k: Datapath " Manikanta Pubbisetty
` (8 subsequent siblings)
19 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:47 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
Add HAL changes required to support WCN6750. Offsets of some registers
for WCN6750 are different from other supported devices; move such
register offsets to platform specific ath11k_hw_regs.
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/core.c | 2 +
drivers/net/wireless/ath/ath11k/hal.c | 15 ++--
drivers/net/wireless/ath/ath11k/hal.h | 15 ++--
drivers/net/wireless/ath/ath11k/hw.c | 134 +++++++++++++++++++++++++++++++++
drivers/net/wireless/ath/ath11k/hw.h | 11 +++
5 files changed, 164 insertions(+), 13 deletions(-)
diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c
index 3acc3e4..347131a 100644
--- a/drivers/net/wireless/ath/ath11k/core.c
+++ b/drivers/net/wireless/ath/ath11k/core.c
@@ -418,8 +418,10 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
},
.max_radios = 1,
.bdf_addr = 0x4B0C0000,
+ .hw_ops = &wcn6750_ops,
.ring_mask = &ath11k_hw_ring_mask_qca6390,
.internal_sleep_clock = false,
+ .regs = &wcn6750_regs,
.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750,
.host_ce_config = ath11k_host_ce_config_qca6390,
.ce_count = 9,
diff --git a/drivers/net/wireless/ath/ath11k/hal.c b/drivers/net/wireless/ath/ath11k/hal.c
index 2ec09ae..9a6340d 100644
--- a/drivers/net/wireless/ath/ath11k/hal.c
+++ b/drivers/net/wireless/ath/ath11k/hal.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/dma-mapping.h>
#include "hal_tx.h"
@@ -1082,10 +1083,10 @@ static void ath11k_hal_srng_update_hp_tp_addr(struct ath11k_base *ab,
srng = &hal->srng_list[ring_id];
if (srng_config->ring_dir == HAL_SRNG_DIR_DST)
- srng->u.dst_ring.tp_addr = (u32 *)(HAL_SHADOW_REG(shadow_cfg_idx) +
+ srng->u.dst_ring.tp_addr = (u32 *)(HAL_SHADOW_REG(ab, shadow_cfg_idx) +
(unsigned long)ab->mem);
else
- srng->u.src_ring.hp_addr = (u32 *)(HAL_SHADOW_REG(shadow_cfg_idx) +
+ srng->u.src_ring.hp_addr = (u32 *)(HAL_SHADOW_REG(ab, shadow_cfg_idx) +
(unsigned long)ab->mem);
}
@@ -1120,7 +1121,7 @@ int ath11k_hal_srng_update_shadow_config(struct ath11k_base *ab,
ath11k_dbg(ab, ATH11k_DBG_HAL,
"target_reg %x, shadow reg 0x%x shadow_idx 0x%x, ring_type %d, ring num %d",
target_reg,
- HAL_SHADOW_REG(shadow_cfg_idx),
+ HAL_SHADOW_REG(ab, shadow_cfg_idx),
shadow_cfg_idx,
ring_type, ring_num);
@@ -1193,12 +1194,12 @@ static int ath11k_hal_srng_create_config(struct ath11k_base *ab)
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_HP(ab);
s = &hal->srng_config[HAL_REO_REINJECT];
- s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB;
- s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP;
+ s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(ab);
+ s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP(ab);
s = &hal->srng_config[HAL_REO_CMD];
- s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB;
- s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP;
+ s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(ab);
+ s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP(ab);
s = &hal->srng_config[HAL_REO_STATUS];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(ab);
diff --git a/drivers/net/wireless/ath/ath11k/hal.h b/drivers/net/wireless/ath/ath11k/hal.h
index a7d9b4c..6fbda01 100644
--- a/drivers/net/wireless/ath/ath11k/hal.h
+++ b/drivers/net/wireless/ath/ath11k/hal.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef ATH11K_HAL_H
@@ -31,12 +32,12 @@ struct ath11k_base;
#define HAL_DSCP_TID_TBL_SIZE 24
/* calculate the register address from bar0 of shadow register x */
-#define HAL_SHADOW_BASE_ADDR 0x000008fc
+#define HAL_SHADOW_BASE_ADDR(ab) ab->hw_params.regs->hal_shadow_base_addr
#define HAL_SHADOW_NUM_REGS 36
#define HAL_HP_OFFSET_IN_REG_START 1
#define HAL_OFFSET_FROM_HP_TO_TP 4
-#define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x)))
+#define HAL_SHADOW_REG(ab, x) (HAL_SHADOW_BASE_ADDR(ab) + (4 * (x)))
/* WCSS Relative address */
#define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000
@@ -180,16 +181,18 @@ struct ath11k_base;
#define HAL_REO_TCL_RING_HP(ab) ab->hw_params.regs->hal_reo_tcl_ring_hp
/* REO CMD R0 address */
-#define HAL_REO_CMD_RING_BASE_LSB 0x00000194
+#define HAL_REO_CMD_RING_BASE_LSB(ab) \
+ ab->hw_params.regs->hal_reo_cmd_ring_base_lsb
/* REO CMD R2 address */
-#define HAL_REO_CMD_HP 0x00003020
+#define HAL_REO_CMD_HP(ab) ab->hw_params.regs->hal_reo_cmd_ring_hp
/* SW2REO R0 address */
-#define HAL_SW2REO_RING_BASE_LSB 0x000001ec
+#define HAL_SW2REO_RING_BASE_LSB(ab) \
+ ab->hw_params.regs->hal_sw2reo_ring_base_lsb
/* SW2REO R2 address */
-#define HAL_SW2REO_RING_HP 0x00003028
+#define HAL_SW2REO_RING_HP(ab) ab->hw_params.regs->hal_sw2reo_ring_hp
/* CE ring R0 address */
#define HAL_CE_DST_RING_BASE_LSB 0x00000000
diff --git a/drivers/net/wireless/ath/ath11k/hw.c b/drivers/net/wireless/ath/ath11k/hw.c
index b7e3b66..8d921a6 100644
--- a/drivers/net/wireless/ath/ath11k/hw.c
+++ b/drivers/net/wireless/ath/ath11k/hw.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) 2018-2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/types.h>
@@ -1007,6 +1008,13 @@ const struct ath11k_hw_ops wcn6855_ops = {
.rx_desc_mpdu_start_addr2 = ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2,
};
+const struct ath11k_hw_ops wcn6750_ops = {
+ .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
+ .wmi_init_config = ath11k_init_wmi_config_qca6390,
+ .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
+ .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
+};
+
#define ATH11K_TX_RING_MASK_0 0x1
#define ATH11K_TX_RING_MASK_1 0x2
#define ATH11K_TX_RING_MASK_2 0x4
@@ -1901,10 +1909,18 @@ const struct ath11k_hw_regs ipq8074_regs = {
.hal_reo_tcl_ring_base_lsb = 0x000003fc,
.hal_reo_tcl_ring_hp = 0x00003058,
+ /* REO CMD ring address */
+ .hal_reo_cmd_ring_base_lsb = 0x00000194,
+ .hal_reo_cmd_ring_hp = 0x00003020,
+
/* REO status address */
.hal_reo_status_ring_base_lsb = 0x00000504,
.hal_reo_status_hp = 0x00003070,
+ /* SW2REO ring address */
+ .hal_sw2reo_ring_base_lsb = 0x000001ec,
+ .hal_sw2reo_ring_hp = 0x00003028,
+
/* WCSS relative address */
.hal_seq_wcss_umac_ce0_src_reg = 0x00a00000,
.hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000,
@@ -1925,6 +1941,9 @@ const struct ath11k_hw_regs ipq8074_regs = {
/* PCIe base address */
.pcie_qserdes_sysclk_en_sel = 0x0,
.pcie_pcs_osc_dtct_config_base = 0x0,
+
+ /* Shadow register area */
+ .hal_shadow_base_addr = 0x0,
};
const struct ath11k_hw_regs qca6390_regs = {
@@ -1972,10 +1991,18 @@ const struct ath11k_hw_regs qca6390_regs = {
.hal_reo_tcl_ring_base_lsb = 0x000003a4,
.hal_reo_tcl_ring_hp = 0x00003050,
+ /* REO CMD ring address */
+ .hal_reo_cmd_ring_base_lsb = 0x00000194,
+ .hal_reo_cmd_ring_hp = 0x00003020,
+
/* REO status address */
.hal_reo_status_ring_base_lsb = 0x000004ac,
.hal_reo_status_hp = 0x00003068,
+ /* SW2REO ring address */
+ .hal_sw2reo_ring_base_lsb = 0x000001ec,
+ .hal_sw2reo_ring_hp = 0x00003028,
+
/* WCSS relative address */
.hal_seq_wcss_umac_ce0_src_reg = 0x00a00000,
.hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000,
@@ -1996,6 +2023,9 @@ const struct ath11k_hw_regs qca6390_regs = {
/* PCIe base address */
.pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
.pcie_pcs_osc_dtct_config_base = 0x01e0c628,
+
+ /* Shadow register area */
+ .hal_shadow_base_addr = 0x000008fc,
};
const struct ath11k_hw_regs qcn9074_regs = {
@@ -2043,10 +2073,18 @@ const struct ath11k_hw_regs qcn9074_regs = {
.hal_reo_tcl_ring_base_lsb = 0x000003fc,
.hal_reo_tcl_ring_hp = 0x00003058,
+ /* REO CMD ring address */
+ .hal_reo_cmd_ring_base_lsb = 0x00000194,
+ .hal_reo_cmd_ring_hp = 0x00003020,
+
/* REO status address */
.hal_reo_status_ring_base_lsb = 0x00000504,
.hal_reo_status_hp = 0x00003070,
+ /* SW2REO ring address */
+ .hal_sw2reo_ring_base_lsb = 0x000001ec,
+ .hal_sw2reo_ring_hp = 0x00003028,
+
/* WCSS relative address */
.hal_seq_wcss_umac_ce0_src_reg = 0x01b80000,
.hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000,
@@ -2067,6 +2105,9 @@ const struct ath11k_hw_regs qcn9074_regs = {
/* PCIe base address */
.pcie_qserdes_sysclk_en_sel = 0x01e0e0a8,
.pcie_pcs_osc_dtct_config_base = 0x01e0f45c,
+
+ /* Shadow register area */
+ .hal_shadow_base_addr = 0x0,
};
const struct ath11k_hw_regs wcn6855_regs = {
@@ -2114,10 +2155,18 @@ const struct ath11k_hw_regs wcn6855_regs = {
.hal_reo_tcl_ring_base_lsb = 0x00000454,
.hal_reo_tcl_ring_hp = 0x00003060,
+ /* REO CMD ring address */
+ .hal_reo_cmd_ring_base_lsb = 0x00000194,
+ .hal_reo_cmd_ring_hp = 0x00003020,
+
/* REO status address */
.hal_reo_status_ring_base_lsb = 0x0000055c,
.hal_reo_status_hp = 0x00003078,
+ /* SW2REO ring address */
+ .hal_sw2reo_ring_base_lsb = 0x000001ec,
+ .hal_sw2reo_ring_hp = 0x00003028,
+
/* WCSS relative address */
.hal_seq_wcss_umac_ce0_src_reg = 0x1b80000,
.hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000,
@@ -2138,6 +2187,91 @@ const struct ath11k_hw_regs wcn6855_regs = {
/* PCIe base address */
.pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
.pcie_pcs_osc_dtct_config_base = 0x01e0c628,
+
+ /* Shadow register area */
+ .hal_shadow_base_addr = 0x000008fc,
+};
+
+const struct ath11k_hw_regs wcn6750_regs = {
+ /* SW2TCL(x) R0 ring configuration address */
+ .hal_tcl1_ring_base_lsb = 0x00000694,
+ .hal_tcl1_ring_base_msb = 0x00000698,
+ .hal_tcl1_ring_id = 0x0000069c,
+ .hal_tcl1_ring_misc = 0x000006a4,
+ .hal_tcl1_ring_tp_addr_lsb = 0x000006b0,
+ .hal_tcl1_ring_tp_addr_msb = 0x000006b4,
+ .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4,
+ .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8,
+ .hal_tcl1_ring_msi1_base_lsb = 0x000006dc,
+ .hal_tcl1_ring_msi1_base_msb = 0x000006e0,
+ .hal_tcl1_ring_msi1_data = 0x000006e4,
+ .hal_tcl2_ring_base_lsb = 0x000006ec,
+ .hal_tcl_ring_base_lsb = 0x0000079c,
+
+ /* TCL STATUS ring address */
+ .hal_tcl_status_ring_base_lsb = 0x000008a4,
+
+ /* REO2SW(x) R0 ring configuration address */
+ .hal_reo1_ring_base_lsb = 0x000001ec,
+ .hal_reo1_ring_base_msb = 0x000001f0,
+ .hal_reo1_ring_id = 0x000001f4,
+ .hal_reo1_ring_misc = 0x000001fc,
+ .hal_reo1_ring_hp_addr_lsb = 0x00000200,
+ .hal_reo1_ring_hp_addr_msb = 0x00000204,
+ .hal_reo1_ring_producer_int_setup = 0x00000210,
+ .hal_reo1_ring_msi1_base_lsb = 0x00000234,
+ .hal_reo1_ring_msi1_base_msb = 0x00000238,
+ .hal_reo1_ring_msi1_data = 0x0000023c,
+ .hal_reo2_ring_base_lsb = 0x00000244,
+ .hal_reo1_aging_thresh_ix_0 = 0x00000564,
+ .hal_reo1_aging_thresh_ix_1 = 0x00000568,
+ .hal_reo1_aging_thresh_ix_2 = 0x0000056c,
+ .hal_reo1_aging_thresh_ix_3 = 0x00000570,
+
+ /* REO2SW(x) R2 ring pointers (head/tail) address */
+ .hal_reo1_ring_hp = 0x00003028,
+ .hal_reo1_ring_tp = 0x0000302c,
+ .hal_reo2_ring_hp = 0x00003030,
+
+ /* REO2TCL R0 ring configuration address */
+ .hal_reo_tcl_ring_base_lsb = 0x000003fc,
+ .hal_reo_tcl_ring_hp = 0x00003058,
+
+ /* REO CMD ring address */
+ .hal_reo_cmd_ring_base_lsb = 0x000000e4,
+ .hal_reo_cmd_ring_hp = 0x00003010,
+
+ /* REO status address */
+ .hal_reo_status_ring_base_lsb = 0x00000504,
+ .hal_reo_status_hp = 0x00003070,
+
+ /* SW2REO ring address */
+ .hal_sw2reo_ring_base_lsb = 0x0000013c,
+ .hal_sw2reo_ring_hp = 0x00003018,
+
+ /* WCSS relative address */
+ .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000,
+ .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000,
+ .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000,
+ .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000,
+
+ /* WBM Idle address */
+ .hal_wbm_idle_link_ring_base_lsb = 0x00000874,
+ .hal_wbm_idle_link_ring_misc = 0x00000884,
+
+ /* SW2WBM release address */
+ .hal_wbm_release_ring_base_lsb = 0x000001ec,
+
+ /* WBM2SW release address */
+ .hal_wbm0_release_ring_base_lsb = 0x00000924,
+ .hal_wbm1_release_ring_base_lsb = 0x0000097c,
+
+ /* PCIe base address */
+ .pcie_qserdes_sysclk_en_sel = 0x0,
+ .pcie_pcs_osc_dtct_config_base = 0x0,
+
+ /* Shadow register area */
+ .hal_shadow_base_addr = 0x00000504,
};
const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = {
diff --git a/drivers/net/wireless/ath/ath11k/hw.h b/drivers/net/wireless/ath/ath11k/hw.h
index ab258a0..cb48d52 100644
--- a/drivers/net/wireless/ath/ath11k/hw.h
+++ b/drivers/net/wireless/ath/ath11k/hw.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef ATH11K_HW_H
@@ -240,6 +241,7 @@ extern const struct ath11k_hw_ops ipq6018_ops;
extern const struct ath11k_hw_ops qca6390_ops;
extern const struct ath11k_hw_ops qcn9074_ops;
extern const struct ath11k_hw_ops wcn6855_ops;
+extern const struct ath11k_hw_ops wcn6750_ops;
extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;
extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;
@@ -336,6 +338,12 @@ struct ath11k_hw_regs {
u32 hal_reo_status_ring_base_lsb;
u32 hal_reo_status_hp;
+ u32 hal_reo_cmd_ring_base_lsb;
+ u32 hal_reo_cmd_ring_hp;
+
+ u32 hal_sw2reo_ring_base_lsb;
+ u32 hal_sw2reo_ring_hp;
+
u32 hal_seq_wcss_umac_ce0_src_reg;
u32 hal_seq_wcss_umac_ce0_dst_reg;
u32 hal_seq_wcss_umac_ce1_src_reg;
@@ -351,11 +359,14 @@ struct ath11k_hw_regs {
u32 pcie_qserdes_sysclk_en_sel;
u32 pcie_pcs_osc_dtct_config_base;
+
+ u32 hal_shadow_base_addr;
};
extern const struct ath11k_hw_regs ipq8074_regs;
extern const struct ath11k_hw_regs qca6390_regs;
extern const struct ath11k_hw_regs qcn9074_regs;
extern const struct ath11k_hw_regs wcn6855_regs;
+extern const struct ath11k_hw_regs wcn6750_regs;
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 12/19] ath11k: Datapath changes to support WCN6750
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
` (10 preceding siblings ...)
2022-01-16 12:47 ` [PATCH v2 11/19] ath11k: HAL changes to support WCN6750 Manikanta Pubbisetty
@ 2022-01-16 12:47 ` Manikanta Pubbisetty
2022-04-27 5:32 ` Kalle Valo
2022-01-16 12:47 ` [PATCH v2 13/19] ath11k: Fix RX de-fragmentation issue on WCN6750 Manikanta Pubbisetty
` (7 subsequent siblings)
19 siblings, 1 reply; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:47 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
HAL RX descriptor for WCN6750 is same as QCN9074, so use
the DP APIs of QCN9074 for WCN6750. There is one change
wrt to REO configuration though, REO configuration for
WCN6750 is same as WCN6855; Therefore, use reo_setup()
of WCN6855 for WCN6750.
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/core.c | 1 +
drivers/net/wireless/ath/ath11k/hw.c | 31 +++++++++++++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c
index 347131a..f65347c 100644
--- a/drivers/net/wireless/ath/ath11k/core.c
+++ b/drivers/net/wireless/ath/ath11k/core.c
@@ -458,6 +458,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.num_vdevs = 16 + 1,
.num_peers = 512,
.supports_suspend = false,
+ .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
.supports_regdb = true,
.fix_l1ss = true,
.credit_flow = true,
diff --git a/drivers/net/wireless/ath/ath11k/hw.c b/drivers/net/wireless/ath/ath11k/hw.c
index 8d921a6..2bc2232 100644
--- a/drivers/net/wireless/ath/ath11k/hw.c
+++ b/drivers/net/wireless/ath/ath11k/hw.c
@@ -1013,6 +1013,37 @@ const struct ath11k_hw_ops wcn6750_ops = {
.wmi_init_config = ath11k_init_wmi_config_qca6390,
.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
+ .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable,
+ .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu,
+ .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu,
+ .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes,
+ .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status,
+ .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid,
+ .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type,
+ .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type,
+ .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl,
+ .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld,
+ .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid,
+ .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no,
+ .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len,
+ .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi,
+ .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs,
+ .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw,
+ .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq,
+ .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type,
+ .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss,
+ .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid,
+ .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id,
+ .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end,
+ .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag,
+ .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id,
+ .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len,
+ .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention,
+ .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
+ .reo_setup = ath11k_hw_wcn6855_reo_setup,
+ .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
+ .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid,
+ .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2,
};
#define ATH11K_TX_RING_MASK_0 0x1
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCH v2 12/19] ath11k: Datapath changes to support WCN6750
2022-01-16 12:47 ` [PATCH v2 12/19] ath11k: Datapath " Manikanta Pubbisetty
@ 2022-04-27 5:32 ` Kalle Valo
2022-04-27 5:37 ` Manikanta Pubbisetty
0 siblings, 1 reply; 49+ messages in thread
From: Kalle Valo @ 2022-04-27 5:32 UTC (permalink / raw)
To: Manikanta Pubbisetty; +Cc: ath11k, linux-wireless, devicetree, robh
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
> HAL RX descriptor for WCN6750 is same as QCN9074, so use
> the DP APIs of QCN9074 for WCN6750. There is one change
> wrt to REO configuration though, REO configuration for
> WCN6750 is same as WCN6855; Therefore, use reo_setup()
> of WCN6855 for WCN6750.
>
> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>
> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
> ---
> drivers/net/wireless/ath/ath11k/core.c | 1 +
> drivers/net/wireless/ath/ath11k/hw.c | 31 +++++++++++++++++++++++++++++++
> 2 files changed, 32 insertions(+)
>
> diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c
> index 347131a..f65347c 100644
> --- a/drivers/net/wireless/ath/ath11k/core.c
> +++ b/drivers/net/wireless/ath/ath11k/core.c
> @@ -458,6 +458,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
> .num_vdevs = 16 + 1,
> .num_peers = 512,
> .supports_suspend = false,
> + .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
You mention nothing about this change in the commit log, I'll add that.
--
https://patchwork.kernel.org/project/linux-wireless/list/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 12/19] ath11k: Datapath changes to support WCN6750
2022-04-27 5:32 ` Kalle Valo
@ 2022-04-27 5:37 ` Manikanta Pubbisetty
2022-04-27 5:48 ` Kalle Valo
0 siblings, 1 reply; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-04-27 5:37 UTC (permalink / raw)
To: Kalle Valo; +Cc: ath11k, linux-wireless, devicetree, robh
On 4/27/2022 11:02 AM, Kalle Valo wrote:
> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>
>> HAL RX descriptor for WCN6750 is same as QCN9074, so use
>> the DP APIs of QCN9074 for WCN6750. There is one change
>> wrt to REO configuration though, REO configuration for
>> WCN6750 is same as WCN6855; Therefore, use reo_setup()
>> of WCN6855 for WCN6750.
>>
>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>
>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>> ---
>> drivers/net/wireless/ath/ath11k/core.c | 1 +
>> drivers/net/wireless/ath/ath11k/hw.c | 31 +++++++++++++++++++++++++++++++
>> 2 files changed, 32 insertions(+)
>>
>> diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c
>> index 347131a..f65347c 100644
>> --- a/drivers/net/wireless/ath/ath11k/core.c
>> +++ b/drivers/net/wireless/ath/ath11k/core.c
>> @@ -458,6 +458,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
>> .num_vdevs = 16 + 1,
>> .num_peers = 512,
>> .supports_suspend = false,
>> + .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
>
> You mention nothing about this change in the commit log, I'll add that.
>
I did mention that "HAL RX descriptor for WCN6750 is same as QCN9074",
you were looking at something specific?
Thanks,
Manikanta
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 12/19] ath11k: Datapath changes to support WCN6750
2022-04-27 5:37 ` Manikanta Pubbisetty
@ 2022-04-27 5:48 ` Kalle Valo
2022-04-27 5:56 ` Manikanta Pubbisetty
0 siblings, 1 reply; 49+ messages in thread
From: Kalle Valo @ 2022-04-27 5:48 UTC (permalink / raw)
To: Manikanta Pubbisetty; +Cc: ath11k, linux-wireless, devicetree, robh
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
> On 4/27/2022 11:02 AM, Kalle Valo wrote:
>> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>>
>>> HAL RX descriptor for WCN6750 is same as QCN9074, so use
>>> the DP APIs of QCN9074 for WCN6750. There is one change
>>> wrt to REO configuration though, REO configuration for
>>> WCN6750 is same as WCN6855; Therefore, use reo_setup()
>>> of WCN6855 for WCN6750.
>>>
>>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>>
>>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>>> ---
>>> drivers/net/wireless/ath/ath11k/core.c | 1 +
>>> drivers/net/wireless/ath/ath11k/hw.c | 31 +++++++++++++++++++++++++++++++
>>> 2 files changed, 32 insertions(+)
>>>
>>> diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c
>>> index 347131a..f65347c 100644
>>> --- a/drivers/net/wireless/ath/ath11k/core.c
>>> +++ b/drivers/net/wireless/ath/ath11k/core.c
>>> @@ -458,6 +458,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
>>> .num_vdevs = 16 + 1,
>>> .num_peers = 512,
>>> .supports_suspend = false,
>>> + .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
>>
>> You mention nothing about this change in the commit log, I'll add that.
>>
>
> I did mention that "HAL RX descriptor for WCN6750 is same as QCN9074",
> you were looking at something specific?
If I'm understanding correctly, by accident hal_desc_sz was not
initialised for qcn9074. If that's the case, it would be good to mention
that in the commit log.
--
https://patchwork.kernel.org/project/linux-wireless/list/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 12/19] ath11k: Datapath changes to support WCN6750
2022-04-27 5:48 ` Kalle Valo
@ 2022-04-27 5:56 ` Manikanta Pubbisetty
2022-04-29 8:56 ` Kalle Valo
0 siblings, 1 reply; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-04-27 5:56 UTC (permalink / raw)
To: Kalle Valo; +Cc: ath11k, linux-wireless, devicetree, robh
On 4/27/2022 11:18 AM, Kalle Valo wrote:
> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>
>> On 4/27/2022 11:02 AM, Kalle Valo wrote:
>>> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>>>
>>>> HAL RX descriptor for WCN6750 is same as QCN9074, so use
>>>> the DP APIs of QCN9074 for WCN6750. There is one change
>>>> wrt to REO configuration though, REO configuration for
>>>> WCN6750 is same as WCN6855; Therefore, use reo_setup()
>>>> of WCN6855 for WCN6750.
>>>>
>>>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>>>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>>>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>>>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>>>
>>>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>>>> ---
>>>> drivers/net/wireless/ath/ath11k/core.c | 1 +
>>>> drivers/net/wireless/ath/ath11k/hw.c | 31 +++++++++++++++++++++++++++++++
>>>> 2 files changed, 32 insertions(+)
>>>>
>>>> diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c
>>>> index 347131a..f65347c 100644
>>>> --- a/drivers/net/wireless/ath/ath11k/core.c
>>>> +++ b/drivers/net/wireless/ath/ath11k/core.c
>>>> @@ -458,6 +458,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
>>>> .num_vdevs = 16 + 1,
>>>> .num_peers = 512,
>>>> .supports_suspend = false,
>>>> + .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
>>>
>>> You mention nothing about this change in the commit log, I'll add that.
>>>
>>
>> I did mention that "HAL RX descriptor for WCN6750 is same as QCN9074",
>> you were looking at something specific?
>
> If I'm understanding correctly, by accident hal_desc_sz was not
> initialised for qcn9074. If that's the case, it would be good to mention
> that in the commit log.
>
If I understand your comment correctly, since HAL RX descriptor is
related to data path, I thought of adding it as part of the data path
patch.
Thanks,
Manikanta
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 12/19] ath11k: Datapath changes to support WCN6750
2022-04-27 5:56 ` Manikanta Pubbisetty
@ 2022-04-29 8:56 ` Kalle Valo
0 siblings, 0 replies; 49+ messages in thread
From: Kalle Valo @ 2022-04-29 8:56 UTC (permalink / raw)
To: Manikanta Pubbisetty; +Cc: ath11k, linux-wireless, devicetree, robh
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
> On 4/27/2022 11:18 AM, Kalle Valo wrote:
>> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>>
>>> On 4/27/2022 11:02 AM, Kalle Valo wrote:
>>>> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>>>>
>>>>> HAL RX descriptor for WCN6750 is same as QCN9074, so use
>>>>> the DP APIs of QCN9074 for WCN6750. There is one change
>>>>> wrt to REO configuration though, REO configuration for
>>>>> WCN6750 is same as WCN6855; Therefore, use reo_setup()
>>>>> of WCN6855 for WCN6750.
>>>>>
>>>>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>>>>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>>>>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>>>>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>>>>
>>>>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>>>>> ---
>>>>> drivers/net/wireless/ath/ath11k/core.c | 1 +
>>>>> drivers/net/wireless/ath/ath11k/hw.c | 31 +++++++++++++++++++++++++++++++
>>>>> 2 files changed, 32 insertions(+)
>>>>>
>>>>> diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c
>>>>> index 347131a..f65347c 100644
>>>>> --- a/drivers/net/wireless/ath/ath11k/core.c
>>>>> +++ b/drivers/net/wireless/ath/ath11k/core.c
>>>>> @@ -458,6 +458,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
>>>>> .num_vdevs = 16 + 1,
>>>>> .num_peers = 512,
>>>>> .supports_suspend = false,
>>>>> + .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
>>>>
>>>> You mention nothing about this change in the commit log, I'll add that.
>>>>
>>>
>>> I did mention that "HAL RX descriptor for WCN6750 is same as QCN9074",
>>> you were looking at something specific?
>>
>> If I'm understanding correctly, by accident hal_desc_sz was not
>> initialised for qcn9074. If that's the case, it would be good to mention
>> that in the commit log.
>>
>
> If I understand your comment correctly, since HAL RX descriptor is
> related to data path, I thought of adding it as part of the data path
> patch.
Ah, now I understand better. I thought you were setting hal_desc_sz for
qcn9074, but now I checked it and you were actually setting it for
wcn6750. It would be better to set hal_desc_sz in patch "ath11k: Add HW
params for WCN6750".
Actually I would prefer that _all_ existing hw_params fields for wcn6750
would be initialised in patch "ath11k: Add HW params for WCN6750", even
if just set to null or invalid values. That way it's easier to track
that we are not missing any fields and makes it easier to review other
patches. But this is getting more to nitpicking so definitely not a hard
requirement.
--
https://patchwork.kernel.org/project/linux-wireless/list/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 13/19] ath11k: Fix RX de-fragmentation issue on WCN6750
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
` (11 preceding siblings ...)
2022-01-16 12:47 ` [PATCH v2 12/19] ath11k: Datapath " Manikanta Pubbisetty
@ 2022-01-16 12:47 ` Manikanta Pubbisetty
2022-01-16 12:47 ` [PATCH v2 14/19] ath11k: Do not put HW in DBS mode for WCN6750 Manikanta Pubbisetty
` (6 subsequent siblings)
19 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:47 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
The offset of REO register where the RX fragment destination ring
is configured is different in WCN6750 as compared to WCN6855.
Due to this differnce in offsets, on WCN6750, fragment destination
ring will be configured incorrectly, leading to RX fragments not
getting delivered to the driver. Fix this by defining HW specific
offset for the REO MISC CTL register.
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/hal.h | 2 +-
drivers/net/wireless/ath/ath11k/hw.c | 10 ++++++++--
drivers/net/wireless/ath/ath11k/hw.h | 1 +
3 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/net/wireless/ath/ath11k/hal.h b/drivers/net/wireless/ath/ath11k/hal.h
index 6fbda01..347d456 100644
--- a/drivers/net/wireless/ath/ath11k/hal.h
+++ b/drivers/net/wireless/ath/ath11k/hal.h
@@ -121,7 +121,7 @@ struct ath11k_base;
#define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008
#define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c
#define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010
-#define HAL_REO1_MISC_CTL 0x00000630
+#define HAL_REO1_MISC_CTL(ab) ab->hw_params.regs->hal_reo1_misc_ctl
#define HAL_REO1_RING_BASE_LSB(ab) ab->hw_params.regs->hal_reo1_ring_base_lsb
#define HAL_REO1_RING_BASE_MSB(ab) ab->hw_params.regs->hal_reo1_ring_base_msb
#define HAL_REO1_RING_ID(ab) ab->hw_params.regs->hal_reo1_ring_id
diff --git a/drivers/net/wireless/ath/ath11k/hw.c b/drivers/net/wireless/ath/ath11k/hw.c
index 2bc2232..c19f9101 100644
--- a/drivers/net/wireless/ath/ath11k/hw.c
+++ b/drivers/net/wireless/ath/ath11k/hw.c
@@ -771,10 +771,10 @@ static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab)
FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
- val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL);
+ val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL(ab));
val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING;
val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING, HAL_SRNG_RING_ID_REO2SW1);
- ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL, val);
+ ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL(ab), val);
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
HAL_DEFAULT_REO_TIMEOUT_USEC);
@@ -2221,6 +2221,9 @@ const struct ath11k_hw_regs wcn6855_regs = {
/* Shadow register area */
.hal_shadow_base_addr = 0x000008fc,
+
+ /* REO MISC CTRL */
+ .hal_reo1_misc_ctl = 0x00000630,
};
const struct ath11k_hw_regs wcn6750_regs = {
@@ -2303,6 +2306,9 @@ const struct ath11k_hw_regs wcn6750_regs = {
/* Shadow register area */
.hal_shadow_base_addr = 0x00000504,
+
+ /* REO MISC CTRL */
+ .hal_reo1_misc_ctl = 0x000005d8,
};
const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = {
diff --git a/drivers/net/wireless/ath/ath11k/hw.h b/drivers/net/wireless/ath/ath11k/hw.h
index cb48d52..a220c9a 100644
--- a/drivers/net/wireless/ath/ath11k/hw.h
+++ b/drivers/net/wireless/ath/ath11k/hw.h
@@ -361,6 +361,7 @@ struct ath11k_hw_regs {
u32 pcie_pcs_osc_dtct_config_base;
u32 hal_shadow_base_addr;
+ u32 hal_reo1_misc_ctl;
};
extern const struct ath11k_hw_regs ipq8074_regs;
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 14/19] ath11k: Do not put HW in DBS mode for WCN6750
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
` (12 preceding siblings ...)
2022-01-16 12:47 ` [PATCH v2 13/19] ath11k: Fix RX de-fragmentation issue on WCN6750 Manikanta Pubbisetty
@ 2022-01-16 12:47 ` Manikanta Pubbisetty
2022-01-16 12:47 ` [PATCH v2 15/19] ath11k: WMI changes to support WCN6750 Manikanta Pubbisetty
` (5 subsequent siblings)
19 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:47 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
Though WCN6750 is a single PDEV device, it is not a
DBS solution. So, do not put HW in DBS mode for WCN6750.
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/core.c | 2 +-
drivers/net/wireless/ath/ath11k/wmi.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c
index f65347c..7208849 100644
--- a/drivers/net/wireless/ath/ath11k/core.c
+++ b/drivers/net/wireless/ath/ath11k/core.c
@@ -1084,7 +1084,7 @@ static int ath11k_core_start(struct ath11k_base *ab,
}
/* put hardware to DBS mode */
- if (ab->hw_params.single_pdev_only) {
+ if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxmda_per_pdev > 1) {
ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS);
if (ret) {
ath11k_err(ab, "failed to send dbs mode: %d\n", ret);
diff --git a/drivers/net/wireless/ath/ath11k/wmi.c b/drivers/net/wireless/ath/ath11k/wmi.c
index 6b68ccf6..0cc8957 100644
--- a/drivers/net/wireless/ath/ath11k/wmi.c
+++ b/drivers/net/wireless/ath/ath11k/wmi.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/skbuff.h>
#include <linux/ctype.h>
@@ -7851,7 +7852,7 @@ int ath11k_wmi_attach(struct ath11k_base *ab)
ab->wmi_ab.preferred_hw_mode = WMI_HOST_HW_MODE_MAX;
/* It's overwritten when service_ext_ready is handled */
- if (ab->hw_params.single_pdev_only)
+ if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxmda_per_pdev > 1)
ab->wmi_ab.preferred_hw_mode = WMI_HOST_HW_MODE_SINGLE;
/* TODO: Init remaining wmi soc resources required */
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 15/19] ath11k: WMI changes to support WCN6750
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
` (13 preceding siblings ...)
2022-01-16 12:47 ` [PATCH v2 14/19] ath11k: Do not put HW in DBS mode for WCN6750 Manikanta Pubbisetty
@ 2022-01-16 12:47 ` Manikanta Pubbisetty
2022-01-16 12:47 ` [PATCH v2 16/19] ath11k: Update WBM idle ring HP after FW mode on Manikanta Pubbisetty
` (4 subsequent siblings)
19 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:47 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
WCN6750 is a single PDEV non-DBS chip which supports 2G, 5G and 6G bands.
It is a single LMAC device which can be either hooked to 2G/5G/6G bands.
Add WMI changes to support WCN6750.
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/wmi.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/net/wireless/ath/ath11k/wmi.c b/drivers/net/wireless/ath/ath11k/wmi.c
index 0cc8957..ca7bb11 100644
--- a/drivers/net/wireless/ath/ath11k/wmi.c
+++ b/drivers/net/wireless/ath/ath11k/wmi.c
@@ -389,6 +389,10 @@ ath11k_pull_mac_phy_cap_svc_ready_ext(struct ath11k_pdev_wmi *wmi_handle,
ab->target_pdev_ids[ab->target_pdev_count].pdev_id = mac_phy_caps->pdev_id;
ab->target_pdev_count++;
+ if (!(mac_phy_caps->supported_bands & WMI_HOST_WLAN_2G_CAP) &&
+ !(mac_phy_caps->supported_bands & WMI_HOST_WLAN_5G_CAP))
+ return -EINVAL;
+
/* Take non-zero tx/rx chainmask. If tx/rx chainmask differs from
* band to band for a single radio, need to see how this should be
* handled.
@@ -396,7 +400,9 @@ ath11k_pull_mac_phy_cap_svc_ready_ext(struct ath11k_pdev_wmi *wmi_handle,
if (mac_phy_caps->supported_bands & WMI_HOST_WLAN_2G_CAP) {
pdev_cap->tx_chain_mask = mac_phy_caps->tx_chain_mask_2g;
pdev_cap->rx_chain_mask = mac_phy_caps->rx_chain_mask_2g;
- } else if (mac_phy_caps->supported_bands & WMI_HOST_WLAN_5G_CAP) {
+ }
+
+ if (mac_phy_caps->supported_bands & WMI_HOST_WLAN_5G_CAP) {
pdev_cap->vht_cap = mac_phy_caps->vht_cap_info_5g;
pdev_cap->vht_mcs = mac_phy_caps->vht_supp_mcs_5g;
pdev_cap->he_mcs = mac_phy_caps->he_supp_mcs_5g;
@@ -406,8 +412,6 @@ ath11k_pull_mac_phy_cap_svc_ready_ext(struct ath11k_pdev_wmi *wmi_handle,
WMI_NSS_RATIO_ENABLE_DISABLE_GET(mac_phy_caps->nss_ratio);
pdev_cap->nss_ratio_info =
WMI_NSS_RATIO_INFO_GET(mac_phy_caps->nss_ratio);
- } else {
- return -EINVAL;
}
/* tx/rx chainmask reported from fw depends on the actual hw chains used,
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 16/19] ath11k: Update WBM idle ring HP after FW mode on
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
` (14 preceding siblings ...)
2022-01-16 12:47 ` [PATCH v2 15/19] ath11k: WMI changes to support WCN6750 Manikanta Pubbisetty
@ 2022-01-16 12:47 ` Manikanta Pubbisetty
2022-01-16 12:47 ` [PATCH v2 17/19] ath11k: Add support for WCN6750 device Manikanta Pubbisetty
` (3 subsequent siblings)
19 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:47 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
Currently, WBM idle ring HP is updated much before the shadow
configuration is sent to the FW. Any update to the shadow
registers before FW mode on request would not be reflected
on to the actual HW registers failing to bring up the device.
Send FW mode ON QMI request before WBM idle ring HP update
to fix this problem.
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/ce.c | 4 +--
drivers/net/wireless/ath/ath11k/core.c | 45 +++++++++++++++++++++++-----------
2 files changed, 32 insertions(+), 17 deletions(-)
diff --git a/drivers/net/wireless/ath/ath11k/ce.c b/drivers/net/wireless/ath/ath11k/ce.c
index aaa7b05..c14c51f 100644
--- a/drivers/net/wireless/ath/ath11k/ce.c
+++ b/drivers/net/wireless/ath/ath11k/ce.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "dp_rx.h"
@@ -918,9 +919,6 @@ int ath11k_ce_init_pipes(struct ath11k_base *ab)
int i;
int ret;
- ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2,
- &ab->qmi.ce_cfg.shadow_reg_v2_len);
-
for (i = 0; i < ab->hw_params.ce_count; i++) {
pipe = &ab->ce.ce_pipe[i];
diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c
index 7208849..86373d6 100644
--- a/drivers/net/wireless/ath/ath11k/core.c
+++ b/drivers/net/wireless/ath/ath11k/core.c
@@ -995,21 +995,14 @@ static void ath11k_core_pdev_destroy(struct ath11k_base *ab)
ath11k_debugfs_pdev_destroy(ab);
}
-static int ath11k_core_start(struct ath11k_base *ab,
- enum ath11k_firmware_mode mode)
+static int ath11k_core_start(struct ath11k_base *ab)
{
int ret;
- ret = ath11k_qmi_firmware_start(ab, mode);
- if (ret) {
- ath11k_err(ab, "failed to attach wmi: %d\n", ret);
- return ret;
- }
-
ret = ath11k_wmi_attach(ab);
if (ret) {
ath11k_err(ab, "failed to attach wmi: %d\n", ret);
- goto err_firmware_stop;
+ return ret;
}
ret = ath11k_htc_init(ab);
@@ -1109,8 +1102,23 @@ static int ath11k_core_start(struct ath11k_base *ab,
ath11k_hif_stop(ab);
err_wmi_detach:
ath11k_wmi_detach(ab);
-err_firmware_stop:
- ath11k_qmi_firmware_stop(ab);
+
+ return ret;
+}
+
+static int ath11k_core_start_firmware(struct ath11k_base *ab,
+ enum ath11k_firmware_mode mode)
+{
+ int ret;
+
+ ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2,
+ &ab->qmi.ce_cfg.shadow_reg_v2_len);
+
+ ret = ath11k_qmi_firmware_start(ab, mode);
+ if (ret) {
+ ath11k_err(ab, "failed to send firmware start: %d\n", ret);
+ return ret;
+ }
return ret;
}
@@ -1140,16 +1148,22 @@ int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
{
int ret;
+ ret = ath11k_core_start_firmware(ab, ATH11K_FIRMWARE_MODE_NORMAL);
+ if (ret) {
+ ath11k_err(ab, "failed to start firmware: %d\n", ret);
+ return ret;
+ }
+
ret = ath11k_ce_init_pipes(ab);
if (ret) {
ath11k_err(ab, "failed to initialize CE: %d\n", ret);
- return ret;
+ goto err_firmware_stop;
}
ret = ath11k_dp_alloc(ab);
if (ret) {
ath11k_err(ab, "failed to init DP: %d\n", ret);
- return ret;
+ goto err_firmware_stop;
}
switch (ath11k_crypto_mode) {
@@ -1170,7 +1184,7 @@ int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
mutex_lock(&ab->core_lock);
- ret = ath11k_core_start(ab, ATH11K_FIRMWARE_MODE_NORMAL);
+ ret = ath11k_core_start(ab);
if (ret) {
ath11k_err(ab, "failed to start core: %d\n", ret);
goto err_dp_free;
@@ -1199,6 +1213,9 @@ int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
err_dp_free:
ath11k_dp_free(ab);
mutex_unlock(&ab->core_lock);
+err_firmware_stop:
+ ath11k_qmi_firmware_stop(ab);
+
return ret;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 17/19] ath11k: Add support for WCN6750 device
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
` (15 preceding siblings ...)
2022-01-16 12:47 ` [PATCH v2 16/19] ath11k: Update WBM idle ring HP after FW mode on Manikanta Pubbisetty
@ 2022-01-16 12:47 ` Manikanta Pubbisetty
2022-01-16 12:47 ` [PATCH v2 18/19] ath11k: Add support for targets without trustzone Manikanta Pubbisetty
` (2 subsequent siblings)
19 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:47 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
WCN6750 is non-DBS 2x2 11AX chipset. Unlike QCA6390 which is a
DBS (dual band simultaneous) solution (2 LMACs), WCN6750 has a
single LMAC supporting 2G, 5G and 6G bands but will operate only
on one band at any given point.
WCN6750 is a PCIe based solution, but it is attached to the WPSS
(Wireless Processor SubSystem) Q6 processor, hence it is enumerated
by the Q6 processor. It is registered to the APSS processor
(Application Processor SubSystem) as a platform device(AHB) and
remoteproc APIs are used to boot up or shutdown the device like
other AHB devices.
Also, Device information like BAR and it's size is not known to the
APSS processor as the chip is enumerated by WPSS Q6. These details
are fetched over QMI.
STA and AP modes are supported. Verified basic connectivity and ping
in both the modes.
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/Makefile | 2 +-
drivers/net/wireless/ath/ath11k/ahb.c | 147 +++++++++++++++++++++++++++---
drivers/net/wireless/ath/ath11k/ahb.h | 1 -
drivers/net/wireless/ath/ath11k/core.h | 1 +
drivers/net/wireless/ath/ath11k/pci_cmn.c | 9 ++
5 files changed, 143 insertions(+), 17 deletions(-)
diff --git a/drivers/net/wireless/ath/ath11k/Makefile b/drivers/net/wireless/ath/ath11k/Makefile
index 71376da..e3ea6a2 100644
--- a/drivers/net/wireless/ath/ath11k/Makefile
+++ b/drivers/net/wireless/ath/ath11k/Makefile
@@ -26,7 +26,7 @@ ath11k-$(CONFIG_THERMAL) += thermal.o
ath11k-$(CONFIG_ATH11K_SPECTRAL) += spectral.o
obj-$(CONFIG_ATH11K_AHB) += ath11k_ahb.o
-ath11k_ahb-y += ahb.o
+ath11k_ahb-y += ahb.o pci_cmn.o
obj-$(CONFIG_ATH11K_PCI) += ath11k_pci.o
ath11k_pci-y += mhi.o pci.o pci_cmn.o
diff --git a/drivers/net/wireless/ath/ath11k/ahb.c b/drivers/net/wireless/ath/ath11k/ahb.c
index ed3a439..219592d 100644
--- a/drivers/net/wireless/ath/ath11k/ahb.c
+++ b/drivers/net/wireless/ath/ath11k/ahb.c
@@ -13,6 +13,7 @@
#include "debug.h"
#include "hif.h"
#include <linux/remoteproc.h>
+#include "pci_cmn.h"
static const struct of_device_id ath11k_ahb_of_match[] = {
/* TODO: Should we change the compatible string to something similar
@@ -24,19 +25,28 @@ static const struct of_device_id ath11k_ahb_of_match[] = {
{ .compatible = "qcom,ipq6018-wifi",
.data = (void *)ATH11K_HW_IPQ6018_HW10,
},
+ { .compatible = "qcom,wcn6750-wifi",
+ .data = (void *)ATH11K_HW_WCN6750_HW10,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, ath11k_ahb_of_match);
-static const struct ath11k_bus_params ath11k_ahb_bus_params = {
+static const struct ath11k_bus_params bus_params_ipq8074 = {
.mhi_support = false,
.m3_fw_support = false,
.fixed_bdf_addr = true,
.fixed_mem_region = true,
};
-const struct ath11k_bus_params ath11k_hybrid_bus_params = {
+static int
+ath11k_ahb_get_msi_irq_wcn6750(struct ath11k_base *ab, unsigned int vector)
+{
+ return ab->msi.irqs[vector];
+}
+
+static const struct ath11k_bus_params bus_params_wcn6750 = {
.mhi_support = false,
.m3_fw_support = false,
.fixed_bdf_addr = false,
@@ -45,6 +55,9 @@ const struct ath11k_bus_params ath11k_hybrid_bus_params = {
.static_window_map = true,
.dp_window_idx = 1,
.ce_window_idx = 2,
+ .ops = {
+ .get_msi_irq = ath11k_ahb_get_msi_irq_wcn6750,
+ },
};
#define ATH11K_IRQ_CE0_OFFSET 4
@@ -411,6 +424,9 @@ static void ath11k_ahb_free_irq(struct ath11k_base *ab)
int irq_idx;
int i;
+ if (ab->bus_params.hybrid_bus_type)
+ return ath11k_pci_free_irq(ab);
+
for (i = 0; i < ab->hw_params.ce_count; i++) {
if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
continue;
@@ -565,6 +581,9 @@ static int ath11k_ahb_config_irq(struct ath11k_base *ab)
int irq, irq_idx, i;
int ret;
+ if (ab->bus_params.hybrid_bus_type)
+ return ath11k_pci_config_irq(ab);
+
/* Configure CE irqs */
for (i = 0; i < ab->hw_params.ce_count; i++) {
struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
@@ -634,7 +653,7 @@ static int ath11k_ahb_map_service_to_pipe(struct ath11k_base *ab, u16 service_id
return 0;
}
-static const struct ath11k_hif_ops ath11k_ahb_hif_ops = {
+static const struct ath11k_hif_ops hif_ops_ipq8074 = {
.start = ath11k_ahb_start,
.stop = ath11k_ahb_stop,
.read32 = ath11k_ahb_read32,
@@ -646,6 +665,20 @@ static const struct ath11k_hif_ops ath11k_ahb_hif_ops = {
.power_up = ath11k_ahb_power_up,
};
+static const struct ath11k_hif_ops hif_ops_wcn6750 = {
+ .start = ath11k_pci_start_cmn,
+ .stop = ath11k_pci_stop,
+ .read32 = ath11k_pci_read32,
+ .write32 = ath11k_pci_write32,
+ .irq_enable = ath11k_pci_ext_irq_enable,
+ .irq_disable = ath11k_pci_ext_irq_disable,
+ .get_msi_address = ath11k_pci_get_msi_address,
+ .get_user_msi_vector = ath11k_pci_get_user_msi_assignment,
+ .map_service_to_pipe = ath11k_pci_map_service_to_pipe,
+ .power_down = ath11k_ahb_power_down,
+ .power_up = ath11k_ahb_power_up,
+};
+
static int ath11k_core_get_rproc(struct ath11k_base *ab)
{
struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
@@ -668,12 +701,84 @@ static int ath11k_core_get_rproc(struct ath11k_base *ab)
return 0;
}
+static int ath11k_ahb_setup_msi_resources(struct ath11k_base *ab)
+{
+ struct platform_device *pdev = ab->pdev;
+ phys_addr_t msi_addr_pa;
+ dma_addr_t msi_addr_iova;
+ struct resource *res;
+ int int_prop;
+ int ret;
+ int i;
+
+ ret = ath11k_pci_get_msi_config(ab);
+ if (ret) {
+ ath11k_err(ab, "failed to fetch msi config: %d\n", ret);
+ return ret;
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "msi_addr");
+ if (!res) {
+ ath11k_err(ab, "failed to fetch msi_addr\n");
+ return -ENOENT;
+ }
+
+ msi_addr_pa = res->start;
+ msi_addr_iova = dma_map_resource(ab->dev, msi_addr_pa, PAGE_SIZE,
+ DMA_FROM_DEVICE, 0);
+ if (dma_mapping_error(ab->dev, msi_addr_iova))
+ return -ENOMEM;
+
+ ab->msi.msi_addr_lo = lower_32_bits(msi_addr_iova);
+ ab->msi.msi_addr_hi = upper_32_bits(msi_addr_iova);
+
+ ret = of_property_read_u32_index(ab->dev->of_node, "interrupts", 1, &int_prop);
+ if (ret)
+ return ret;
+
+ ab->msi.msi_ep_base_data = int_prop + 32;
+
+ for (i = 0; i < ab->msi.msi_config->total_vectors; i++) {
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
+ if (!res)
+ return -ENODEV;
+
+ ab->msi.irqs[i] = res->start;
+ }
+
+ set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
+
+ return 0;
+}
+
+static int ath11k_ahb_setup_resources(struct ath11k_base *ab)
+{
+ struct platform_device *pdev = ab->pdev;
+ struct resource *mem_res;
+ void __iomem *mem;
+
+ if (ab->bus_params.hybrid_bus_type)
+ return ath11k_ahb_setup_msi_resources(ab);
+
+ mem = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res);
+ if (IS_ERR(mem)) {
+ dev_err(&pdev->dev, "ioremap error\n");
+ return PTR_ERR(mem);
+ }
+
+ ab->mem = mem;
+ ab->mem_len = resource_size(mem_res);
+
+ return 0;
+}
+
static int ath11k_ahb_probe(struct platform_device *pdev)
{
struct ath11k_base *ab;
const struct of_device_id *of_id;
- struct resource *mem_res;
- void __iomem *mem;
+ const struct ath11k_bus_params *bus_params;
+ const struct ath11k_hif_ops *hif_ops;
+ enum ath11k_hw_rev hw_rev;
int ret;
of_id = of_match_device(ath11k_ahb_of_match, &pdev->dev);
@@ -682,10 +787,21 @@ static int ath11k_ahb_probe(struct platform_device *pdev)
return -EINVAL;
}
- mem = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res);
- if (IS_ERR(mem)) {
- dev_err(&pdev->dev, "ioremap error\n");
- return PTR_ERR(mem);
+ hw_rev = (enum ath11k_hw_rev)of_id->data;
+
+ switch (hw_rev) {
+ case ATH11K_HW_IPQ8074:
+ case ATH11K_HW_IPQ6018_HW10:
+ bus_params = &bus_params_ipq8074;
+ hif_ops = &hif_ops_ipq8074;
+ break;
+ case ATH11K_HW_WCN6750_HW10:
+ bus_params = &bus_params_wcn6750;
+ hif_ops = &hif_ops_wcn6750;
+ break;
+ default:
+ dev_err(&pdev->dev, "unsupported device type %d\n", hw_rev);
+ return -EOPNOTSUPP;
}
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
@@ -695,20 +811,21 @@ static int ath11k_ahb_probe(struct platform_device *pdev)
}
ab = ath11k_core_alloc(&pdev->dev, sizeof(struct ath11k_ahb),
- ATH11K_BUS_AHB,
- &ath11k_ahb_bus_params);
+ ATH11K_BUS_AHB, bus_params);
if (!ab) {
dev_err(&pdev->dev, "failed to allocate ath11k base\n");
return -ENOMEM;
}
- ab->hif.ops = &ath11k_ahb_hif_ops;
+ ab->hif.ops = hif_ops;
ab->pdev = pdev;
- ab->hw_rev = (enum ath11k_hw_rev)of_id->data;
- ab->mem = mem;
- ab->mem_len = resource_size(mem_res);
+ ab->hw_rev = hw_rev;
platform_set_drvdata(pdev, ab);
+ ret = ath11k_ahb_setup_resources(ab);
+ if (ret)
+ goto err_core_free;
+
ret = ath11k_core_pre_init(ab);
if (ret)
goto err_core_free;
diff --git a/drivers/net/wireless/ath/ath11k/ahb.h b/drivers/net/wireless/ath/ath11k/ahb.h
index a97f2dd..1ae038e 100644
--- a/drivers/net/wireless/ath/ath11k/ahb.h
+++ b/drivers/net/wireless/ath/ath11k/ahb.h
@@ -10,7 +10,6 @@
#define ATH11K_AHB_RECOVERY_TIMEOUT (3 * HZ)
struct ath11k_base;
-extern const struct ath11k_bus_params ath11k_hybrid_bus_params;
struct ath11k_ahb {
struct rproc *tgt_rproc;
diff --git a/drivers/net/wireless/ath/ath11k/core.h b/drivers/net/wireless/ath/ath11k/core.h
index 92c1ea1..76f5aef 100644
--- a/drivers/net/wireless/ath/ath11k/core.h
+++ b/drivers/net/wireless/ath/ath11k/core.h
@@ -835,6 +835,7 @@ struct ath11k_base {
struct {
const struct ath11k_msi_config *msi_config;
u32 msi_ep_base_data;
+ u32 irqs[32];
u32 msi_addr_lo;
u32 msi_addr_hi;
} msi;
diff --git a/drivers/net/wireless/ath/ath11k/pci_cmn.c b/drivers/net/wireless/ath/ath11k/pci_cmn.c
index fede1d06d..047fcd7 100644
--- a/drivers/net/wireless/ath/ath11k/pci_cmn.c
+++ b/drivers/net/wireless/ath/ath11k/pci_cmn.c
@@ -95,6 +95,15 @@ static const struct ath11k_msi_config ath11k_msi_config[] = {
},
.hw_rev = ATH11K_HW_WCN6855_HW20,
},
+ {
+ .total_vectors = 28,
+ .total_users = 2,
+ .users = (struct ath11k_msi_user[]) {
+ { .name = "CE", .num_vectors = 10, .base_vector = 0 },
+ { .name = "DP", .num_vectors = 18, .base_vector = 10 },
+ },
+ .hw_rev = ATH11K_HW_WCN6750_HW10,
+ },
};
int ath11k_pci_get_msi_config(struct ath11k_base *ab)
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 18/19] ath11k: Add support for targets without trustzone
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
` (16 preceding siblings ...)
2022-01-16 12:47 ` [PATCH v2 17/19] ath11k: Add support for WCN6750 device Manikanta Pubbisetty
@ 2022-01-16 12:47 ` Manikanta Pubbisetty
2022-01-28 10:42 ` Kalle Valo
2022-01-16 12:47 ` [PATCH v2 19/19] dt: bindings: net: add bindings of WCN6750 for ath11k Manikanta Pubbisetty
2022-01-28 10:07 ` [PATCH v2 00/19] add support for WCN6750 Kalle Valo
19 siblings, 1 reply; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:47 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
Add the support to attach WCN6750 and map iommu domain
for targets which do not have the support of TrustZone.
Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
drivers/net/wireless/ath/ath11k/ahb.c | 174 +++++++++++++++++++++++++++++++++-
drivers/net/wireless/ath/ath11k/ahb.h | 9 ++
2 files changed, 181 insertions(+), 2 deletions(-)
diff --git a/drivers/net/wireless/ath/ath11k/ahb.c b/drivers/net/wireless/ath/ath11k/ahb.c
index 219592d..7cb13a0 100644
--- a/drivers/net/wireless/ath/ath11k/ahb.c
+++ b/drivers/net/wireless/ath/ath11k/ahb.c
@@ -9,6 +9,8 @@
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/dma-mapping.h>
+#include <linux/of_address.h>
+#include <linux/iommu.h>
#include "ahb.h"
#include "debug.h"
#include "hif.h"
@@ -772,6 +774,166 @@ static int ath11k_ahb_setup_resources(struct ath11k_base *ab)
return 0;
}
+static int ath11k_ahb_setup_msa_resources(struct ath11k_base *ab)
+{
+ struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
+ struct device *dev = ab->dev;
+ struct device_node *node;
+ struct resource r;
+ int ret;
+
+ node = of_parse_phandle(dev->of_node, "memory-region", 0);
+ if (!node)
+ return -ENOENT;
+
+ ret = of_address_to_resource(node, 0, &r);
+ of_node_put(node);
+ if (ret) {
+ dev_err(dev, "failed to resolve msa fixed region\n");
+ return ret;
+ }
+
+ ab_ahb->fw.msa_paddr = r.start;
+ ab_ahb->fw.msa_size = resource_size(&r);
+
+ node = of_parse_phandle(dev->of_node, "memory-region", 1);
+ if (!node)
+ return -ENOENT;
+
+ ret = of_address_to_resource(node, 0, &r);
+ of_node_put(node);
+ if (ret) {
+ dev_err(dev, "failed to resolve ce fixed region\n");
+ return ret;
+ }
+
+ ab_ahb->fw.ce_paddr = r.start;
+ ab_ahb->fw.ce_size = resource_size(&r);
+
+ return 0;
+}
+
+static int ath11k_ahb_fw_resources_init(struct ath11k_base *ab)
+{
+ struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
+ struct device *host_dev = ab->dev;
+ struct platform_device_info info = {0};
+ struct iommu_domain *iommu_dom;
+ struct platform_device *pdev;
+ struct device_node *node;
+ int ret;
+
+ node = of_get_child_by_name(host_dev->of_node, "wifi-firmware");
+ if (!node) {
+ ab_ahb->fw.use_tz = true;
+ return 0;
+ }
+
+ ret = ath11k_ahb_setup_msa_resources(ab);
+ if (ret) {
+ ath11k_err(ab, "failed to setup msa resources\n");
+ return ret;
+ }
+
+ info.fwnode = &node->fwnode;
+ info.parent = host_dev;
+ info.name = node->name;
+ info.dma_mask = DMA_BIT_MASK(32);
+
+ pdev = platform_device_register_full(&info);
+ if (IS_ERR(pdev)) {
+ of_node_put(node);
+ return PTR_ERR(pdev);
+ }
+
+ ret = of_dma_configure(&pdev->dev, node, true);
+ if (ret) {
+ ath11k_err(ab, "dma configure fail: %d\n", ret);
+ goto err_unregister;
+ }
+
+ ab_ahb->fw.dev = &pdev->dev;
+
+ iommu_dom = iommu_domain_alloc(&platform_bus_type);
+ if (!iommu_dom) {
+ ath11k_err(ab, "failed to allocate iommu domain\n");
+ ret = -ENOMEM;
+ goto err_unregister;
+ }
+
+ ret = iommu_attach_device(iommu_dom, ab_ahb->fw.dev);
+ if (ret) {
+ ath11k_err(ab, "could not attach device: %d\n", ret);
+ goto err_iommu_free;
+ }
+
+ ret = iommu_map(iommu_dom, ab_ahb->fw.msa_paddr,
+ ab_ahb->fw.msa_paddr, ab_ahb->fw.msa_size,
+ IOMMU_READ | IOMMU_WRITE);
+ if (ret) {
+ ath11k_err(ab, "failed to map firmware region: %d\n", ret);
+ goto err_iommu_detach;
+ }
+
+ ret = iommu_map(iommu_dom, ab_ahb->fw.ce_paddr,
+ ab_ahb->fw.ce_paddr, ab_ahb->fw.ce_size,
+ IOMMU_READ | IOMMU_WRITE);
+ if (ret) {
+ ath11k_err(ab, "failed to map firmware CE region: %d\n", ret);
+ goto err_iommu_unmap;
+ }
+
+ ab_ahb->fw.use_tz = false;
+ ab_ahb->fw.iommu_domain = iommu_dom;
+ of_node_put(node);
+
+ return 0;
+
+err_iommu_unmap:
+ iommu_unmap(iommu_dom, ab_ahb->fw.msa_paddr, ab_ahb->fw.msa_size);
+
+err_iommu_detach:
+ iommu_detach_device(iommu_dom, ab_ahb->fw.dev);
+
+err_iommu_free:
+ iommu_domain_free(iommu_dom);
+
+err_unregister:
+ platform_device_unregister(pdev);
+ of_node_put(node);
+
+ return ret;
+}
+
+static int ath11k_ahb_fw_resource_deinit(struct ath11k_base *ab)
+{
+ struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
+ struct iommu_domain *iommu;
+ size_t unmapped_size;
+
+ if (ab_ahb->fw.use_tz)
+ return 0;
+
+ iommu = ab_ahb->fw.iommu_domain;
+
+ unmapped_size = iommu_unmap(iommu, ab_ahb->fw.msa_paddr, ab_ahb->fw.msa_size);
+ if (unmapped_size != ab_ahb->fw.msa_size)
+ ath11k_err(ab, "failed to unmap firmware: %zu\n",
+ unmapped_size);
+
+ unmapped_size = iommu_unmap(iommu, ab_ahb->fw.ce_paddr, ab_ahb->fw.ce_size);
+ if (unmapped_size != ab_ahb->fw.ce_size)
+ ath11k_err(ab, "failed to unmap firmware CE memory: %zu\n",
+ unmapped_size);
+
+ iommu_detach_device(iommu, ab_ahb->fw.dev);
+ iommu_domain_free(iommu);
+
+ platform_device_unregister(to_platform_device(ab_ahb->fw.dev));
+
+ return 0;
+}
+
static int ath11k_ahb_probe(struct platform_device *pdev)
{
struct ath11k_base *ab;
@@ -826,13 +988,17 @@ static int ath11k_ahb_probe(struct platform_device *pdev)
if (ret)
goto err_core_free;
- ret = ath11k_core_pre_init(ab);
+ ret = ath11k_ahb_fw_resources_init(ab);
if (ret)
goto err_core_free;
+ ret = ath11k_core_pre_init(ab);
+ if (ret)
+ goto err_fw_deinit;
+
ret = ath11k_hal_srng_init(ab);
if (ret)
- goto err_core_free;
+ goto err_fw_deinit;
ret = ath11k_ce_alloc_pipes(ab);
if (ret) {
@@ -870,6 +1036,9 @@ static int ath11k_ahb_probe(struct platform_device *pdev)
err_hal_srng_deinit:
ath11k_hal_srng_deinit(ab);
+err_fw_deinit:
+ ath11k_ahb_fw_resource_deinit(ab);
+
err_core_free:
ath11k_core_free(ab);
platform_set_drvdata(pdev, NULL);
@@ -905,6 +1074,7 @@ static int ath11k_ahb_remove(struct platform_device *pdev)
qmi_fail:
ath11k_ahb_free_irq(ab);
ath11k_hal_srng_deinit(ab);
+ ath11k_ahb_fw_resource_deinit(ab);
ath11k_ce_free_pipes(ab);
ath11k_core_free(ab);
platform_set_drvdata(pdev, NULL);
diff --git a/drivers/net/wireless/ath/ath11k/ahb.h b/drivers/net/wireless/ath/ath11k/ahb.h
index 1ae038e..4c7872d 100644
--- a/drivers/net/wireless/ath/ath11k/ahb.h
+++ b/drivers/net/wireless/ath/ath11k/ahb.h
@@ -13,6 +13,15 @@ struct ath11k_base;
struct ath11k_ahb {
struct rproc *tgt_rproc;
+ struct {
+ struct device *dev;
+ struct iommu_domain *iommu_domain;
+ dma_addr_t msa_paddr;
+ u32 msa_size;
+ dma_addr_t ce_paddr;
+ u32 ce_size;
+ bool use_tz;
+ } fw;
};
static inline struct ath11k_ahb *ath11k_ahb_priv(struct ath11k_base *ab)
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCH v2 18/19] ath11k: Add support for targets without trustzone
2022-01-16 12:47 ` [PATCH v2 18/19] ath11k: Add support for targets without trustzone Manikanta Pubbisetty
@ 2022-01-28 10:42 ` Kalle Valo
2022-02-21 8:00 ` Manikanta Pubbisetty
0 siblings, 1 reply; 49+ messages in thread
From: Kalle Valo @ 2022-01-28 10:42 UTC (permalink / raw)
To: Manikanta Pubbisetty; +Cc: ath11k, linux-wireless, devicetree, robh
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
> Add the support to attach WCN6750 and map iommu domain
> for targets which do not have the support of TrustZone.
>
> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>
> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
Is this not needed in the initial WCN6750 support? If yes, please submit
this patch after WCN6750 support has been commited. That way we can
reduce patchset size.
--
https://patchwork.kernel.org/project/linux-wireless/list/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 18/19] ath11k: Add support for targets without trustzone
2022-01-28 10:42 ` Kalle Valo
@ 2022-02-21 8:00 ` Manikanta Pubbisetty
0 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-02-21 8:00 UTC (permalink / raw)
To: Kalle Valo; +Cc: ath11k, linux-wireless, devicetree, robh
On 1/28/2022 4:12 PM, Kalle Valo wrote:
> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>
>> Add the support to attach WCN6750 and map iommu domain
>> for targets which do not have the support of TrustZone.
>>
>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>
>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>
> Is this not needed in the initial WCN6750 support? If yes, please submit
> this patch after WCN6750 support has been commited. That way we can
> reduce patchset size.
>
Sure, we can do that.
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 19/19] dt: bindings: net: add bindings of WCN6750 for ath11k
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
` (17 preceding siblings ...)
2022-01-16 12:47 ` [PATCH v2 18/19] ath11k: Add support for targets without trustzone Manikanta Pubbisetty
@ 2022-01-16 12:47 ` Manikanta Pubbisetty
2022-01-28 10:39 ` Kalle Valo
2022-02-07 22:13 ` Rob Herring
2022-01-28 10:07 ` [PATCH v2 00/19] add support for WCN6750 Kalle Valo
19 siblings, 2 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-01-16 12:47 UTC (permalink / raw)
To: ath11k; +Cc: linux-wireless, devicetree, robh, Manikanta Pubbisetty
Add WCN6750 wireless driver support, its based on ath11k driver.
Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
.../bindings/net/wireless/qcom,ath11k.yaml | 365 +++++++++++++++------
1 file changed, 257 insertions(+), 108 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
index cdf7b87..dba1434 100644
--- a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
+++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
@@ -20,120 +20,21 @@ properties:
enum:
- qcom,ipq8074-wifi
- qcom,ipq6018-wifi
+ - qcom,wcn6750-wifi
reg:
maxItems: 1
- interrupts:
- items:
- - description: misc-pulse1 interrupt events
- - description: misc-latch interrupt events
- - description: sw exception interrupt events
- - description: watchdog interrupt events
- - description: interrupt event for ring CE0
- - description: interrupt event for ring CE1
- - description: interrupt event for ring CE2
- - description: interrupt event for ring CE3
- - description: interrupt event for ring CE4
- - description: interrupt event for ring CE5
- - description: interrupt event for ring CE6
- - description: interrupt event for ring CE7
- - description: interrupt event for ring CE8
- - description: interrupt event for ring CE9
- - description: interrupt event for ring CE10
- - description: interrupt event for ring CE11
- - description: interrupt event for ring host2wbm-desc-feed
- - description: interrupt event for ring host2reo-re-injection
- - description: interrupt event for ring host2reo-command
- - description: interrupt event for ring host2rxdma-monitor-ring3
- - description: interrupt event for ring host2rxdma-monitor-ring2
- - description: interrupt event for ring host2rxdma-monitor-ring1
- - description: interrupt event for ring reo2ost-exception
- - description: interrupt event for ring wbm2host-rx-release
- - description: interrupt event for ring reo2host-status
- - description: interrupt event for ring reo2host-destination-ring4
- - description: interrupt event for ring reo2host-destination-ring3
- - description: interrupt event for ring reo2host-destination-ring2
- - description: interrupt event for ring reo2host-destination-ring1
- - description: interrupt event for ring rxdma2host-monitor-destination-mac3
- - description: interrupt event for ring rxdma2host-monitor-destination-mac2
- - description: interrupt event for ring rxdma2host-monitor-destination-mac1
- - description: interrupt event for ring ppdu-end-interrupts-mac3
- - description: interrupt event for ring ppdu-end-interrupts-mac2
- - description: interrupt event for ring ppdu-end-interrupts-mac1
- - description: interrupt event for ring rxdma2host-monitor-status-ring-mac3
- - description: interrupt event for ring rxdma2host-monitor-status-ring-mac2
- - description: interrupt event for ring rxdma2host-monitor-status-ring-mac1
- - description: interrupt event for ring host2rxdma-host-buf-ring-mac3
- - description: interrupt event for ring host2rxdma-host-buf-ring-mac2
- - description: interrupt event for ring host2rxdma-host-buf-ring-mac1
- - description: interrupt event for ring rxdma2host-destination-ring-mac3
- - description: interrupt event for ring rxdma2host-destination-ring-mac2
- - description: interrupt event for ring rxdma2host-destination-ring-mac1
- - description: interrupt event for ring host2tcl-input-ring4
- - description: interrupt event for ring host2tcl-input-ring3
- - description: interrupt event for ring host2tcl-input-ring2
- - description: interrupt event for ring host2tcl-input-ring1
- - description: interrupt event for ring wbm2host-tx-completions-ring3
- - description: interrupt event for ring wbm2host-tx-completions-ring2
- - description: interrupt event for ring wbm2host-tx-completions-ring1
- - description: interrupt event for ring tcl2host-status-ring
+ reg-names:
+ maxItems: 1
+ interrupts:
+ minItems: 32
+ maxItems: 52
interrupt-names:
- items:
- - const: misc-pulse1
- - const: misc-latch
- - const: sw-exception
- - const: watchdog
- - const: ce0
- - const: ce1
- - const: ce2
- - const: ce3
- - const: ce4
- - const: ce5
- - const: ce6
- - const: ce7
- - const: ce8
- - const: ce9
- - const: ce10
- - const: ce11
- - const: host2wbm-desc-feed
- - const: host2reo-re-injection
- - const: host2reo-command
- - const: host2rxdma-monitor-ring3
- - const: host2rxdma-monitor-ring2
- - const: host2rxdma-monitor-ring1
- - const: reo2ost-exception
- - const: wbm2host-rx-release
- - const: reo2host-status
- - const: reo2host-destination-ring4
- - const: reo2host-destination-ring3
- - const: reo2host-destination-ring2
- - const: reo2host-destination-ring1
- - const: rxdma2host-monitor-destination-mac3
- - const: rxdma2host-monitor-destination-mac2
- - const: rxdma2host-monitor-destination-mac1
- - const: ppdu-end-interrupts-mac3
- - const: ppdu-end-interrupts-mac2
- - const: ppdu-end-interrupts-mac1
- - const: rxdma2host-monitor-status-ring-mac3
- - const: rxdma2host-monitor-status-ring-mac2
- - const: rxdma2host-monitor-status-ring-mac1
- - const: host2rxdma-host-buf-ring-mac3
- - const: host2rxdma-host-buf-ring-mac2
- - const: host2rxdma-host-buf-ring-mac1
- - const: rxdma2host-destination-ring-mac3
- - const: rxdma2host-destination-ring-mac2
- - const: rxdma2host-destination-ring-mac1
- - const: host2tcl-input-ring4
- - const: host2tcl-input-ring3
- - const: host2tcl-input-ring2
- - const: host2tcl-input-ring1
- - const: wbm2host-tx-completions-ring3
- - const: wbm2host-tx-completions-ring2
- - const: wbm2host-tx-completions-ring1
- - const: tcl2host-status-ring
+ minItems: 32
+ maxItems: 52
qcom,rproc:
$ref: /schemas/types.yaml#/definitions/phandle
@@ -156,15 +57,201 @@ properties:
phandle to a node describing reserved memory (System RAM memory)
used by ath11k firmware (see bindings/reserved-memory/reserved-memory.txt)
+ iommus:
+ maxItems: 1
+
+ wifi-firmware:
+ type: object
+ description: |
+ WCN6750 wifi node can contain one optional firmware subnode.
+ Firmware subnode is needed when the platform does not have TustZone.
+ properties:
+ iommus:
+ maxItems: 1
+ required:
+ - iommus
+
required:
- compatible
- reg
- interrupts
- - interrupt-names
- qcom,rproc
additionalProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq8074-wifi
+ - qcom,ipq6018-wifi
+ then:
+ properties:
+ interrupts:
+ items:
+ - description: misc-pulse1 interrupt events
+ - description: misc-latch interrupt events
+ - description: sw exception interrupt events
+ - description: watchdog interrupt events
+ - description: interrupt event for ring CE0
+ - description: interrupt event for ring CE1
+ - description: interrupt event for ring CE2
+ - description: interrupt event for ring CE3
+ - description: interrupt event for ring CE4
+ - description: interrupt event for ring CE5
+ - description: interrupt event for ring CE6
+ - description: interrupt event for ring CE7
+ - description: interrupt event for ring CE8
+ - description: interrupt event for ring CE9
+ - description: interrupt event for ring CE10
+ - description: interrupt event for ring CE11
+ - description: interrupt event for ring host2wbm-desc-feed
+ - description: interrupt event for ring host2reo-re-injection
+ - description: interrupt event for ring host2reo-command
+ - description: interrupt event for ring host2rxdma-monitor-ring3
+ - description: interrupt event for ring host2rxdma-monitor-ring2
+ - description: interrupt event for ring host2rxdma-monitor-ring1
+ - description: interrupt event for ring reo2ost-exception
+ - description: interrupt event for ring wbm2host-rx-release
+ - description: interrupt event for ring reo2host-status
+ - description: interrupt event for ring reo2host-destination-ring4
+ - description: interrupt event for ring reo2host-destination-ring3
+ - description: interrupt event for ring reo2host-destination-ring2
+ - description: interrupt event for ring reo2host-destination-ring1
+ - description: interrupt event for ring rxdma2host-monitor-destination-mac3
+ - description: interrupt event for ring rxdma2host-monitor-destination-mac2
+ - description: interrupt event for ring rxdma2host-monitor-destination-mac1
+ - description: interrupt event for ring ppdu-end-interrupts-mac3
+ - description: interrupt event for ring ppdu-end-interrupts-mac2
+ - description: interrupt event for ring ppdu-end-interrupts-mac1
+ - description: interrupt event for ring rxdma2host-monitor-status-ring-mac3
+ - description: interrupt event for ring rxdma2host-monitor-status-ring-mac2
+ - description: interrupt event for ring rxdma2host-monitor-status-ring-mac1
+ - description: interrupt event for ring host2rxdma-host-buf-ring-mac3
+ - description: interrupt event for ring host2rxdma-host-buf-ring-mac2
+ - description: interrupt event for ring host2rxdma-host-buf-ring-mac1
+ - description: interrupt event for ring rxdma2host-destination-ring-mac3
+ - description: interrupt event for ring rxdma2host-destination-ring-mac2
+ - description: interrupt event for ring rxdma2host-destination-ring-mac1
+ - description: interrupt event for ring host2tcl-input-ring4
+ - description: interrupt event for ring host2tcl-input-ring3
+ - description: interrupt event for ring host2tcl-input-ring2
+ - description: interrupt event for ring host2tcl-input-ring1
+ - description: interrupt event for ring wbm2host-tx-completions-ring3
+ - description: interrupt event for ring wbm2host-tx-completions-ring2
+ - description: interrupt event for ring wbm2host-tx-completions-ring1
+ - description: interrupt event for ring tcl2host-status-ring
+ interrupt-names:
+ items:
+ - const: misc-pulse1
+ - const: misc-latch
+ - const: sw-exception
+ - const: watchdog
+ - const: ce0
+ - const: ce1
+ - const: ce2
+ - const: ce3
+ - const: ce4
+ - const: ce5
+ - const: ce6
+ - const: ce7
+ - const: ce8
+ - const: ce9
+ - const: ce10
+ - const: ce11
+ - const: host2wbm-desc-feed
+ - const: host2reo-re-injection
+ - const: host2reo-command
+ - const: host2rxdma-monitor-ring3
+ - const: host2rxdma-monitor-ring2
+ - const: host2rxdma-monitor-ring1
+ - const: reo2ost-exception
+ - const: wbm2host-rx-release
+ - const: reo2host-status
+ - const: reo2host-destination-ring4
+ - const: reo2host-destination-ring3
+ - const: reo2host-destination-ring2
+ - const: reo2host-destination-ring1
+ - const: rxdma2host-monitor-destination-mac3
+ - const: rxdma2host-monitor-destination-mac2
+ - const: rxdma2host-monitor-destination-mac1
+ - const: ppdu-end-interrupts-mac3
+ - const: ppdu-end-interrupts-mac2
+ - const: ppdu-end-interrupts-mac1
+ - const: rxdma2host-monitor-status-ring-mac3
+ - const: rxdma2host-monitor-status-ring-mac2
+ - const: rxdma2host-monitor-status-ring-mac1
+ - const: host2rxdma-host-buf-ring-mac3
+ - const: host2rxdma-host-buf-ring-mac2
+ - const: host2rxdma-host-buf-ring-mac1
+ - const: rxdma2host-destination-ring-mac3
+ - const: rxdma2host-destination-ring-mac2
+ - const: rxdma2host-destination-ring-mac1
+ - const: host2tcl-input-ring4
+ - const: host2tcl-input-ring3
+ - const: host2tcl-input-ring2
+ - const: host2tcl-input-ring1
+ - const: wbm2host-tx-completions-ring3
+ - const: wbm2host-tx-completions-ring2
+ - const: wbm2host-tx-completions-ring1
+ - const: tcl2host-status-ring
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq8074-wifi
+ - qcom,ipq6018-wifi
+ then:
+ required:
+ - interrupt-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,wcn6750-wifi
+ then:
+ properties:
+ interrupts:
+ items:
+ - description: interrupt event for ring CE1
+ - description: interrupt event for ring CE2
+ - description: interrupt event for ring CE3
+ - description: interrupt event for ring CE4
+ - description: interrupt event for ring CE5
+ - description: interrupt event for ring CE6
+ - description: interrupt event for ring CE7
+ - description: interrupt event for ring CE8
+ - description: interrupt event for ring CE9
+ - description: interrupt event for ring CE10
+ - description: interrupt event for ring DP1
+ - description: interrupt event for ring DP2
+ - description: interrupt event for ring DP3
+ - description: interrupt event for ring DP4
+ - description: interrupt event for ring DP5
+ - description: interrupt event for ring DP6
+ - description: interrupt event for ring DP7
+ - description: interrupt event for ring DP8
+ - description: interrupt event for ring DP9
+ - description: interrupt event for ring DP10
+ - description: interrupt event for ring DP11
+ - description: interrupt event for ring DP12
+ - description: interrupt event for ring DP13
+ - description: interrupt event for ring DP14
+ - description: interrupt event for ring DP15
+ - description: interrupt event for ring DP16
+ - description: interrupt event for ring DP17
+ - description: interrupt event for ring DP18
+ - description: interrupt event for ring DP19
+ - description: interrupt event for ring DP20
+ - description: interrupt event for ring DP21
+ - description: interrupt event for ring DP22
+
examples:
- |
@@ -309,3 +396,65 @@ examples:
};
};
};
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ wlan_ce_mem: wlan_ce_mem@4cd000 {
+ no-map;
+ reg = <0x0 0x4cd000 0x0 0x1000>;
+ };
+
+ wlan_fw_mem: wlan_fw_mem@80c00000 {
+ no-map;
+ reg = <0x0 0x80c00000 0x0 0xc00000>;
+ };
+ };
+
+ wifi: wifi@17a10040 {
+ compatible = "qcom,wcn6750-wifi";
+ reg = <0x17A10040 0x0>;
+ reg-names = "msi_addr";
+ iommus = <&apps_smmu 0x1C00 0x1>;
+ interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
+ qcom,rproc = <&remoteproc_wpss>;
+ memory-region = <&wlan_fw_mem &wlan_ce_mem>;
+ wifi-firmware {
+ iommus = <&apps_smmu 0x1C02 0x1>;
+ };
+ };
--
2.7.4
^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCH v2 19/19] dt: bindings: net: add bindings of WCN6750 for ath11k
2022-01-16 12:47 ` [PATCH v2 19/19] dt: bindings: net: add bindings of WCN6750 for ath11k Manikanta Pubbisetty
@ 2022-01-28 10:39 ` Kalle Valo
2022-02-21 7:08 ` Manikanta Pubbisetty
2022-02-07 22:13 ` Rob Herring
1 sibling, 1 reply; 49+ messages in thread
From: Kalle Valo @ 2022-01-28 10:39 UTC (permalink / raw)
To: Manikanta Pubbisetty; +Cc: ath11k, linux-wireless, devicetree, robh
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
> Add WCN6750 wireless driver support, its based on ath11k driver.
>
> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
Device tree bindings should be first in the patchset.
I'm no DT expert, but you have a lot of changes in the bindings and it
would be nice to have some kind of description what you are doing here.
--
https://patchwork.kernel.org/project/linux-wireless/list/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 19/19] dt: bindings: net: add bindings of WCN6750 for ath11k
2022-01-28 10:39 ` Kalle Valo
@ 2022-02-21 7:08 ` Manikanta Pubbisetty
0 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-02-21 7:08 UTC (permalink / raw)
To: Kalle Valo; +Cc: ath11k, linux-wireless, devicetree, robh
On 1/28/2022 4:09 PM, Kalle Valo wrote:
> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>
>> Add WCN6750 wireless driver support, its based on ath11k driver.
>>
>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>
> Device tree bindings should be first in the patchset.
>
> I'm no DT expert, but you have a lot of changes in the bindings and it
> would be nice to have some kind of description what you are doing here.
>
Sure.
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 19/19] dt: bindings: net: add bindings of WCN6750 for ath11k
2022-01-16 12:47 ` [PATCH v2 19/19] dt: bindings: net: add bindings of WCN6750 for ath11k Manikanta Pubbisetty
2022-01-28 10:39 ` Kalle Valo
@ 2022-02-07 22:13 ` Rob Herring
2022-02-25 11:34 ` Manikanta Pubbisetty
1 sibling, 1 reply; 49+ messages in thread
From: Rob Herring @ 2022-02-07 22:13 UTC (permalink / raw)
To: Manikanta Pubbisetty; +Cc: ath11k, linux-wireless, devicetree
On Sun, Jan 16, 2022 at 06:17:15PM +0530, Manikanta Pubbisetty wrote:
> Add WCN6750 wireless driver support, its based on ath11k driver.
As mentioned, provide a better commit message answering 'why'?
>
> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
> ---
> .../bindings/net/wireless/qcom,ath11k.yaml | 365 +++++++++++++++------
> 1 file changed, 257 insertions(+), 108 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
> index cdf7b87..dba1434 100644
> --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
> +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
> @@ -20,120 +20,21 @@ properties:
> enum:
> - qcom,ipq8074-wifi
> - qcom,ipq6018-wifi
> + - qcom,wcn6750-wifi
>
> reg:
> maxItems: 1
>
> - interrupts:
> - items:
> - - description: misc-pulse1 interrupt events
> - - description: misc-latch interrupt events
> - - description: sw exception interrupt events
> - - description: watchdog interrupt events
> - - description: interrupt event for ring CE0
> - - description: interrupt event for ring CE1
> - - description: interrupt event for ring CE2
> - - description: interrupt event for ring CE3
> - - description: interrupt event for ring CE4
> - - description: interrupt event for ring CE5
> - - description: interrupt event for ring CE6
> - - description: interrupt event for ring CE7
> - - description: interrupt event for ring CE8
> - - description: interrupt event for ring CE9
> - - description: interrupt event for ring CE10
> - - description: interrupt event for ring CE11
> - - description: interrupt event for ring host2wbm-desc-feed
> - - description: interrupt event for ring host2reo-re-injection
> - - description: interrupt event for ring host2reo-command
> - - description: interrupt event for ring host2rxdma-monitor-ring3
> - - description: interrupt event for ring host2rxdma-monitor-ring2
> - - description: interrupt event for ring host2rxdma-monitor-ring1
> - - description: interrupt event for ring reo2ost-exception
> - - description: interrupt event for ring wbm2host-rx-release
> - - description: interrupt event for ring reo2host-status
> - - description: interrupt event for ring reo2host-destination-ring4
> - - description: interrupt event for ring reo2host-destination-ring3
> - - description: interrupt event for ring reo2host-destination-ring2
> - - description: interrupt event for ring reo2host-destination-ring1
> - - description: interrupt event for ring rxdma2host-monitor-destination-mac3
> - - description: interrupt event for ring rxdma2host-monitor-destination-mac2
> - - description: interrupt event for ring rxdma2host-monitor-destination-mac1
> - - description: interrupt event for ring ppdu-end-interrupts-mac3
> - - description: interrupt event for ring ppdu-end-interrupts-mac2
> - - description: interrupt event for ring ppdu-end-interrupts-mac1
> - - description: interrupt event for ring rxdma2host-monitor-status-ring-mac3
> - - description: interrupt event for ring rxdma2host-monitor-status-ring-mac2
> - - description: interrupt event for ring rxdma2host-monitor-status-ring-mac1
> - - description: interrupt event for ring host2rxdma-host-buf-ring-mac3
> - - description: interrupt event for ring host2rxdma-host-buf-ring-mac2
> - - description: interrupt event for ring host2rxdma-host-buf-ring-mac1
> - - description: interrupt event for ring rxdma2host-destination-ring-mac3
> - - description: interrupt event for ring rxdma2host-destination-ring-mac2
> - - description: interrupt event for ring rxdma2host-destination-ring-mac1
> - - description: interrupt event for ring host2tcl-input-ring4
> - - description: interrupt event for ring host2tcl-input-ring3
> - - description: interrupt event for ring host2tcl-input-ring2
> - - description: interrupt event for ring host2tcl-input-ring1
> - - description: interrupt event for ring wbm2host-tx-completions-ring3
> - - description: interrupt event for ring wbm2host-tx-completions-ring2
> - - description: interrupt event for ring wbm2host-tx-completions-ring1
> - - description: interrupt event for ring tcl2host-status-ring
> + reg-names:
> + maxItems: 1
Need to define the names though for 1 entry, -names is kind of
pointless.
>
> + interrupts:
> + minItems: 32
> + maxItems: 52
>
> interrupt-names:
> - items:
> - - const: misc-pulse1
> - - const: misc-latch
> - - const: sw-exception
> - - const: watchdog
> - - const: ce0
> - - const: ce1
> - - const: ce2
> - - const: ce3
> - - const: ce4
> - - const: ce5
> - - const: ce6
> - - const: ce7
> - - const: ce8
> - - const: ce9
> - - const: ce10
> - - const: ce11
> - - const: host2wbm-desc-feed
> - - const: host2reo-re-injection
> - - const: host2reo-command
> - - const: host2rxdma-monitor-ring3
> - - const: host2rxdma-monitor-ring2
> - - const: host2rxdma-monitor-ring1
> - - const: reo2ost-exception
> - - const: wbm2host-rx-release
> - - const: reo2host-status
> - - const: reo2host-destination-ring4
> - - const: reo2host-destination-ring3
> - - const: reo2host-destination-ring2
> - - const: reo2host-destination-ring1
> - - const: rxdma2host-monitor-destination-mac3
> - - const: rxdma2host-monitor-destination-mac2
> - - const: rxdma2host-monitor-destination-mac1
> - - const: ppdu-end-interrupts-mac3
> - - const: ppdu-end-interrupts-mac2
> - - const: ppdu-end-interrupts-mac1
> - - const: rxdma2host-monitor-status-ring-mac3
> - - const: rxdma2host-monitor-status-ring-mac2
> - - const: rxdma2host-monitor-status-ring-mac1
> - - const: host2rxdma-host-buf-ring-mac3
> - - const: host2rxdma-host-buf-ring-mac2
> - - const: host2rxdma-host-buf-ring-mac1
> - - const: rxdma2host-destination-ring-mac3
> - - const: rxdma2host-destination-ring-mac2
> - - const: rxdma2host-destination-ring-mac1
> - - const: host2tcl-input-ring4
> - - const: host2tcl-input-ring3
> - - const: host2tcl-input-ring2
> - - const: host2tcl-input-ring1
> - - const: wbm2host-tx-completions-ring3
> - - const: wbm2host-tx-completions-ring2
> - - const: wbm2host-tx-completions-ring1
> - - const: tcl2host-status-ring
> + minItems: 32
> + maxItems: 52
But you didn't define any names for the new chip.
>
> qcom,rproc:
> $ref: /schemas/types.yaml#/definitions/phandle
> @@ -156,15 +57,201 @@ properties:
> phandle to a node describing reserved memory (System RAM memory)
> used by ath11k firmware (see bindings/reserved-memory/reserved-memory.txt)
>
> + iommus:
> + maxItems: 1
> +
> + wifi-firmware:
> + type: object
> + description: |
> + WCN6750 wifi node can contain one optional firmware subnode.
> + Firmware subnode is needed when the platform does not have TustZone.
Trustzone
> + properties:
> + iommus:
> + maxItems: 1
If this is the only property, then just make parent 'iommus' 1 or 2
entries.
> + required:
> + - iommus
> +
> required:
> - compatible
> - reg
> - interrupts
> - - interrupt-names
> - qcom,rproc
>
> additionalProperties: false
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,ipq8074-wifi
> + - qcom,ipq6018-wifi
> + then:
> + properties:
> + interrupts:
> + items:
> + - description: misc-pulse1 interrupt events
> + - description: misc-latch interrupt events
> + - description: sw exception interrupt events
> + - description: watchdog interrupt events
> + - description: interrupt event for ring CE0
> + - description: interrupt event for ring CE1
> + - description: interrupt event for ring CE2
> + - description: interrupt event for ring CE3
> + - description: interrupt event for ring CE4
> + - description: interrupt event for ring CE5
> + - description: interrupt event for ring CE6
> + - description: interrupt event for ring CE7
> + - description: interrupt event for ring CE8
> + - description: interrupt event for ring CE9
> + - description: interrupt event for ring CE10
> + - description: interrupt event for ring CE11
> + - description: interrupt event for ring host2wbm-desc-feed
> + - description: interrupt event for ring host2reo-re-injection
> + - description: interrupt event for ring host2reo-command
> + - description: interrupt event for ring host2rxdma-monitor-ring3
> + - description: interrupt event for ring host2rxdma-monitor-ring2
> + - description: interrupt event for ring host2rxdma-monitor-ring1
> + - description: interrupt event for ring reo2ost-exception
> + - description: interrupt event for ring wbm2host-rx-release
> + - description: interrupt event for ring reo2host-status
> + - description: interrupt event for ring reo2host-destination-ring4
> + - description: interrupt event for ring reo2host-destination-ring3
> + - description: interrupt event for ring reo2host-destination-ring2
> + - description: interrupt event for ring reo2host-destination-ring1
> + - description: interrupt event for ring rxdma2host-monitor-destination-mac3
> + - description: interrupt event for ring rxdma2host-monitor-destination-mac2
> + - description: interrupt event for ring rxdma2host-monitor-destination-mac1
> + - description: interrupt event for ring ppdu-end-interrupts-mac3
> + - description: interrupt event for ring ppdu-end-interrupts-mac2
> + - description: interrupt event for ring ppdu-end-interrupts-mac1
> + - description: interrupt event for ring rxdma2host-monitor-status-ring-mac3
> + - description: interrupt event for ring rxdma2host-monitor-status-ring-mac2
> + - description: interrupt event for ring rxdma2host-monitor-status-ring-mac1
> + - description: interrupt event for ring host2rxdma-host-buf-ring-mac3
> + - description: interrupt event for ring host2rxdma-host-buf-ring-mac2
> + - description: interrupt event for ring host2rxdma-host-buf-ring-mac1
> + - description: interrupt event for ring rxdma2host-destination-ring-mac3
> + - description: interrupt event for ring rxdma2host-destination-ring-mac2
> + - description: interrupt event for ring rxdma2host-destination-ring-mac1
> + - description: interrupt event for ring host2tcl-input-ring4
> + - description: interrupt event for ring host2tcl-input-ring3
> + - description: interrupt event for ring host2tcl-input-ring2
> + - description: interrupt event for ring host2tcl-input-ring1
> + - description: interrupt event for ring wbm2host-tx-completions-ring3
> + - description: interrupt event for ring wbm2host-tx-completions-ring2
> + - description: interrupt event for ring wbm2host-tx-completions-ring1
> + - description: interrupt event for ring tcl2host-status-ring
> + interrupt-names:
> + items:
> + - const: misc-pulse1
> + - const: misc-latch
> + - const: sw-exception
> + - const: watchdog
> + - const: ce0
> + - const: ce1
> + - const: ce2
> + - const: ce3
> + - const: ce4
> + - const: ce5
> + - const: ce6
> + - const: ce7
> + - const: ce8
> + - const: ce9
> + - const: ce10
> + - const: ce11
> + - const: host2wbm-desc-feed
> + - const: host2reo-re-injection
> + - const: host2reo-command
> + - const: host2rxdma-monitor-ring3
> + - const: host2rxdma-monitor-ring2
> + - const: host2rxdma-monitor-ring1
> + - const: reo2ost-exception
> + - const: wbm2host-rx-release
> + - const: reo2host-status
> + - const: reo2host-destination-ring4
> + - const: reo2host-destination-ring3
> + - const: reo2host-destination-ring2
> + - const: reo2host-destination-ring1
> + - const: rxdma2host-monitor-destination-mac3
> + - const: rxdma2host-monitor-destination-mac2
> + - const: rxdma2host-monitor-destination-mac1
> + - const: ppdu-end-interrupts-mac3
> + - const: ppdu-end-interrupts-mac2
> + - const: ppdu-end-interrupts-mac1
> + - const: rxdma2host-monitor-status-ring-mac3
> + - const: rxdma2host-monitor-status-ring-mac2
> + - const: rxdma2host-monitor-status-ring-mac1
> + - const: host2rxdma-host-buf-ring-mac3
> + - const: host2rxdma-host-buf-ring-mac2
> + - const: host2rxdma-host-buf-ring-mac1
> + - const: rxdma2host-destination-ring-mac3
> + - const: rxdma2host-destination-ring-mac2
> + - const: rxdma2host-destination-ring-mac1
> + - const: host2tcl-input-ring4
> + - const: host2tcl-input-ring3
> + - const: host2tcl-input-ring2
> + - const: host2tcl-input-ring1
> + - const: wbm2host-tx-completions-ring3
> + - const: wbm2host-tx-completions-ring2
> + - const: wbm2host-tx-completions-ring1
> + - const: tcl2host-status-ring
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,ipq8074-wifi
> + - qcom,ipq6018-wifi
> + then:
> + required:
> + - interrupt-names
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,wcn6750-wifi
> + then:
> + properties:
> + interrupts:
> + items:
> + - description: interrupt event for ring CE1
> + - description: interrupt event for ring CE2
> + - description: interrupt event for ring CE3
> + - description: interrupt event for ring CE4
> + - description: interrupt event for ring CE5
> + - description: interrupt event for ring CE6
> + - description: interrupt event for ring CE7
> + - description: interrupt event for ring CE8
> + - description: interrupt event for ring CE9
> + - description: interrupt event for ring CE10
> + - description: interrupt event for ring DP1
> + - description: interrupt event for ring DP2
> + - description: interrupt event for ring DP3
> + - description: interrupt event for ring DP4
> + - description: interrupt event for ring DP5
> + - description: interrupt event for ring DP6
> + - description: interrupt event for ring DP7
> + - description: interrupt event for ring DP8
> + - description: interrupt event for ring DP9
> + - description: interrupt event for ring DP10
> + - description: interrupt event for ring DP11
> + - description: interrupt event for ring DP12
> + - description: interrupt event for ring DP13
> + - description: interrupt event for ring DP14
> + - description: interrupt event for ring DP15
> + - description: interrupt event for ring DP16
> + - description: interrupt event for ring DP17
> + - description: interrupt event for ring DP18
> + - description: interrupt event for ring DP19
> + - description: interrupt event for ring DP20
> + - description: interrupt event for ring DP21
> + - description: interrupt event for ring DP22
> +
> examples:
> - |
>
> @@ -309,3 +396,65 @@ examples:
> };
> };
> };
> +
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + wlan_ce_mem: wlan_ce_mem@4cd000 {
> + no-map;
> + reg = <0x0 0x4cd000 0x0 0x1000>;
> + };
> +
> + wlan_fw_mem: wlan_fw_mem@80c00000 {
> + no-map;
> + reg = <0x0 0x80c00000 0x0 0xc00000>;
> + };
> + };
> +
> + wifi: wifi@17a10040 {
> + compatible = "qcom,wcn6750-wifi";
> + reg = <0x17A10040 0x0>;
> + reg-names = "msi_addr";
> + iommus = <&apps_smmu 0x1C00 0x1>;
> + interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
> + qcom,rproc = <&remoteproc_wpss>;
> + memory-region = <&wlan_fw_mem &wlan_ce_mem>;
memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
> + wifi-firmware {
> + iommus = <&apps_smmu 0x1C02 0x1>;
> + };
> + };
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 19/19] dt: bindings: net: add bindings of WCN6750 for ath11k
2022-02-07 22:13 ` Rob Herring
@ 2022-02-25 11:34 ` Manikanta Pubbisetty
0 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-02-25 11:34 UTC (permalink / raw)
To: Rob Herring; +Cc: ath11k, linux-wireless, devicetree
On 2/8/2022 3:43 AM, Rob Herring wrote:
> On Sun, Jan 16, 2022 at 06:17:15PM +0530, Manikanta Pubbisetty wrote:
>> Add WCN6750 wireless driver support, its based on ath11k driver.
>
> As mentioned, provide a better commit message answering 'why'?
>
>>
>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>> ---
>> .../bindings/net/wireless/qcom,ath11k.yaml | 365 +++++++++++++++------
>> 1 file changed, 257 insertions(+), 108 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
>> index cdf7b87..dba1434 100644
>> --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
>> +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
>> @@ -20,120 +20,21 @@ properties:
>> enum:
>> - qcom,ipq8074-wifi
>> - qcom,ipq6018-wifi
>> + - qcom,wcn6750-wifi
>>
>> reg:
>> maxItems: 1
>>
>> - interrupts:
>> - items:
>> - - description: misc-pulse1 interrupt events
>> - - description: misc-latch interrupt events
>> - - description: sw exception interrupt events
>> - - description: watchdog interrupt events
>> - - description: interrupt event for ring CE0
>> - - description: interrupt event for ring CE1
>> - - description: interrupt event for ring CE2
>> - - description: interrupt event for ring CE3
>> - - description: interrupt event for ring CE4
>> - - description: interrupt event for ring CE5
>> - - description: interrupt event for ring CE6
>> - - description: interrupt event for ring CE7
>> - - description: interrupt event for ring CE8
>> - - description: interrupt event for ring CE9
>> - - description: interrupt event for ring CE10
>> - - description: interrupt event for ring CE11
>> - - description: interrupt event for ring host2wbm-desc-feed
>> - - description: interrupt event for ring host2reo-re-injection
>> - - description: interrupt event for ring host2reo-command
>> - - description: interrupt event for ring host2rxdma-monitor-ring3
>> - - description: interrupt event for ring host2rxdma-monitor-ring2
>> - - description: interrupt event for ring host2rxdma-monitor-ring1
>> - - description: interrupt event for ring reo2ost-exception
>> - - description: interrupt event for ring wbm2host-rx-release
>> - - description: interrupt event for ring reo2host-status
>> - - description: interrupt event for ring reo2host-destination-ring4
>> - - description: interrupt event for ring reo2host-destination-ring3
>> - - description: interrupt event for ring reo2host-destination-ring2
>> - - description: interrupt event for ring reo2host-destination-ring1
>> - - description: interrupt event for ring rxdma2host-monitor-destination-mac3
>> - - description: interrupt event for ring rxdma2host-monitor-destination-mac2
>> - - description: interrupt event for ring rxdma2host-monitor-destination-mac1
>> - - description: interrupt event for ring ppdu-end-interrupts-mac3
>> - - description: interrupt event for ring ppdu-end-interrupts-mac2
>> - - description: interrupt event for ring ppdu-end-interrupts-mac1
>> - - description: interrupt event for ring rxdma2host-monitor-status-ring-mac3
>> - - description: interrupt event for ring rxdma2host-monitor-status-ring-mac2
>> - - description: interrupt event for ring rxdma2host-monitor-status-ring-mac1
>> - - description: interrupt event for ring host2rxdma-host-buf-ring-mac3
>> - - description: interrupt event for ring host2rxdma-host-buf-ring-mac2
>> - - description: interrupt event for ring host2rxdma-host-buf-ring-mac1
>> - - description: interrupt event for ring rxdma2host-destination-ring-mac3
>> - - description: interrupt event for ring rxdma2host-destination-ring-mac2
>> - - description: interrupt event for ring rxdma2host-destination-ring-mac1
>> - - description: interrupt event for ring host2tcl-input-ring4
>> - - description: interrupt event for ring host2tcl-input-ring3
>> - - description: interrupt event for ring host2tcl-input-ring2
>> - - description: interrupt event for ring host2tcl-input-ring1
>> - - description: interrupt event for ring wbm2host-tx-completions-ring3
>> - - description: interrupt event for ring wbm2host-tx-completions-ring2
>> - - description: interrupt event for ring wbm2host-tx-completions-ring1
>> - - description: interrupt event for ring tcl2host-status-ring
>> + reg-names:
>> + maxItems: 1
>
> Need to define the names though for 1 entry, -names is kind of
> pointless.
Makes sense, I'll remove this in the next revision.
>
>>
>> + interrupts:
>> + minItems: 32
>> + maxItems: 52
>>
>> interrupt-names:
>> - items:
>> - - const: misc-pulse1
>> - - const: misc-latch
>> - - const: sw-exception
>> - - const: watchdog
>> - - const: ce0
>> - - const: ce1
>> - - const: ce2
>> - - const: ce3
>> - - const: ce4
>> - - const: ce5
>> - - const: ce6
>> - - const: ce7
>> - - const: ce8
>> - - const: ce9
>> - - const: ce10
>> - - const: ce11
>> - - const: host2wbm-desc-feed
>> - - const: host2reo-re-injection
>> - - const: host2reo-command
>> - - const: host2rxdma-monitor-ring3
>> - - const: host2rxdma-monitor-ring2
>> - - const: host2rxdma-monitor-ring1
>> - - const: reo2ost-exception
>> - - const: wbm2host-rx-release
>> - - const: reo2host-status
>> - - const: reo2host-destination-ring4
>> - - const: reo2host-destination-ring3
>> - - const: reo2host-destination-ring2
>> - - const: reo2host-destination-ring1
>> - - const: rxdma2host-monitor-destination-mac3
>> - - const: rxdma2host-monitor-destination-mac2
>> - - const: rxdma2host-monitor-destination-mac1
>> - - const: ppdu-end-interrupts-mac3
>> - - const: ppdu-end-interrupts-mac2
>> - - const: ppdu-end-interrupts-mac1
>> - - const: rxdma2host-monitor-status-ring-mac3
>> - - const: rxdma2host-monitor-status-ring-mac2
>> - - const: rxdma2host-monitor-status-ring-mac1
>> - - const: host2rxdma-host-buf-ring-mac3
>> - - const: host2rxdma-host-buf-ring-mac2
>> - - const: host2rxdma-host-buf-ring-mac1
>> - - const: rxdma2host-destination-ring-mac3
>> - - const: rxdma2host-destination-ring-mac2
>> - - const: rxdma2host-destination-ring-mac1
>> - - const: host2tcl-input-ring4
>> - - const: host2tcl-input-ring3
>> - - const: host2tcl-input-ring2
>> - - const: host2tcl-input-ring1
>> - - const: wbm2host-tx-completions-ring3
>> - - const: wbm2host-tx-completions-ring2
>> - - const: wbm2host-tx-completions-ring1
>> - - const: tcl2host-status-ring
>> + minItems: 32
>> + maxItems: 52
>
> But you didn't define any names for the new chip.
>
In the case of new chip, interrupts are not tied for a specific purpose
unlike the case of IPQ8074/IPQ6018 where the driver searches an IRQ
based on name. That is the reason why interrupt-names are omitted for
the new chip.
>>
>> qcom,rproc:
>> $ref: /schemas/types.yaml#/definitions/phandle
>> @@ -156,15 +57,201 @@ properties:
>> phandle to a node describing reserved memory (System RAM memory)
>> used by ath11k firmware (see bindings/reserved-memory/reserved-memory.txt)
>>
>> + iommus:
>> + maxItems: 1
>> +
>> + wifi-firmware:
>> + type: object
>> + description: |
>> + WCN6750 wifi node can contain one optional firmware subnode.
>> + Firmware subnode is needed when the platform does not have TustZone.
>
> Trustzone
>
I'll change it.
>> + properties:
>> + iommus:
>> + maxItems: 1
>
> If this is the only property, then just make parent 'iommus' 1 or 2
> entries.
>
You mean something like this shown below?
iommus:
minItems: 1
maxItems: 2
wifi-firmware:
type: object
description: |
WCN6750 wifi node can contain one optional firmware subnode.
Firmware subnode is needed when the platform does not have
Tustzone.
required:
- iommus
>> + required:
>> + - iommus
>> +
>> required:
>> - compatible
>> - reg
>> - interrupts
>> - - interrupt-names
>> - qcom,rproc
>>
>> additionalProperties: false
>>
>> +allOf:
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,ipq8074-wifi
>> + - qcom,ipq6018-wifi
>> + then:
>> + properties:
>> + interrupts:
>> + items:
>> + - description: misc-pulse1 interrupt events
>> + - description: misc-latch interrupt events
>> + - description: sw exception interrupt events
>> + - description: watchdog interrupt events
>> + - description: interrupt event for ring CE0
>> + - description: interrupt event for ring CE1
>> + - description: interrupt event for ring CE2
>> + - description: interrupt event for ring CE3
>> + - description: interrupt event for ring CE4
>> + - description: interrupt event for ring CE5
>> + - description: interrupt event for ring CE6
>> + - description: interrupt event for ring CE7
>> + - description: interrupt event for ring CE8
>> + - description: interrupt event for ring CE9
>> + - description: interrupt event for ring CE10
>> + - description: interrupt event for ring CE11
>> + - description: interrupt event for ring host2wbm-desc-feed
>> + - description: interrupt event for ring host2reo-re-injection
>> + - description: interrupt event for ring host2reo-command
>> + - description: interrupt event for ring host2rxdma-monitor-ring3
>> + - description: interrupt event for ring host2rxdma-monitor-ring2
>> + - description: interrupt event for ring host2rxdma-monitor-ring1
>> + - description: interrupt event for ring reo2ost-exception
>> + - description: interrupt event for ring wbm2host-rx-release
>> + - description: interrupt event for ring reo2host-status
>> + - description: interrupt event for ring reo2host-destination-ring4
>> + - description: interrupt event for ring reo2host-destination-ring3
>> + - description: interrupt event for ring reo2host-destination-ring2
>> + - description: interrupt event for ring reo2host-destination-ring1
>> + - description: interrupt event for ring rxdma2host-monitor-destination-mac3
>> + - description: interrupt event for ring rxdma2host-monitor-destination-mac2
>> + - description: interrupt event for ring rxdma2host-monitor-destination-mac1
>> + - description: interrupt event for ring ppdu-end-interrupts-mac3
>> + - description: interrupt event for ring ppdu-end-interrupts-mac2
>> + - description: interrupt event for ring ppdu-end-interrupts-mac1
>> + - description: interrupt event for ring rxdma2host-monitor-status-ring-mac3
>> + - description: interrupt event for ring rxdma2host-monitor-status-ring-mac2
>> + - description: interrupt event for ring rxdma2host-monitor-status-ring-mac1
>> + - description: interrupt event for ring host2rxdma-host-buf-ring-mac3
>> + - description: interrupt event for ring host2rxdma-host-buf-ring-mac2
>> + - description: interrupt event for ring host2rxdma-host-buf-ring-mac1
>> + - description: interrupt event for ring rxdma2host-destination-ring-mac3
>> + - description: interrupt event for ring rxdma2host-destination-ring-mac2
>> + - description: interrupt event for ring rxdma2host-destination-ring-mac1
>> + - description: interrupt event for ring host2tcl-input-ring4
>> + - description: interrupt event for ring host2tcl-input-ring3
>> + - description: interrupt event for ring host2tcl-input-ring2
>> + - description: interrupt event for ring host2tcl-input-ring1
>> + - description: interrupt event for ring wbm2host-tx-completions-ring3
>> + - description: interrupt event for ring wbm2host-tx-completions-ring2
>> + - description: interrupt event for ring wbm2host-tx-completions-ring1
>> + - description: interrupt event for ring tcl2host-status-ring
>> + interrupt-names:
>> + items:
>> + - const: misc-pulse1
>> + - const: misc-latch
>> + - const: sw-exception
>> + - const: watchdog
>> + - const: ce0
>> + - const: ce1
>> + - const: ce2
>> + - const: ce3
>> + - const: ce4
>> + - const: ce5
>> + - const: ce6
>> + - const: ce7
>> + - const: ce8
>> + - const: ce9
>> + - const: ce10
>> + - const: ce11
>> + - const: host2wbm-desc-feed
>> + - const: host2reo-re-injection
>> + - const: host2reo-command
>> + - const: host2rxdma-monitor-ring3
>> + - const: host2rxdma-monitor-ring2
>> + - const: host2rxdma-monitor-ring1
>> + - const: reo2ost-exception
>> + - const: wbm2host-rx-release
>> + - const: reo2host-status
>> + - const: reo2host-destination-ring4
>> + - const: reo2host-destination-ring3
>> + - const: reo2host-destination-ring2
>> + - const: reo2host-destination-ring1
>> + - const: rxdma2host-monitor-destination-mac3
>> + - const: rxdma2host-monitor-destination-mac2
>> + - const: rxdma2host-monitor-destination-mac1
>> + - const: ppdu-end-interrupts-mac3
>> + - const: ppdu-end-interrupts-mac2
>> + - const: ppdu-end-interrupts-mac1
>> + - const: rxdma2host-monitor-status-ring-mac3
>> + - const: rxdma2host-monitor-status-ring-mac2
>> + - const: rxdma2host-monitor-status-ring-mac1
>> + - const: host2rxdma-host-buf-ring-mac3
>> + - const: host2rxdma-host-buf-ring-mac2
>> + - const: host2rxdma-host-buf-ring-mac1
>> + - const: rxdma2host-destination-ring-mac3
>> + - const: rxdma2host-destination-ring-mac2
>> + - const: rxdma2host-destination-ring-mac1
>> + - const: host2tcl-input-ring4
>> + - const: host2tcl-input-ring3
>> + - const: host2tcl-input-ring2
>> + - const: host2tcl-input-ring1
>> + - const: wbm2host-tx-completions-ring3
>> + - const: wbm2host-tx-completions-ring2
>> + - const: wbm2host-tx-completions-ring1
>> + - const: tcl2host-status-ring
>> +
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,ipq8074-wifi
>> + - qcom,ipq6018-wifi
>> + then:
>> + required:
>> + - interrupt-names
>> +
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,wcn6750-wifi
>> + then:
>> + properties:
>> + interrupts:
>> + items:
>> + - description: interrupt event for ring CE1
>> + - description: interrupt event for ring CE2
>> + - description: interrupt event for ring CE3
>> + - description: interrupt event for ring CE4
>> + - description: interrupt event for ring CE5
>> + - description: interrupt event for ring CE6
>> + - description: interrupt event for ring CE7
>> + - description: interrupt event for ring CE8
>> + - description: interrupt event for ring CE9
>> + - description: interrupt event for ring CE10
>> + - description: interrupt event for ring DP1
>> + - description: interrupt event for ring DP2
>> + - description: interrupt event for ring DP3
>> + - description: interrupt event for ring DP4
>> + - description: interrupt event for ring DP5
>> + - description: interrupt event for ring DP6
>> + - description: interrupt event for ring DP7
>> + - description: interrupt event for ring DP8
>> + - description: interrupt event for ring DP9
>> + - description: interrupt event for ring DP10
>> + - description: interrupt event for ring DP11
>> + - description: interrupt event for ring DP12
>> + - description: interrupt event for ring DP13
>> + - description: interrupt event for ring DP14
>> + - description: interrupt event for ring DP15
>> + - description: interrupt event for ring DP16
>> + - description: interrupt event for ring DP17
>> + - description: interrupt event for ring DP18
>> + - description: interrupt event for ring DP19
>> + - description: interrupt event for ring DP20
>> + - description: interrupt event for ring DP21
>> + - description: interrupt event for ring DP22
>> +
>> examples:
>> - |
>>
>> @@ -309,3 +396,65 @@ examples:
>> };
>> };
>> };
>> +
>> + - |
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + wlan_ce_mem: wlan_ce_mem@4cd000 {
>> + no-map;
>> + reg = <0x0 0x4cd000 0x0 0x1000>;
>> + };
>> +
>> + wlan_fw_mem: wlan_fw_mem@80c00000 {
>> + no-map;
>> + reg = <0x0 0x80c00000 0x0 0xc00000>;
>> + };
>> + };
>> +
>> + wifi: wifi@17a10040 {
>> + compatible = "qcom,wcn6750-wifi";
>> + reg = <0x17A10040 0x0>;
>> + reg-names = "msi_addr";
>> + iommus = <&apps_smmu 0x1C00 0x1>;
>> + interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
>> + qcom,rproc = <&remoteproc_wpss>;
>> + memory-region = <&wlan_fw_mem &wlan_ce_mem>;
>
> memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
>
Okay.
>> + wifi-firmware {
>> + iommus = <&apps_smmu 0x1C02 0x1>;
>> + };
>> + };
>> --
>> 2.7.4
>>
>>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 00/19] add support for WCN6750
2022-01-16 12:46 [PATCH v2 00/19] add support for WCN6750 Manikanta Pubbisetty
` (18 preceding siblings ...)
2022-01-16 12:47 ` [PATCH v2 19/19] dt: bindings: net: add bindings of WCN6750 for ath11k Manikanta Pubbisetty
@ 2022-01-28 10:07 ` Kalle Valo
2022-02-21 6:29 ` Manikanta Pubbisetty
19 siblings, 1 reply; 49+ messages in thread
From: Kalle Valo @ 2022-01-28 10:07 UTC (permalink / raw)
To: Manikanta Pubbisetty; +Cc: ath11k, linux-wireless, devicetree, robh
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
> WCN6750 is non-DBS 2x2 11AX chipset. Unlike QCA6390/WCN6855 which
> are DBS (dual band simultaneous) solutions (2 LMACs), WCN6750 has a
> single LMAC supporting 2G, 5G and 6G bands. It can be operated only
> on one band at any given point.
>
> WCN6750 is a PCIe device. Unlike other supported ATH11K PCIe devices
> which are directly attached to APSS (Application Processor SubSystem),
> WCN6750 is not attached to APSS, it is attached to the WPSS
> (Wireless Processor SubSystem) Q6 processor, the FW which runs on the
> Q6 processor will enumerate the PCIe device. Since APSS is unaware of
> such a device, it has to be registered as a platform device(AHB) to the
> kernel for device probing. Like other AHB devices, remoteproc APIs are
> used to boot up or shutdown of WCN6750.
>
> WCN6750 uses both AHB and PCIe ATH11K APIs for it's operation.
> It uses AHB APIs for device probe and booting of the remote processor.
> Once device is booted up, it uses ATH11K PCIe APIs for initialization
> and register access. Hence, it is referred as hybrid bus device in
> the rest of this series.
>
> Since the chip is enumerated by WPSS Q6, device information like
> BAR and BAR size is not known to the APSS processor. A new QMI message
> called device info QMI request will be sent to the target for fetching
> these details.
>
> STA and AP modes are supported; Basic connectivity and ping are
> verified in both the modes.
>
> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>
> Note:
> * Remoteproc driver changes for WCN6750 which takes care of
> downloading the FW and booting of Q6 processor are under
> upstream review.
> Link: https://patchwork.kernel.org/project/linux-remoteproc/list/?series=582475
This is a very good overview, thanks for that. But I think something
which is not clearly mentioned here is that this only works on Qualcomm
Snapdragon SoC, right? So even though WCN6750 is a PCI device, it cannot
be attached to any platform. It would be good to emphasise that.
> Manikanta Pubbisetty (19):
> ath11k: PCI changes to support WCN6750
> ath11k: Refactor PCI code to support hybrid bus devices
> ath11k: Choose MSI config based on HW revision
> ath11k: Refactor MSI logic
> ath11k: Remove core PCI references from PCI common code
> ath11k: Add HW params for WCN6750
> ath11k: Add bus params for WCN6750
> ath11k: Add register access logic for WCN6750
> ath11k: Fetch device information via QMI for WCN6750
> ath11k: Add QMI changes for WCN6750
> ath11k: HAL changes to support WCN6750
> ath11k: Datapath changes to support WCN6750
> ath11k: Fix RX de-fragmentation issue on WCN6750
> ath11k: Do not put HW in DBS mode for WCN6750
> ath11k: WMI changes to support WCN6750
> ath11k: Update WBM idle ring HP after FW mode on
> ath11k: Add support for WCN6750 device
> ath11k: Add support for targets without trustzone
> dt: bindings: net: add bindings of WCN6750 for ath11k
19 patches is a lot to chew on in one go, my recommendation is to have
max 10-12 patches per set.
In this case having three patchsets would make it a lot easier for
reviewers, but not sure how to split them. Maybe you could submit these
patches separate for preparing WCN6750 support, after a quick look they
seem pretty independent:
ath11k: Fetch device information via QMI for WCN6750
ath11k: HAL changes to support WCN6750
ath11k: Fix RX de-fragmentation issue on WCN6750
ath11k: Do not put HW in DBS mode for WCN6750
ath11k: WMI changes to support WCN6750
--
https://patchwork.kernel.org/project/linux-wireless/list/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 00/19] add support for WCN6750
2022-01-28 10:07 ` [PATCH v2 00/19] add support for WCN6750 Kalle Valo
@ 2022-02-21 6:29 ` Manikanta Pubbisetty
0 siblings, 0 replies; 49+ messages in thread
From: Manikanta Pubbisetty @ 2022-02-21 6:29 UTC (permalink / raw)
To: Kalle Valo; +Cc: ath11k, linux-wireless, devicetree, robh
On 1/28/2022 3:37 PM, Kalle Valo wrote:
> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>
>> WCN6750 is non-DBS 2x2 11AX chipset. Unlike QCA6390/WCN6855 which
>> are DBS (dual band simultaneous) solutions (2 LMACs), WCN6750 has a
>> single LMAC supporting 2G, 5G and 6G bands. It can be operated only
>> on one band at any given point.
>>
>> WCN6750 is a PCIe device. Unlike other supported ATH11K PCIe devices
>> which are directly attached to APSS (Application Processor SubSystem),
>> WCN6750 is not attached to APSS, it is attached to the WPSS
>> (Wireless Processor SubSystem) Q6 processor, the FW which runs on the
>> Q6 processor will enumerate the PCIe device. Since APSS is unaware of
>> such a device, it has to be registered as a platform device(AHB) to the
>> kernel for device probing. Like other AHB devices, remoteproc APIs are
>> used to boot up or shutdown of WCN6750.
>>
>> WCN6750 uses both AHB and PCIe ATH11K APIs for it's operation.
>> It uses AHB APIs for device probe and booting of the remote processor.
>> Once device is booted up, it uses ATH11K PCIe APIs for initialization
>> and register access. Hence, it is referred as hybrid bus device in
>> the rest of this series.
>>
>> Since the chip is enumerated by WPSS Q6, device information like
>> BAR and BAR size is not known to the APSS processor. A new QMI message
>> called device info QMI request will be sent to the target for fetching
>> these details.
>>
>> STA and AP modes are supported; Basic connectivity and ping are
>> verified in both the modes.
>>
>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>
>> Note:
>> * Remoteproc driver changes for WCN6750 which takes care of
>> downloading the FW and booting of Q6 processor are under
>> upstream review.
>> Link: https://patchwork.kernel.org/project/linux-remoteproc/list/?series=582475
> This is a very good overview, thanks for that. But I think something
> which is not clearly mentioned here is that this only works on Qualcomm
> Snapdragon SoC, right?
You are absolutely right.
> So even though WCN6750 is a PCI device, it cannot
> be attached to any platform. It would be good to emphasise that.
I'll add this detail in the next revision.
>> Manikanta Pubbisetty (19):
>> ath11k: PCI changes to support WCN6750
>> ath11k: Refactor PCI code to support hybrid bus devices
>> ath11k: Choose MSI config based on HW revision
>> ath11k: Refactor MSI logic
>> ath11k: Remove core PCI references from PCI common code
>> ath11k: Add HW params for WCN6750
>> ath11k: Add bus params for WCN6750
>> ath11k: Add register access logic for WCN6750
>> ath11k: Fetch device information via QMI for WCN6750
>> ath11k: Add QMI changes for WCN6750
>> ath11k: HAL changes to support WCN6750
>> ath11k: Datapath changes to support WCN6750
>> ath11k: Fix RX de-fragmentation issue on WCN6750
>> ath11k: Do not put HW in DBS mode for WCN6750
>> ath11k: WMI changes to support WCN6750
>> ath11k: Update WBM idle ring HP after FW mode on
>> ath11k: Add support for WCN6750 device
>> ath11k: Add support for targets without trustzone
>> dt: bindings: net: add bindings of WCN6750 for ath11k
> 19 patches is a lot to chew on in one go, my recommendation is to have
> max 10-12 patches per set.
>
> In this case having three patchsets would make it a lot easier for
> reviewers, but not sure how to split them. Maybe you could submit these
> patches separate for preparing WCN6750 support, after a quick look they
> seem pretty independent:
>
> ath11k: Fetch device information via QMI for WCN6750
> ath11k: HAL changes to support WCN6750
> ath11k: Fix RX de-fragmentation issue on WCN6750
> ath11k: Do not put HW in DBS mode for WCN6750
> ath11k: WMI changes to support WCN6750
Sure, I'll logically split the series in the next revisions.
^ permalink raw reply [flat|nested] 49+ messages in thread