From: Krishna chaitanya chundru <quic_krichai@quicinc.com>
To: manivannan.sadhasivam@linaro.org
Cc: quic_vbadigan@quicinc.com, quic_ramkri@quicinc.com,
"Krishna chaitanya chundru" <quic_krichai@quicinc.com>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci@vger.kernel.org (open list:PCIE ENDPOINT DRIVER FOR
QUALCOMM),
linux-arm-msm@vger.kernel.org (open list:PCIE ENDPOINT DRIVER
FOR QUALCOMM), linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v2 3/3] PCI: qcom-ep: Add ICC bandwidth voting support
Date: Wed, 7 Jun 2023 21:48:07 +0530 [thread overview]
Message-ID: <1686154687-29356-4-git-send-email-quic_krichai@quicinc.com> (raw)
In-Reply-To: <1686154687-29356-1-git-send-email-quic_krichai@quicinc.com>
Add support to vote for ICC bandwidth based on the link
speed and width.
This patch is inspired from pcie-qcom driver to add basic
interconnect support.
Link:https://patchwork.kernel.org/project/linux-pci/patch/20221102090705.23634-3-johan+linaro@kernel.org/
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
---
drivers/pci/controller/dwc/pcie-qcom-ep.c | 68 +++++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 19b3283..5f9139d 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -13,6 +13,7 @@
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
+#include <linux/interconnect.h>
#include <linux/mfd/syscon.h>
#include <linux/phy/pcie.h>
#include <linux/phy/phy.h>
@@ -28,6 +29,7 @@
#define PARF_SYS_CTRL 0x00
#define PARF_DB_CTRL 0x10
#define PARF_PM_CTRL 0x20
+#define PARF_PM_STTS 0x24
#define PARF_MHI_CLOCK_RESET_CTRL 0x174
#define PARF_MHI_BASE_ADDR_LOWER 0x178
#define PARF_MHI_BASE_ADDR_UPPER 0x17c
@@ -128,6 +130,9 @@
/* DBI register fields */
#define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0)
+#define DBI_LINKCTRLSTATUS 0x80
+#define DBI_LINKCTRLSTATUS_SHIFT 16
+
#define XMLH_LINK_UP 0x400
#define CORE_RESET_TIME_US_MIN 1000
#define CORE_RESET_TIME_US_MAX 1005
@@ -178,6 +183,8 @@ struct qcom_pcie_ep {
struct phy *phy;
struct dentry *debugfs;
+ struct icc_path *icc;
+
struct clk_bulk_data *clks;
int num_clks;
@@ -253,9 +260,51 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci)
disable_irq(pcie_ep->perst_irq);
}
+static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep)
+{
+ struct dw_pcie *pci = &pcie_ep->pci;
+ int speed, width;
+ u32 val, bw;
+ int ret;
+
+ if (!pcie_ep->icc)
+ return;
+
+ val = dw_pcie_readl_dbi(pci, DBI_LINKCTRLSTATUS);
+ val = val >> DBI_LINKCTRLSTATUS_SHIFT;
+
+ speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, val);
+ width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val);
+
+ switch (speed) {
+ case 1:
+ bw = MBps_to_icc(250); /* BW for GEN1 per lane: 250MBps */
+ break;
+ case 2:
+ bw = MBps_to_icc(500); /* BW for GEN2 per lane: 500MBps */
+ break;
+ case 3:
+ bw = MBps_to_icc(985); /* BW for GEN3 per lane: 985MBps */
+ break;
+ default:
+ WARN_ON_ONCE(1);
+ fallthrough;
+ case 4:
+ bw = MBps_to_icc(1969); /* BW for GEN4 per lane: 985MBps */
+ break;
+ }
+
+ ret = icc_set_bw(pcie_ep->icc, 0, width * bw);
+ if (ret) {
+ dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
+ ret);
+ }
+}
+
static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
{
int ret;
+ struct dw_pcie *pci = &pcie_ep->pci;
ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks);
if (ret)
@@ -277,6 +326,20 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
if (ret)
goto err_phy_exit;
+ /*
+ * Some Qualcomm platforms require interconnect bandwidth constraints
+ * to be set before enabling interconnect clocks.
+ *
+ * Set an initial average bandwidth corresponding to single-lane Gen 1
+ * for the pcie to mem path.
+ */
+ ret = icc_set_bw(pcie_ep->icc, 0, MBps_to_icc(250)); /* BW for GEN1 per lane: 250MBps */
+ if (ret) {
+ dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
+ ret);
+ goto err_phy_exit;
+ }
+
return 0;
err_phy_exit:
@@ -550,6 +613,10 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev,
if (IS_ERR(pcie_ep->phy))
ret = PTR_ERR(pcie_ep->phy);
+ pcie_ep->icc = devm_of_icc_get(dev, "pcie-mem");
+ if (IS_ERR(pcie_ep->icc))
+ ret = PTR_ERR(pcie_ep->icc);
+
return ret;
}
@@ -572,6 +639,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data)
} else if (FIELD_GET(PARF_INT_ALL_BME, status)) {
dev_dbg(dev, "Received BME event. Link is enabled!\n");
pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED;
+ qcom_pcie_ep_icc_update(pcie_ep);
} else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) {
dev_dbg(dev, "Received PM Turn-off event! Entering L23\n");
val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
--
2.7.4
next prev parent reply other threads:[~2023-06-07 16:18 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1686154687-29356-1-git-send-email-quic_krichai@quicinc.com>
2023-06-07 16:18 ` [PATCH v2 1/3] dt-bindings: PCI: qcom: ep: Add interconnects path Krishna chaitanya chundru
2023-06-07 17:21 ` Rob Herring
2023-06-09 11:55 ` Krishna Chaitanya Chundru
2023-06-09 15:34 ` Krzysztof Kozlowski
2023-06-08 15:27 ` Rob Herring
2023-06-08 15:52 ` Manivannan Sadhasivam
2023-06-07 16:18 ` [PATCH v2 2/3] arm: dts: qcom: sdx55: Add interconnect path Krishna chaitanya chundru
2023-06-08 16:00 ` Manivannan Sadhasivam
2023-06-09 11:09 ` kernel test robot
2023-06-07 16:18 ` Krishna chaitanya chundru [this message]
2023-06-07 16:43 ` [PATCH v2 3/3] PCI: qcom-ep: Add ICC bandwidth voting support Bjorn Helgaas
2023-06-09 11:50 ` Krishna Chaitanya Chundru
2023-06-09 11:52 ` Krishna Chaitanya Chundru
2023-06-09 16:58 ` Bjorn Helgaas
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