* [PATCH v2 0/2] arm64: qcom: sa8775p: add support for x4 EP PCIe controller
@ 2024-04-30 16:21 Mrinmay Sarkar
2024-04-30 16:21 ` [PATCH v2 1/2] phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p Mrinmay Sarkar
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Mrinmay Sarkar @ 2024-04-30 16:21 UTC (permalink / raw
To: andersson, krzysztof.kozlowski+dt, conor+dt, konrad.dybcio,
manivannan.sadhasivam
Cc: quic_shazhuss, quic_nitegupt, quic_ramkri, quic_nayiluri,
quic_krichai, quic_vbadigan, quic_schintav, Mrinmay Sarkar,
Rob Herring, Krzysztof Kozlowski, Vinod Koul,
Kishon Vijay Abraham I, Dmitry Baryshkov, Neil Armstrong,
Qiang Yu, Abel Vesa, linux-arm-msm, devicetree, linux-kernel,
linux-phy
This series updates PHY and add EP PCIe node in dtsi file for
ep pcie1 controller that supports gen4 and x4 lane width.
Dependency for Patch 2
----------------------
Depends on:
https://lore.kernel.org/all/1714492540-15419-1-git-send-email-quic_msarkar@quicinc.com/
V1 -> V2:
- Added Reviewed-by tag in patch 1
- Fixed indentation in patch 2
- Fixed merged conflict on patch 2 and rebased on top of v6.9-rc6
- link to v1: https://lore.kernel.org/all/1699362294-15558-1-git-send-email-quic_msarkar@quicinc.com/
Mrinmay Sarkar (2):
phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p
arm64: dts: qcom: sa8775p: Add ep pcie1 controller node
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 47 ++++++++++++++++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 +++++-
2 files changed, 55 insertions(+), 1 deletion(-)
--
2.7.4
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/2] phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p
2024-04-30 16:21 [PATCH v2 0/2] arm64: qcom: sa8775p: add support for x4 EP PCIe controller Mrinmay Sarkar
@ 2024-04-30 16:21 ` Mrinmay Sarkar
2024-04-30 16:21 ` [PATCH v2 2/2] arm64: dts: qcom: sa8775p: Add ep pcie1 controller node Mrinmay Sarkar
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Mrinmay Sarkar @ 2024-04-30 16:21 UTC (permalink / raw
To: andersson, krzysztof.kozlowski+dt, conor+dt, konrad.dybcio,
manivannan.sadhasivam
Cc: quic_shazhuss, quic_nitegupt, quic_ramkri, quic_nayiluri,
quic_krichai, quic_vbadigan, quic_schintav, Mrinmay Sarkar,
Rob Herring, Krzysztof Kozlowski, Vinod Koul,
Kishon Vijay Abraham I, Dmitry Baryshkov, Neil Armstrong,
Abel Vesa, Can Guo, linux-arm-msm, devicetree, linux-kernel,
linux-phy
Add support for x4 lane end point mode PHY found on sa8755p platform.
Reusing existing serdes and pcs_misc table for EP and moved
BIAS_EN_CLKBUFLR_EN register from RC serdes table to common serdes
table as this register is part of both RC and EP.
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index e3103bc..6c79672 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -2248,6 +2248,7 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl[] = {
};
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
@@ -2274,7 +2275,6 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[]
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
@@ -3306,6 +3306,13 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = {
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
},
+ .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
+ .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl,
+ .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl),
+ .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
+ .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
+ },
+
.reset_list = sdm845_pciephy_reset_l,
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
.vreg_list = qmp_phy_vreg_l,
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] arm64: dts: qcom: sa8775p: Add ep pcie1 controller node
2024-04-30 16:21 [PATCH v2 0/2] arm64: qcom: sa8775p: add support for x4 EP PCIe controller Mrinmay Sarkar
2024-04-30 16:21 ` [PATCH v2 1/2] phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p Mrinmay Sarkar
@ 2024-04-30 16:21 ` Mrinmay Sarkar
2024-05-04 12:14 ` (subset) [PATCH v2 0/2] arm64: qcom: sa8775p: add support for x4 EP PCIe controller Vinod Koul
2024-05-27 3:00 ` Bjorn Andersson
3 siblings, 0 replies; 5+ messages in thread
From: Mrinmay Sarkar @ 2024-04-30 16:21 UTC (permalink / raw
To: andersson, krzysztof.kozlowski+dt, conor+dt, konrad.dybcio,
manivannan.sadhasivam
Cc: quic_shazhuss, quic_nitegupt, quic_ramkri, quic_nayiluri,
quic_krichai, quic_vbadigan, quic_schintav, Mrinmay Sarkar,
Rob Herring, Krzysztof Kozlowski, Vinod Koul,
Kishon Vijay Abraham I, Dmitry Baryshkov, Neil Armstrong,
Qiang Yu, Abel Vesa, linux-arm-msm, devicetree, linux-kernel,
linux-phy
Add ep pcie dtsi node for pcie1 controller found on sa8775p platform.
It supports gen4 and x4 link width. Limiting the speed to Gen3 due to
stability issue with Gen4.
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 47 +++++++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 4084e77..9065645 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3845,6 +3845,53 @@
};
};
+ pcie1_ep: pcie-ep@1c10000 {
+ compatible = "qcom,sa8775p-pcie-ep";
+ reg = <0x0 0x01c10000 0x0 0x3000>,
+ <0x0 0x60000000 0x0 0xf20>,
+ <0x0 0x60000f20 0x0 0xa8>,
+ <0x0 0x60001000 0x0 0x4000>,
+ <0x0 0x60200000 0x0 0x100000>,
+ <0x0 0x01c13000 0x0 0x1000>,
+ <0x0 0x60005000 0x0 0x2000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
+ "mmio", "dma";
+
+ clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
+
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a";
+
+ interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "global", "doorbell", "dma";
+
+ interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ dma-coherent;
+ iommus = <&pcie_smmu 0x80 0x7f>;
+ resets = <&gcc GCC_PCIE_1_BCR>;
+ reset-names = "core";
+ power-domains = <&gcc PCIE_1_GDSC>;
+ phys = <&pcie1_phy>;
+ phy-names = "pciephy";
+ max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
+ num-lanes = <4>;
+
+ status = "disabled";
+ };
+
pcie1_phy: phy@1c14000 {
compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
reg = <0x0 0x1c14000 0x0 0x4000>;
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: (subset) [PATCH v2 0/2] arm64: qcom: sa8775p: add support for x4 EP PCIe controller
2024-04-30 16:21 [PATCH v2 0/2] arm64: qcom: sa8775p: add support for x4 EP PCIe controller Mrinmay Sarkar
2024-04-30 16:21 ` [PATCH v2 1/2] phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p Mrinmay Sarkar
2024-04-30 16:21 ` [PATCH v2 2/2] arm64: dts: qcom: sa8775p: Add ep pcie1 controller node Mrinmay Sarkar
@ 2024-05-04 12:14 ` Vinod Koul
2024-05-27 3:00 ` Bjorn Andersson
3 siblings, 0 replies; 5+ messages in thread
From: Vinod Koul @ 2024-05-04 12:14 UTC (permalink / raw
To: andersson, krzysztof.kozlowski+dt, conor+dt, konrad.dybcio,
manivannan.sadhasivam, Mrinmay Sarkar
Cc: quic_shazhuss, quic_nitegupt, quic_ramkri, quic_nayiluri,
quic_krichai, quic_vbadigan, quic_schintav, Rob Herring,
Krzysztof Kozlowski, Kishon Vijay Abraham I, Dmitry Baryshkov,
Neil Armstrong, Qiang Yu, Abel Vesa, linux-arm-msm, devicetree,
linux-kernel, linux-phy
On Tue, 30 Apr 2024 21:51:25 +0530, Mrinmay Sarkar wrote:
> This series updates PHY and add EP PCIe node in dtsi file for
> ep pcie1 controller that supports gen4 and x4 lane width.
>
> Dependency for Patch 2
> ----------------------
>
> Depends on:
> https://lore.kernel.org/all/1714492540-15419-1-git-send-email-quic_msarkar@quicinc.com/
>
> [...]
Applied, thanks!
[1/2] phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p
commit: 82b7487b8eb93e82ace92866560de3d4952555db
Best regards,
--
~Vinod
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: (subset) [PATCH v2 0/2] arm64: qcom: sa8775p: add support for x4 EP PCIe controller
2024-04-30 16:21 [PATCH v2 0/2] arm64: qcom: sa8775p: add support for x4 EP PCIe controller Mrinmay Sarkar
` (2 preceding siblings ...)
2024-05-04 12:14 ` (subset) [PATCH v2 0/2] arm64: qcom: sa8775p: add support for x4 EP PCIe controller Vinod Koul
@ 2024-05-27 3:00 ` Bjorn Andersson
3 siblings, 0 replies; 5+ messages in thread
From: Bjorn Andersson @ 2024-05-27 3:00 UTC (permalink / raw
To: krzysztof.kozlowski+dt, conor+dt, konrad.dybcio,
manivannan.sadhasivam, Mrinmay Sarkar
Cc: quic_shazhuss, quic_nitegupt, quic_ramkri, quic_nayiluri,
quic_krichai, quic_vbadigan, quic_schintav, Rob Herring,
Krzysztof Kozlowski, Vinod Koul, Kishon Vijay Abraham I,
Dmitry Baryshkov, Neil Armstrong, Qiang Yu, Abel Vesa,
linux-arm-msm, devicetree, linux-kernel, linux-phy
On Tue, 30 Apr 2024 21:51:25 +0530, Mrinmay Sarkar wrote:
> This series updates PHY and add EP PCIe node in dtsi file for
> ep pcie1 controller that supports gen4 and x4 lane width.
>
> Dependency for Patch 2
> ----------------------
>
> Depends on:
> https://lore.kernel.org/all/1714492540-15419-1-git-send-email-quic_msarkar@quicinc.com/
>
> [...]
Applied, thanks!
[2/2] arm64: dts: qcom: sa8775p: Add ep pcie1 controller node
commit: c5f5de8434ec35d8ccd5b3a746df3afb37bfefeb
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 5+ messages in thread
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2024-04-30 16:21 [PATCH v2 0/2] arm64: qcom: sa8775p: add support for x4 EP PCIe controller Mrinmay Sarkar
2024-04-30 16:21 ` [PATCH v2 1/2] phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p Mrinmay Sarkar
2024-04-30 16:21 ` [PATCH v2 2/2] arm64: dts: qcom: sa8775p: Add ep pcie1 controller node Mrinmay Sarkar
2024-05-04 12:14 ` (subset) [PATCH v2 0/2] arm64: qcom: sa8775p: add support for x4 EP PCIe controller Vinod Koul
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