From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752650AbcBASkG (ORCPT ); Mon, 1 Feb 2016 13:40:06 -0500 Received: from smtp5-g21.free.fr ([212.27.42.5]:7338 "EHLO smtp5-g21.free.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751798AbcBASkF convert rfc822-to-8bit (ORCPT ); Mon, 1 Feb 2016 13:40:05 -0500 Date: Mon, 1 Feb 2016 19:40:00 +0100 From: Jean-Francois Moine To: Andre Przywara Cc: Maxime Ripard , Chen-Yu Tsai , linux-sunxi@googlegroups.com, Arnd Bergmann , Emilio =?ISO-8859-1?Q?L=F3pez?= , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, Jens Kuske , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 06/11] clk: sunxi: add generic multi-parent bus clock gates driver Message-Id: <20160201194000.282a253b14a2ab35df8b8cc7@free.fr> In-Reply-To: <1454348370-3816-7-git-send-email-andre.przywara@arm.com> References: <1454348370-3816-1-git-send-email-andre.przywara@arm.com> <1454348370-3816-7-git-send-email-andre.przywara@arm.com> X-Mailer: Sylpheed 3.4.3 (GTK+ 2.24.29; armv7l-unknown-linux-gnueabihf) Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 1 Feb 2016 17:39:25 +0000 Andre Przywara wrote: > The Allwinner H3 SoC introduced bus clock gates with potentially > different parents per clock gate. The H3 driver chose to hardcode the > actual parent clock relation in the code. > Add a new driver (which has the potential to drive the H3 and also > the simple clock gates as well) which uses the power of DT to describe > this relationship in an elegant and flexible way. > Using one subnode for every parent clock we get away with a single > DT compatible match, which can be used as a fallback value in the > actual DTs without the need to add specific compatible strings to the > code. This avoids adding a new driver or function for every new SoC. > > Signed-off-by: Andre Przywara > --- > Changelog RFC .. v1: > - fix IRQ muxes to cover the three banks of the SoC > - amend naming of PCM pins > > drivers/clk/sunxi/Makefile | 1 + > drivers/clk/sunxi/clk-multi-gates.c | 105 ++++++++++++++++++++++++++++++++++++ > 2 files changed, 106 insertions(+) > create mode 100644 drivers/clk/sunxi/clk-multi-gates.c [snip] Glad to see that things are moving to the right way. Thanks. Acked-by: Jean-Francois Moine -- Ken ar c'hentań | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/