From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753464AbcBENdY (ORCPT ); Fri, 5 Feb 2016 08:33:24 -0500 Received: from down.free-electrons.com ([37.187.137.238]:54462 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752821AbcBENdV (ORCPT ); Fri, 5 Feb 2016 08:33:21 -0500 Date: Fri, 5 Feb 2016 14:33:18 +0100 From: Thomas Petazzoni To: Timur Tabi Cc: Fu Wei , Guenter Roeck , Rob Herring , =?UTF-8?B?UGF3ZcWC?= Moll , Mark Rutland , Ian Campbell , Kumar Gala , Wim Van Sebroeck , Jon Corbet , Catalin Marinas , Will Deacon , Suravee Suthikulpanit , LKML , linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Linaro ACPI Mailman List , rruigrok@codeaurora.org, "Abdulhamid, Harb" , Christopher Covington , Dave Young , Pratyush Anand , G Gregory , Al Stone , Hanjun Guo , Jon Masters , Arnd Bergmann , Leo Duran , Sudeep Holla Subject: Re: [PATCH v10 5/5] Watchdog: ARM SBSA Generic Watchdog half timeout panic support Message-ID: <20160205143318.2de2815c@free-electrons.com> In-Reply-To: <56B49EC7.4050306@codeaurora.org> References: <1454519923-25230-1-git-send-email-fu.wei@linaro.org> <1454519923-25230-6-git-send-email-fu.wei@linaro.org> <56B23883.7000501@codeaurora.org> <56B23E99.1030604@codeaurora.org> <56B2423B.1020109@codeaurora.org> <56B24642.8090105@codeaurora.org> <56B24AB5.3070001@codeaurora.org> <56B2DEE4.7060901@roeck-us.net> <20160205140259.72a33699@free-electrons.com> <56B49EC7.4050306@codeaurora.org> Organization: Free Electrons X-Mailer: Claws Mail 3.12.0 (GTK+ 2.24.28; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello, On Fri, 5 Feb 2016 07:08:23 -0600, Timur Tabi wrote: > > I'm quite certainly missing something completely obvious here, but how > > can you get the WS1 interrupt*after* raising a panic? Aren't all > > interrupts disabled and the system fully halted once you get a panic(), > > especially when raised from an interrupt handler? If that's the case, > > how can the system continue to do things, such as receiving the WS1 > > interrupt and resetting ? > > Typically, WS1 is not an interrupt. Instead, it's a hard system-level > reset. Ah, right, true. I missed that aspect because on my HW, triggering a system-level reset on WS1 is optional. I can actually get an interrupt on both WS0 and WS1, and no reset at all. But a normal configuration indeed involves having the WS1 event configured in HW to be a system-level reset. So, OK, it makes sense. Thanks for the clarification! Thomas -- Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com