From: Zong Li <zong.li@sifive.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com, sboyd@kernel.org,
schwab@linux-m68k.org, pragnesh.patel@openfive.com,
aou@eecs.berkeley.edu, mturquette@baylibre.com,
yash.shah@sifive.com, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org
Cc: Zong Li <zong.li@sifive.com>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Pragnesh Patel <Pragnesh.patel@sifive.com>
Subject: [PATCH v7 2/5] clk: sifive: Use common name for prci configuration
Date: Wed, 9 Dec 2020 17:49:13 +0800 [thread overview]
Message-ID: <20201209094916.17383-3-zong.li@sifive.com> (raw)
In-Reply-To: <20201209094916.17383-1-zong.li@sifive.com>
Use generic name CLK_SIFIVE_PRCI instead of CLK_SIFIVE_FU540_PRCI. This
patch is prepared for fu740 support.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
---
arch/riscv/Kconfig.socs | 2 +-
drivers/clk/sifive/Kconfig | 6 +++---
drivers/clk/sifive/Makefile | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 8a55f6156661..3284d5c291be 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -5,7 +5,7 @@ config SOC_SIFIVE
select SERIAL_SIFIVE if TTY
select SERIAL_SIFIVE_CONSOLE if TTY
select CLK_SIFIVE
- select CLK_SIFIVE_FU540_PRCI
+ select CLK_SIFIVE_PRCI
select SIFIVE_PLIC
help
This enables support for SiFive SoC platform hardware.
diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
index f3b4eb9cb0f5..ab48cf7e0105 100644
--- a/drivers/clk/sifive/Kconfig
+++ b/drivers/clk/sifive/Kconfig
@@ -8,12 +8,12 @@ menuconfig CLK_SIFIVE
if CLK_SIFIVE
-config CLK_SIFIVE_FU540_PRCI
- bool "PRCI driver for SiFive FU540 SoCs"
+config CLK_SIFIVE_PRCI
+ bool "PRCI driver for SiFive SoCs"
select CLK_ANALOGBITS_WRPLL_CLN28HPC
help
Supports the Power Reset Clock interface (PRCI) IP block found in
- FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
+ FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
enable this driver.
endif
diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
index 51b6ebc359e4..3074cdbc6009 100644
--- a/drivers/clk/sifive/Makefile
+++ b/drivers/clk/sifive/Makefile
@@ -1,2 +1,2 @@
# SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI) += sifive-prci.o fu540-prci.o
+obj-$(CONFIG_CLK_SIFIVE_PRCI) += sifive-prci.o fu540-prci.o
--
2.29.2
next prev parent reply other threads:[~2020-12-09 9:50 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-09 9:49 [PATCH v7 0/5] clk: add driver for the SiFive FU740 Zong Li
2020-12-09 9:49 ` [PATCH v7 1/5] clk: sifive: Extract prci core to common base Zong Li
2020-12-16 20:21 ` Stephen Boyd
2020-12-09 9:49 ` Zong Li [this message]
2020-12-16 20:21 ` [PATCH v7 2/5] clk: sifive: Use common name for prci configuration Stephen Boyd
2020-12-09 9:49 ` [PATCH v7 3/5] clk: sifive: Add a driver for the SiFive FU740 PRCI IP block Zong Li
2020-12-16 20:21 ` Stephen Boyd
2020-12-09 9:49 ` [PATCH v7 4/5] clk: sifive: Fix the wrong bit field shift Zong Li
2020-12-16 20:21 ` Stephen Boyd
2020-12-09 9:49 ` [PATCH v7 5/5] clk: sifive: Add clock enable and disable ops Zong Li
2020-12-16 20:21 ` Stephen Boyd
2021-03-16 19:45 ` [PATCH v7 0/5] clk: add driver for the SiFive FU740 Andreas Schwab
2021-03-18 2:07 ` Zong Li
2021-03-19 8:20 ` Zong Li
2021-03-19 8:44 ` Yixun Lan
2021-03-19 8:49 ` Andreas Schwab
2021-03-24 10:36 ` Andreas Schwab
2021-03-25 3:21 ` Zong Li
2021-03-25 9:22 ` Andreas Schwab
2021-03-26 9:10 ` Zong Li
2021-03-26 9:23 ` Andreas Schwab
2021-03-29 10:18 ` Zong Li
2021-03-29 10:37 ` Andreas Schwab
2021-03-31 8:11 ` Zong Li
2021-04-12 11:31 ` Andreas Schwab
2021-04-14 14:13 ` Zong Li
2021-05-11 8:53 ` Yixun Lan
2021-05-19 15:53 ` Zong Li
2021-05-19 18:17 ` Geert Uytterhoeven
2021-05-21 10:34 ` Zong Li
2021-05-21 12:52 ` Zong Li
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