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Miller" , Dennis Dalessandro , Devesh Sharma , Faisal Latif , Jack Wang , Jakub Kicinski , Bruce Fields , Jens Axboe , Karsten Graul , Keith Busch , Lijun Ou , CIFS , LKML , Linux NFS Mailing List , "linux-nvme@lists.infradead.org" , OFED mailing list , "linux-s390@vger.kernel.org" , Max Gurtovoy , Max Gurtovoy , "Md. Haris Iqbal" , Michael Guralnik , Michal Kalderon , Mike Marciniszyn , Naresh Kumar PBS , Linux-Net , Potnuri Bharat Teja , "rds-devel@oss.oracle.com" , Sagi Grimberg , "samba-technical@lists.samba.org" , Santosh Shilimkar , Selvin Xavier , Shiraz Saleem , Somnath Kotur , Sriharsha Basavapatna , Steve French , Trond Myklebust , VMware PV-Drivers , Weihang Li , Yishai Hadas , Zhu Yanjun Subject: Re: [PATCH rdma-next 00/10] Enable relaxed ordering for ULPs Message-ID: <20210414144907.GD1370958@nvidia.com> References: <8A5E83DF-5C08-49CE-8EE3-08DC63135735@oracle.com> <4b02d1b2-be0e-0d1d-7ac3-38d32e44e77e@talpey.com> <1FA38618-E245-4C53-BF49-6688CA93C660@oracle.com> <7b9e7d9c-13d7-0d18-23b4-0d94409c7741@talpey.com> <880A23A2-F078-42CF-BEE2-30666BCB9B5D@oracle.com> <7deadc67-650c-ea15-722b-a1d77d38faba@talpey.com> <20210412224843.GQ7405@nvidia.com> <02593083-056e-cc62-22cf-d6bd6c9b18a8@talpey.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Originating-IP: [142.162.115.133] X-ClientProxiedBy: MN2PR16CA0011.namprd16.prod.outlook.com (2603:10b6:208:134::24) To DM6PR12MB3834.namprd12.prod.outlook.com (2603:10b6:5:14a::12) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from mlx.ziepe.ca (142.162.115.133) by MN2PR16CA0011.namprd16.prod.outlook.com (2603:10b6:208:134::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4042.16 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?Fcs4gwxFQ9tsPg4lFbTieG9fbnkmkUOclKLV3cI1ZYcXkSS3fUzqDlL2qq2V?= =?us-ascii?Q?u5ka/JRMfnEdyaHNBseXWzx7QD8ndvkbdYuYmNHPOaRNSpgJNiZFLPjUQh9z?= =?us-ascii?Q?gMkz504WoeyE443IIaNyaHAGfn6YGSQ3IUYg/So/NGWWXWdyZucrvVa1IU55?= =?us-ascii?Q?/0cNVXqU7BRxn+zT1P631QBOUkS88rAv5AlH2r21sQvOonKp3Kde64H3HtO8?= =?us-ascii?Q?1NXgXqssPGX1BwYAbG8eUCTaDglDVG5yuxAqN7aAyRj9e+XUbefMJybNVjLM?= =?us-ascii?Q?csxjSbv0+9HymF3wco+VcLpaeqDZO1COJGjnYcmHLVLmvW1vFRQU6cc/f3M7?= =?us-ascii?Q?X9NbvO9dv7BeUaYPGV8BXbh5SfFXBalfsbfQZsk6i5z0DWF4xPsrKFMqVNYZ?= =?us-ascii?Q?8g+MhCFC5sGvpw4NahmtROpKS8sNdLWzB/24+qF5gmaGm/8pltH+/Y1iloPW?= =?us-ascii?Q?XWrDic77OecTyLit68J61YkTH9SbXv3m2jLG8JZFzL7Al24B0bbUtnINGaMW?= =?us-ascii?Q?6YT4yMEvBHDKzsd755KLUHdHuhGbQe0Abd1M3rxQ72CEw0ue26rCLZdgUc4Z?= =?us-ascii?Q?O9fq1Klzp2v0epJrvEUfxr5Pk/TjkQ+mAdIDc087T+J2ID7Wd4Ps80VKWPwh?= =?us-ascii?Q?Ondzk16ALxcp+EX3ShIkSaEviCogEhjf1H+S/1CHwsKUITEwHXpwDoTeqoFC?= =?us-ascii?Q?9BxfNzvNtlE6RJpQCENwT36v7IH1Gh6qMxMsCCkDJhPhoPMcnAxwx96mprqC?= =?us-ascii?Q?REmRmwkvCbQpHwvviAEj6Rk5lTj4oO4wWt00ECX5Ws3VA4g8EXZeoyDMbmJ7?= =?us-ascii?Q?NnsncTl85jJgzSbDcv+V0Nyi7HDpvIzNbteuoRHU7yKyXgAiQSzd201jr7QV?= =?us-ascii?Q?XgXiL7uY+UV3g4PhoV6z/+BdCn3CA5LnHHZrR/i9tKfc9qjbxKzr0lG+YlBu?= =?us-ascii?Q?LuTKFunuIi3UdDn+QUmI8c6UQcYhh7n7zwKaoPgBc+r6gc8szahbpOvT3n4l?= =?us-ascii?Q?Po0UwEzPHPNzlVxW8EMNTKN74pnLdMVKui5qhni90bGmO9dn1XUGETycTqaw?= =?us-ascii?Q?AC6JVEjId3x0to48+G6Nay8Bn0E81MwVHEmDN7T3Xefm/Omf+VBf9pnPq4OU?= =?us-ascii?Q?0wo8E+TLGPzk8hXpnKMSuHc/iVYa9icKrmRaJ/hbzedGXETQgnMJxLiCBjXl?= =?us-ascii?Q?vx3LHHWOw+zvEBEGUgWqxJC+tWzVyxIgVW3CpUJonf9zf81Xe4xTqG6YlDd4?= =?us-ascii?Q?2f/GAWE406yXvfN5qjuULIKLeCbcz3J7v31BpeELsTJYGKIJ157IEmdml56T?= =?us-ascii?Q?4xQahhYDYzUiNrYWw+JAfobcXqXNyCjykS4zK6wAyL10rQ=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4053342e-6ed5-4bc1-3c62-08d8ff547571 X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3834.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2021 14:49:08.9803 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: KC3J15Oe0Fv0gtkVf31Qnsl5m7MPF0yPgTE3ZbViDQqa7gI6EvKI8e4EJJBCTs3B X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1148 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Apr 14, 2021 at 02:41:52PM +0000, David Laight wrote: > So whatever driver initialises the target needs to configure whatever > target-specific register enables the RO transfers themselves. RDMA in general, and mlx5 in particular, is a layered design: mlx5_core <- owns the PCI function, should turn on RO at the PCI function level mlx5_en <- Commands the chip to use RO for queues used in ethernet ib_core ib_uverbs mlx5_ib <- Commands the chip to use RO for some queues used in userspace ib_srp* <- A ULP driver built on RDMA - this patch commands the chip to use RO on SRP queues nvme-rdma <- Ditto ib_iser <- Ditto rds <- Ditto So this series is about expanding the set of queues running on mlx5 that have RO turned when the PCI function is already running with RO enabled. We want as many queues as possible RO enabled because it brings big performance wins Jason