* [PATCH 1/3] arm64: dts: renesas: r8a779a0: Add DU support
[not found] <20210622234257.3228634-1-kieran.bingham@ideasonboard.com>
@ 2021-06-22 23:42 ` Kieran Bingham
2021-06-23 13:00 ` Geert Uytterhoeven
2021-06-22 23:42 ` [PATCH 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders Kieran Bingham
2021-06-22 23:42 ` [PATCH 3/3] arm64: dts: renesas: falcon-cpu: Add DSI display output Kieran Bingham
2 siblings, 1 reply; 4+ messages in thread
From: Kieran Bingham @ 2021-06-22 23:42 UTC (permalink / raw
To: Geert Uytterhoeven, Kieran Bingham
Cc: Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring,
open list:ARM/RENESAS ARM64 ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Provide the device nodes for the DU on the V3U platforms.
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
---
arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 31 +++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index 78ca75f619f6..24476886e498 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -1142,6 +1142,37 @@ vspd1: vsp@fea28000 {
renesas,fcp = <&fcpvd1>;
};
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a779a0";
+ reg = <0 0xfeb00000 0 0x40000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 411>,
+ <&cpg CPG_MOD 411>;
+ clock-names = "du.0", "du.1";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 411>;
+ vsps = <&vspd0 0>, <&vspd1 0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_dsi0: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ du_out_dsi1: endpoint {
+ };
+ };
+ };
+ };
+
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
--
2.30.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders
[not found] <20210622234257.3228634-1-kieran.bingham@ideasonboard.com>
2021-06-22 23:42 ` [PATCH 1/3] arm64: dts: renesas: r8a779a0: Add DU support Kieran Bingham
@ 2021-06-22 23:42 ` Kieran Bingham
2021-06-22 23:42 ` [PATCH 3/3] arm64: dts: renesas: falcon-cpu: Add DSI display output Kieran Bingham
2 siblings, 0 replies; 4+ messages in thread
From: Kieran Bingham @ 2021-06-22 23:42 UTC (permalink / raw
To: Geert Uytterhoeven, Kieran Bingham
Cc: Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring,
open list:ARM/RENESAS ARM64 ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Provide the two MIPI DSI encoders on the V3U and connect them to the DU
accordingly.
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
---
arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 60 +++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index 24476886e498..54f10a7e6b89 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -1162,12 +1162,72 @@ ports {
port@0 {
reg = <0>;
du_out_dsi0: endpoint {
+ remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
du_out_dsi1: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi-encoder@fed80000 {
+ compatible = "renesas,r8a779a0-dsi-csi2-tx";
+ reg = <0 0xfed80000 0 0x10000>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ clocks = <&cpg CPG_MOD 415>,
+ <&cpg CPG_CORE R8A779A0_CLK_DSI>;
+ clock-names = "fck", "dsi";
+ resets = <&cpg 415>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&du_out_dsi0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi1: dsi-encoder@fed90000 {
+ compatible = "renesas,r8a779a0-dsi-csi2-tx";
+ reg = <0 0xfed90000 0 0x10000>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ clocks = <&cpg CPG_MOD 416>,
+ <&cpg CPG_CORE R8A779A0_CLK_DSI>;
+ clock-names = "fck", "dsi";
+ resets = <&cpg 416>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi1_in: endpoint {
+ remote-endpoint = <&du_out_dsi1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi1_out: endpoint {
};
};
};
--
2.30.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 3/3] arm64: dts: renesas: falcon-cpu: Add DSI display output
[not found] <20210622234257.3228634-1-kieran.bingham@ideasonboard.com>
2021-06-22 23:42 ` [PATCH 1/3] arm64: dts: renesas: r8a779a0: Add DU support Kieran Bingham
2021-06-22 23:42 ` [PATCH 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders Kieran Bingham
@ 2021-06-22 23:42 ` Kieran Bingham
2 siblings, 0 replies; 4+ messages in thread
From: Kieran Bingham @ 2021-06-22 23:42 UTC (permalink / raw
To: Geert Uytterhoeven, Kieran Bingham
Cc: Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring,
open list:ARM/RENESAS ARM64 ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Provide the display output using the sn65dsi86 MIPI DSI bridge.
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
---
.../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
index a0a1a1da0d87..5530bb82de6b 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
@@ -66,6 +66,15 @@ memory@700000000 {
reg = <0x7 0x00000000 0x0 0x80000000>;
};
+ reg_1p2v: regulator-1p2v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.2V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
@@ -83,6 +92,46 @@ reg_3p3v: regulator-3p3v {
regulator-boot-on;
regulator-always-on;
};
+
+ mini-dp-con {
+ compatible = "dp-connector";
+ label = "CN5";
+ type = "mini";
+
+ port {
+ mini_dp_con_in: endpoint {
+ remote-endpoint = <&sn65dsi86_out>;
+ };
+ };
+ };
+
+ sn65dsi86_refclk: sn65dsi86-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <38400000>;
+ };
+};
+
+&dsi0 {
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 415>,
+ <&cpg CPG_CORE R8A779A0_CLK_DSI>,
+ <&extal_clk>;
+ clock-names = "fck", "dsi", "extal";
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <&sn65dsi86_in>;
+ data-lanes = <1 2 3 4>;
+ };
+ };
+ };
+};
+
+&du {
+ status = "okay";
};
&extal_clk {
@@ -114,6 +163,41 @@ &i2c1 {
status = "okay";
clock-frequency = <400000>;
+
+ sn65dsi86@2c {
+ compatible = "ti,sn65dsi86";
+ reg = <0x2c>;
+
+ clocks = <&sn65dsi86_refclk>;
+ clock-names = "refclk";
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+
+ vccio-supply = <®_1p8v>;
+ vpll-supply = <®_1p8v>;
+ vcca-supply = <®_1p2v>;
+ vcc-supply = <®_1p2v>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ sn65dsi86_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ sn65dsi86_out: endpoint {
+ remote-endpoint = <&mini_dp_con_in>;
+ };
+ };
+ };
+ };
};
&i2c6 {
--
2.30.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/3] arm64: dts: renesas: r8a779a0: Add DU support
2021-06-22 23:42 ` [PATCH 1/3] arm64: dts: renesas: r8a779a0: Add DU support Kieran Bingham
@ 2021-06-23 13:00 ` Geert Uytterhoeven
0 siblings, 0 replies; 4+ messages in thread
From: Geert Uytterhoeven @ 2021-06-23 13:00 UTC (permalink / raw
To: Kieran Bingham
Cc: Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring,
open list:ARM/RENESAS ARM64 ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
Hi Kieran,
On Wed, Jun 23, 2021 at 1:43 AM Kieran Bingham
<kieran.bingham@ideasonboard.com> wrote:
> From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
>
> Provide the device nodes for the DU on the V3U platforms.
>
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> @@ -1142,6 +1142,37 @@ vspd1: vsp@fea28000 {
> renesas,fcp = <&fcpvd1>;
> };
>
> + du: display@feb00000 {
> + compatible = "renesas,du-r8a779a0";
> + reg = <0 0xfeb00000 0 0x40000>;
> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 411>,
> + <&cpg CPG_MOD 411>;
> + clock-names = "du.0", "du.1";
> + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> + resets = <&cpg 411>;
> + vsps = <&vspd0 0>, <&vspd1 0>;
> + status = "disabled";
Modulo my comments on the clock part of the bindings:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 4+ messages in thread
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[not found] <20210622234257.3228634-1-kieran.bingham@ideasonboard.com>
2021-06-22 23:42 ` [PATCH 1/3] arm64: dts: renesas: r8a779a0: Add DU support Kieran Bingham
2021-06-23 13:00 ` Geert Uytterhoeven
2021-06-22 23:42 ` [PATCH 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders Kieran Bingham
2021-06-22 23:42 ` [PATCH 3/3] arm64: dts: renesas: falcon-cpu: Add DSI display output Kieran Bingham
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