* [PATCH 0/5] Add support for Texas Instruments MCRC64 engine
@ 2023-07-30 18:55 Kamlesh Gurudasani
2023-07-30 18:55 ` [PATCH 1/5] crypto: crc64 - add crc64-iso test vectors Kamlesh Gurudasani
` (5 more replies)
0 siblings, 6 replies; 14+ messages in thread
From: Kamlesh Gurudasani @ 2023-07-30 18:55 UTC (permalink / raw
To: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Catalin Marinas, Will Deacon
Cc: linux-crypto, linux-kernel, devicetree, linux-arm-kernel,
Kamlesh Gurudasani
Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode
MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
according to the ISO 3309 standard.
Generator polynomial: x^64 + x^4 + x^3 + x + 1
Polynomial value: 0x000000000000001b
Tested with
and tcrypt,
sudo modprobe tcrypt mode=329 sec=1
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
---
Kamlesh Gurudasani (5):
crypto: crc64 - add crc64-iso test vectors
dt-bindings: crypto: Add binding for TI MCRC64 driver
crypto: ti - add driver for MCRC64 engine
arm64: dts: ti: k3-am62: Add dt node, cbass_main ranges for MCRC64
arm64: defconfig: enable MCRC module
Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml | 42 +++++++
MAINTAINERS | 7 ++
arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 7 ++
arch/arm64/boot/dts/ti/k3-am62.dtsi | 1 +
arch/arm64/configs/defconfig | 2 +
crypto/tcrypt.c | 5 +
crypto/testmgr.c | 7 ++
crypto/testmgr.h | 401 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/crypto/Kconfig | 1 +
drivers/crypto/Makefile | 1 +
drivers/crypto/ti/Kconfig | 10 ++
drivers/crypto/ti/Makefile | 2 +
drivers/crypto/ti/mcrc64.c | 360 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
13 files changed, 846 insertions(+)
---
base-commit: d7b3af5a77e8d8da28f435f313e069aea5bcf172
change-id: 20230719-mcrc-upstream-7ae9a75cab37
Best regards,
--
Kamlesh Gurudasani <kamlesh@ti.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/5] crypto: crc64 - add crc64-iso test vectors
2023-07-30 18:55 [PATCH 0/5] Add support for Texas Instruments MCRC64 engine Kamlesh Gurudasani
@ 2023-07-30 18:55 ` Kamlesh Gurudasani
2023-07-30 18:55 ` [PATCH 2/5] dt-bindings: crypto: Add binding for TI MCRC64 driver Kamlesh Gurudasani
` (4 subsequent siblings)
5 siblings, 0 replies; 14+ messages in thread
From: Kamlesh Gurudasani @ 2023-07-30 18:55 UTC (permalink / raw
To: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Catalin Marinas, Will Deacon
Cc: linux-crypto, linux-kernel, devicetree, linux-arm-kernel,
Kamlesh Gurudasani
Add testmgr, tcrypt tests and vectors for 64-bit cyclic
redundancy checks (CRC) according to the ISO 3309 standard.
Generator polynomial: x^64 + x^4 + x^3 + x + 1
Polynomial value: 0x000000000000001b
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
---
crypto/tcrypt.c | 5 ++
crypto/testmgr.c | 7 ++
crypto/testmgr.h | 401 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 413 insertions(+)
diff --git a/crypto/tcrypt.c b/crypto/tcrypt.c
index 202ca1a3105d..a41d52a879d6 100644
--- a/crypto/tcrypt.c
+++ b/crypto/tcrypt.c
@@ -2327,6 +2327,11 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb)
generic_hash_speed_template);
if (mode > 300 && mode < 400) break;
fallthrough;
+ case 329:
+ test_hash_speed("crc64-iso", sec, generic_hash_speed_template);
+ if (mode > 300 && mode < 400)
+ break;
+ fallthrough;
case 399:
break;
diff --git a/crypto/testmgr.c b/crypto/testmgr.c
index 216878c8bc3d..bd0414b99287 100644
--- a/crypto/testmgr.c
+++ b/crypto/testmgr.c
@@ -4679,6 +4679,13 @@ static const struct alg_test_desc alg_test_descs[] = {
.suite = {
.hash = __VECS(crc32c_tv_template)
}
+ }, {
+ .alg = "crc64-iso",
+ .test = alg_test_hash,
+ .fips_allowed = 1,
+ .suite = {
+ .hash = __VECS(crc64_iso_tv_template)
+ }
}, {
.alg = "crc64-rocksoft",
.test = alg_test_hash,
diff --git a/crypto/testmgr.h b/crypto/testmgr.h
index 5ca7a412508f..54d0b03e3228 100644
--- a/crypto/testmgr.h
+++ b/crypto/testmgr.h
@@ -5209,6 +5209,407 @@ static const struct hash_testvec rmd160_tv_template[] = {
}
};
+static const struct hash_testvec crc64_iso_tv_template[] = {
+ {
+ .plaintext = "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .psize = 8,
+ .digest = "\x00\x00\x00\x00\x00\x00\x00\x00",
+ },
+ {
+ .plaintext = "\x01\x02\x03\x04\x05\x06\x07\x08"
+ "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10"
+ "\x11\x12\x13\x14\x15\x16\x17\x18"
+ "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20"
+ "\x21\x22\x23\x24\x25\x26\x27\x28",
+ .psize = 40,
+ .digest = "\xaf\x45\xba\x7d\xf2\xda\xa0\xaa",
+ },
+ {
+ .plaintext = "\x29\x2a\x2b\x2c\x2d\x2e\x2f\x30"
+ "\x31\x32\x33\x34\x35\x36\x37\x38"
+ "\x39\x3a\x3b\x3c\x3d\x3e\x3f\x40"
+ "\x41\x42\x43\x44\x45\x46\x47\x48"
+ "\x49\x4a\x4b\x4c\x4d\x4e\x4f\x50",
+ .psize = 40,
+ .digest = "\x81\x55\x2e\x76\xf8\xd0\xaa\xa0",
+ },
+ {
+ .plaintext = "\x51\x52\x53\x54\x55\x56\x57\x58"
+ "\x59\x5a\x5b\x5c\x5d\x5e\x5f\x60"
+ "\x61\x62\x63\x64\x65\x66\x67\x68"
+ "\x69\x6a\x6b\x6c\x6d\x6e\x6f\x70"
+ "\x71\x72\x73\x74\x75\x76\x77\x78",
+ .psize = 40,
+ .digest = "\xc6\xb6\x26\x82\x0d\x25\x5f\x55",
+ },
+ {
+ .plaintext = "\x79\x7a\x7b\x7c\x7d\x7e\x7f\x80"
+ "\x81\x82\x83\x84\x85\x86\x87\x88"
+ "\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90"
+ "\x91\x92\x93\x94\x95\x96\x97\x98"
+ "\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0",
+ .psize = 40,
+ .digest = "\x20\x8a\xe6\x59\xdf\xf7\x8d\x87",
+ },
+ {
+ .plaintext = "\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8"
+ "\xa9\xaa\xab\xac\xad\xae\xaf\xb0"
+ "\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8"
+ "\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0"
+ "\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8",
+ .psize = 40,
+ .digest = "\x19\x9e\xba\xff\x70\x58\x22\x28",
+
+ },
+ {
+ .plaintext = "\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0"
+ "\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8"
+ "\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0"
+ "\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8"
+ "\xe9\xea\xeb\xec\xed\xee\xef\xf0",
+ .psize = 40,
+ .digest = "\xa3\xdc\x11\x98\x16\x3e\x44\x4e",
+ },
+ {
+ .plaintext = "\x29\x2a\x2b\x2c\x2d\x2e\x2f\x30"
+ "\x31\x32\x33\x34\x35\x36\x37\x38"
+ "\x39\x3a\x3b\x3c\x3d\x3e\x3f\x40"
+ "\x41\x42\x43\x44\x45\x46\x47\x48"
+ "\x49\x4a\x4b\x4c\x4d\x4e\x4f\x50",
+ .psize = 40,
+ .digest = "\x81\x55\x2e\x76\xf8\xd0\xaa\xa0",
+ },
+ {
+ .plaintext = "\x51\x52\x53\x54\x55\x56\x57\x58"
+ "\x59\x5a\x5b\x5c\x5d\x5e\x5f\x60"
+ "\x61\x62\x63\x64\x65\x66\x67\x68"
+ "\x69\x6a\x6b\x6c\x6d\x6e\x6f\x70"
+ "\x71\x72\x73\x74\x75\x76\x77\x78",
+ .psize = 40,
+ .digest = "\xc6\xb6\x26\x82\x0d\x25\x5f\x55",
+ },
+ {
+ .plaintext = "\x79\x7a\x7b\x7c\x7d\x7e\x7f\x80"
+ "\x81\x82\x83\x84\x85\x86\x87\x88"
+ "\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90"
+ "\x91\x92\x93\x94\x95\x96\x97\x98"
+ "\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0",
+ .psize = 40,
+ .digest = "\x20\x8a\xe6\x59\xdf\xf7\x8d\x87",
+ },
+ {
+ .plaintext = "\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8"
+ "\xa9\xaa\xab\xac\xad\xae\xaf\xb0"
+ "\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8"
+ "\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0"
+ "\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8",
+ .psize = 40,
+ .digest = "\x19\x9e\xba\xff\x70\x58\x22\x28",
+ },
+ {
+ .plaintext = "\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0"
+ "\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8"
+ "\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0"
+ "\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8"
+ "\xe9\xea\xeb\xec\xed\xee\xef\xf0",
+ .psize = 40,
+ .digest = "\xa3\xdc\x11\x98\x16\x3e\x44\x4e",
+ },
+ {
+ .plaintext = "\x01\x02\x03\x04\x05\x06\x07\x08"
+ "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10"
+ "\x11\x12\x13\x14\x15\x16\x17\x18"
+ "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20"
+ "\x21\x22\x23\x24\x25\x26\x27\x28"
+ "\x29\x2a\x2b\x2c\x2d\x2e\x2f\x30"
+ "\x31\x32\x33\x34\x35\x36\x37\x38"
+ "\x39\x3a\x3b\x3c\x3d\x3e\x3f\x40"
+ "\x41\x42\x43\x44\x45\x46\x47\x48"
+ "\x49\x4a\x4b\x4c\x4d\x4e\x4f\x50"
+ "\x51\x52\x53\x54\x55\x56\x57\x58"
+ "\x59\x5a\x5b\x5c\x5d\x5e\x5f\x60"
+ "\x61\x62\x63\x64\x65\x66\x67\x68"
+ "\x69\x6a\x6b\x6c\x6d\x6e\x6f\x70"
+ "\x71\x72\x73\x74\x75\x76\x77\x78"
+ "\x79\x7a\x7b\x7c\x7d\x7e\x7f\x80"
+ "\x81\x82\x83\x84\x85\x86\x87\x88"
+ "\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90"
+ "\x91\x92\x93\x94\x95\x96\x97\x98"
+ "\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0"
+ "\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8"
+ "\xa9\xaa\xab\xac\xad\xae\xaf\xb0"
+ "\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8"
+ "\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0"
+ "\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8"
+ "\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0"
+ "\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8"
+ "\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0"
+ "\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8"
+ "\xe9\xea\xeb\xec\xed\xee\xef\xf0",
+ .psize = 240,
+ .digest = "\x19\x0f\xb1\x04\x11\x22\xfc\x21",
+ }, {
+ .plaintext = "\x6e\x05\x79\x10\xa7\x1b\xb2\x49"
+ "\xe0\x54\xeb\x82\x19\x8d\x24\xbb"
+ "\x2f\xc6\x5d\xf4\x68\xff\x96\x0a"
+ "\xa1\x38\xcf\x43\xda\x71\x08\x7c"
+ "\x13\xaa\x1e\xb5\x4c\xe3\x57\xee"
+ "\x85\x1c\x90\x27\xbe\x32\xc9\x60"
+ "\xf7\x6b\x02\x99\x0d\xa4\x3b\xd2"
+ "\x46\xdd\x74\x0b\x7f\x16\xad\x21"
+ "\xb8\x4f\xe6\x5a\xf1\x88\x1f\x93"
+ "\x2a\xc1\x35\xcc\x63\xfa\x6e\x05"
+ "\x9c\x10\xa7\x3e\xd5\x49\xe0\x77"
+ "\x0e\x82\x19\xb0\x24\xbb\x52\xe9"
+ "\x5d\xf4\x8b\x22\x96\x2d\xc4\x38"
+ "\xcf\x66\xfd\x71\x08\x9f\x13\xaa"
+ "\x41\xd8\x4c\xe3\x7a\x11\x85\x1c"
+ "\xb3\x27\xbe\x55\xec\x60\xf7\x8e"
+ "\x02\x99\x30\xc7\x3b\xd2\x69\x00"
+ "\x74\x0b\xa2\x16\xad\x44\xdb\x4f"
+ "\xe6\x7d\x14\x88\x1f\xb6\x2a\xc1"
+ "\x58\xef\x63\xfa\x91\x05\x9c\x33"
+ "\xca\x3e\xd5\x6c\x03\x77\x0e\xa5"
+ "\x19\xb0\x47\xde\x52\xe9\x80\x17"
+ "\x8b\x22\xb9\x2d\xc4\x5b\xf2\x66"
+ "\xfd\x94\x08\x9f\x36\xcd\x41\xd8"
+ "\x6f\x06\x7a\x11\xa8\x1c\xb3\x4a"
+ "\xe1\x55\xec\x83\x1a\x8e\x25\xbc"
+ "\x30\xc7\x5e\xf5\x69\x00\x97\x0b"
+ "\xa2\x39\xd0\x44\xdb\x72\x09\x7d"
+ "\x14\xab\x1f\xb6\x4d\xe4\x58\xef"
+ "\x86\x1d\x91\x28\xbf\x33\xca\x61"
+ "\xf8\x6c\x03\x9a\x0e\xa5\x3c\xd3"
+ "\x47\xde\x75\x0c\x80\x17\xae\x22"
+ "\xb9\x50\xe7\x5b\xf2\x89\x20\x94"
+ "\x2b\xc2\x36\xcd\x64\xfb\x6f\x06"
+ "\x9d\x11\xa8\x3f\xd6\x4a\xe1\x78"
+ "\x0f\x83\x1a\xb1\x25\xbc\x53\xea"
+ "\x5e\xf5\x8c\x00\x97\x2e\xc5\x39"
+ "\xd0\x67\xfe\x72\x09\xa0\x14\xab"
+ "\x42\xd9\x4d\xe4\x7b\x12\x86\x1d"
+ "\xb4\x28\xbf\x56\xed\x61\xf8\x8f"
+ "\x03\x9a\x31\xc8\x3c\xd3\x6a\x01"
+ "\x75\x0c\xa3\x17\xae\x45\xdc\x50"
+ "\xe7\x7e\x15\x89\x20\xb7\x2b\xc2"
+ "\x59\xf0\x64\xfb\x92\x06\x9d\x34"
+ "\xcb\x3f\xd6\x6d\x04\x78\x0f\xa6"
+ "\x1a\xb1\x48\xdf\x53\xea\x81\x18"
+ "\x8c\x23\xba\x2e\xc5\x5c\xf3\x67"
+ "\xfe\x95\x09\xa0\x37\xce\x42\xd9"
+ "\x70\x07\x7b\x12\xa9\x1d\xb4\x4b"
+ "\xe2\x56\xed\x84\x1b\x8f\x26\xbd"
+ "\x31\xc8\x5f\xf6\x6a\x01\x98\x0c"
+ "\xa3\x3a\xd1\x45\xdc\x73\x0a\x7e"
+ "\x15\xac\x20\xb7\x4e\xe5\x59\xf0"
+ "\x87\x1e\x92\x29\xc0\x34\xcb\x62"
+ "\xf9\x6d\x04\x9b\x0f\xa6\x3d\xd4"
+ "\x48\xdf\x76\x0d\x81\x18\xaf\x23"
+ "\xba\x51\xe8\x5c\xf3\x8a\x21\x95"
+ "\x2c\xc3\x37\xce\x65\xfc\x70\x07"
+ "\x9e\x12\xa9\x40\xd7\x4b\xe2\x79"
+ "\x10\x84\x1b\xb2\x26\xbd\x54\xeb"
+ "\x5f\xf6\x8d\x01\x98\x2f\xc6\x3a"
+ "\xd1\x68\xff\x73\x0a\xa1\x15\xac"
+ "\x43\xda\x4e\xe5\x7c\x13\x87\x1e"
+ "\xb5\x29\xc0\x57\xee\x62\xf9\x90"
+ "\x04\x9b\x32\xc9\x3d\xd4\x6b\x02"
+ "\x76\x0d\xa4\x18\xaf\x46\xdd\x51"
+ "\xe8\x7f\x16\x8a\x21\xb8\x2c\xc3"
+ "\x5a\xf1\x65\xfc\x93\x07\x9e\x35"
+ "\xcc\x40\xd7\x6e\x05\x79\x10\xa7"
+ "\x1b\xb2\x49\xe0\x54\xeb\x82\x19"
+ "\x8d\x24\xbb\x2f\xc6\x5d\xf4\x68"
+ "\xff\x96\x0a\xa1\x38\xcf\x43\xda"
+ "\x71\x08\x7c\x13\xaa\x1e\xb5\x4c"
+ "\xe3\x57\xee\x85\x1c\x90\x27\xbe"
+ "\x32\xc9\x60\xf7\x6b\x02\x99\x0d"
+ "\xa4\x3b\xd2\x46\xdd\x74\x0b\x7f"
+ "\x16\xad\x21\xb8\x4f\xe6\x5a\xf1"
+ "\x88\x1f\x93\x2a\xc1\x35\xcc\x63"
+ "\xfa\x6e\x05\x9c\x10\xa7\x3e\xd5"
+ "\x49\xe0\x77\x0e\x82\x19\xb0\x24"
+ "\xbb\x52\xe9\x5d\xf4\x8b\x22\x96"
+ "\x2d\xc4\x38\xcf\x66\xfd\x71\x08"
+ "\x9f\x13\xaa\x41\xd8\x4c\xe3\x7a"
+ "\x11\x85\x1c\xb3\x27\xbe\x55\xec"
+ "\x60\xf7\x8e\x02\x99\x30\xc7\x3b"
+ "\xd2\x69\x00\x74\x0b\xa2\x16\xad"
+ "\x44\xdb\x4f\xe6\x7d\x14\x88\x1f"
+ "\xb6\x2a\xc1\x58\xef\x63\xfa\x91"
+ "\x05\x9c\x33\xca\x3e\xd5\x6c\x03"
+ "\x77\x0e\xa5\x19\xb0\x47\xde\x52"
+ "\xe9\x80\x17\x8b\x22\xb9\x2d\xc4"
+ "\x5b\xf2\x66\xfd\x94\x08\x9f\x36"
+ "\xcd\x41\xd8\x6f\x06\x7a\x11\xa8"
+ "\x1c\xb3\x4a\xe1\x55\xec\x83\x1a"
+ "\x8e\x25\xbc\x30\xc7\x5e\xf5\x69"
+ "\x00\x97\x0b\xa2\x39\xd0\x44\xdb"
+ "\x72\x09\x7d\x14\xab\x1f\xb6\x4d"
+ "\xe4\x58\xef\x86\x1d\x91\x28\xbf"
+ "\x33\xca\x61\xf8\x6c\x03\x9a\x0e"
+ "\xa5\x3c\xd3\x47\xde\x75\x0c\x80"
+ "\x17\xae\x22\xb9\x50\xe7\x5b\xf2"
+ "\x89\x20\x94\x2b\xc2\x36\xcd\x64"
+ "\xfb\x6f\x06\x9d\x11\xa8\x3f\xd6"
+ "\x4a\xe1\x78\x0f\x83\x1a\xb1\x25"
+ "\xbc\x53\xea\x5e\xf5\x8c\x00\x97"
+ "\x2e\xc5\x39\xd0\x67\xfe\x72\x09"
+ "\xa0\x14\xab\x42\xd9\x4d\xe4\x7b"
+ "\x12\x86\x1d\xb4\x28\xbf\x56\xed"
+ "\x61\xf8\x8f\x03\x9a\x31\xc8\x3c"
+ "\xd3\x6a\x01\x75\x0c\xa3\x17\xae"
+ "\x45\xdc\x50\xe7\x7e\x15\x89\x20"
+ "\xb7\x2b\xc2\x59\xf0\x64\xfb\x92"
+ "\x06\x9d\x34\xcb\x3f\xd6\x6d\x04"
+ "\x78\x0f\xa6\x1a\xb1\x48\xdf\x53"
+ "\xea\x81\x18\x8c\x23\xba\x2e\xc5"
+ "\x5c\xf3\x67\xfe\x95\x09\xa0\x37"
+ "\xce\x42\xd9\x70\x07\x7b\x12\xa9"
+ "\x1d\xb4\x4b\xe2\x56\xed\x84\x1b"
+ "\x8f\x26\xbd\x31\xc8\x5f\xf6\x6a"
+ "\x01\x98\x0c\xa3\x3a\xd1\x45\xdc"
+ "\x73\x0a\x7e\x15\xac\x20\xb7\x4e"
+ "\xe5\x59\xf0\x87\x1e\x92\x29\xc0"
+ "\x34\xcb\x62\xf9\x6d\x04\x9b\x0f"
+ "\xa6\x3d\xd4\x48\xdf\x76\x0d\x81"
+ "\x18\xaf\x23\xba\x51\xe8\x5c\xf3"
+ "\x8a\x21\x95\x2c\xc3\x37\xce\x65"
+ "\xfc\x70\x07\x9e\x12\xa9\x40\xd7"
+ "\x4b\xe2\x79\x10\x84\x1b\xb2\x26"
+ "\xbd\x54\xeb\x5f\xf6\x8d\x01\x98"
+ "\x2f\xc6\x3a\xd1\x68\xff\x73\x0a"
+ "\xa1\x15\xac\x43\xda\x4e\xe5\x7c"
+ "\x13\x87\x1e\xb5\x29\xc0\x57\xee"
+ "\x62\xf9\x90\x04\x9b\x32\xc9\x3d"
+ "\xd4\x6b\x02\x76\x0d\xa4\x18\xaf"
+ "\x46\xdd\x51\xe8\x7f\x16\x8a\x21"
+ "\xb8\x2c\xc3\x5a\xf1\x65\xfc\x93"
+ "\x07\x9e\x35\xcc\x40\xd7\x6e\x05"
+ "\x79\x10\xa7\x1b\xb2\x49\xe0\x54"
+ "\xeb\x82\x19\x8d\x24\xbb\x2f\xc6"
+ "\x5d\xf4\x68\xff\x96\x0a\xa1\x38"
+ "\xcf\x43\xda\x71\x08\x7c\x13\xaa"
+ "\x1e\xb5\x4c\xe3\x57\xee\x85\x1c"
+ "\x90\x27\xbe\x32\xc9\x60\xf7\x6b"
+ "\x02\x99\x0d\xa4\x3b\xd2\x46\xdd"
+ "\x74\x0b\x7f\x16\xad\x21\xb8\x4f"
+ "\xe6\x5a\xf1\x88\x1f\x93\x2a\xc1"
+ "\x35\xcc\x63\xfa\x6e\x05\x9c\x10"
+ "\xa7\x3e\xd5\x49\xe0\x77\x0e\x82"
+ "\x19\xb0\x24\xbb\x52\xe9\x5d\xf4"
+ "\x8b\x22\x96\x2d\xc4\x38\xcf\x66"
+ "\xfd\x71\x08\x9f\x13\xaa\x41\xd8"
+ "\x4c\xe3\x7a\x11\x85\x1c\xb3\x27"
+ "\xbe\x55\xec\x60\xf7\x8e\x02\x99"
+ "\x30\xc7\x3b\xd2\x69\x00\x74\x0b"
+ "\xa2\x16\xad\x44\xdb\x4f\xe6\x7d"
+ "\x14\x88\x1f\xb6\x2a\xc1\x58\xef"
+ "\x63\xfa\x91\x05\x9c\x33\xca\x3e"
+ "\xd5\x6c\x03\x77\x0e\xa5\x19\xb0"
+ "\x47\xde\x52\xe9\x80\x17\x8b\x22"
+ "\xb9\x2d\xc4\x5b\xf2\x66\xfd\x94"
+ "\x08\x9f\x36\xcd\x41\xd8\x6f\x06"
+ "\x7a\x11\xa8\x1c\xb3\x4a\xe1\x55"
+ "\xec\x83\x1a\x8e\x25\xbc\x30\xc7"
+ "\x5e\xf5\x69\x00\x97\x0b\xa2\x39"
+ "\xd0\x44\xdb\x72\x09\x7d\x14\xab"
+ "\x1f\xb6\x4d\xe4\x58\xef\x86\x1d"
+ "\x91\x28\xbf\x33\xca\x61\xf8\x6c"
+ "\x03\x9a\x0e\xa5\x3c\xd3\x47\xde"
+ "\x75\x0c\x80\x17\xae\x22\xb9\x50"
+ "\xe7\x5b\xf2\x89\x20\x94\x2b\xc2"
+ "\x36\xcd\x64\xfb\x6f\x06\x9d\x11"
+ "\xa8\x3f\xd6\x4a\xe1\x78\x0f\x83"
+ "\x1a\xb1\x25\xbc\x53\xea\x5e\xf5"
+ "\x8c\x00\x97\x2e\xc5\x39\xd0\x67"
+ "\xfe\x72\x09\xa0\x14\xab\x42\xd9"
+ "\x4d\xe4\x7b\x12\x86\x1d\xb4\x28"
+ "\xbf\x56\xed\x61\xf8\x8f\x03\x9a"
+ "\x31\xc8\x3c\xd3\x6a\x01\x75\x0c"
+ "\xa3\x17\xae\x45\xdc\x50\xe7\x7e"
+ "\x15\x89\x20\xb7\x2b\xc2\x59\xf0"
+ "\x64\xfb\x92\x06\x9d\x34\xcb\x3f"
+ "\xd6\x6d\x04\x78\x0f\xa6\x1a\xb1"
+ "\x48\xdf\x53\xea\x81\x18\x8c\x23"
+ "\xba\x2e\xc5\x5c\xf3\x67\xfe\x95"
+ "\x09\xa0\x37\xce\x42\xd9\x70\x07"
+ "\x7b\x12\xa9\x1d\xb4\x4b\xe2\x56"
+ "\xed\x84\x1b\x8f\x26\xbd\x31\xc8"
+ "\x5f\xf6\x6a\x01\x98\x0c\xa3\x3a"
+ "\xd1\x45\xdc\x73\x0a\x7e\x15\xac"
+ "\x20\xb7\x4e\xe5\x59\xf0\x87\x1e"
+ "\x92\x29\xc0\x34\xcb\x62\xf9\x6d"
+ "\x04\x9b\x0f\xa6\x3d\xd4\x48\xdf"
+ "\x76\x0d\x81\x18\xaf\x23\xba\x51"
+ "\xe8\x5c\xf3\x8a\x21\x95\x2c\xc3"
+ "\x37\xce\x65\xfc\x70\x07\x9e\x12"
+ "\xa9\x40\xd7\x4b\xe2\x79\x10\x84"
+ "\x1b\xb2\x26\xbd\x54\xeb\x5f\xf6"
+ "\x8d\x01\x98\x2f\xc6\x3a\xd1\x68"
+ "\xff\x73\x0a\xa1\x15\xac\x43\xda"
+ "\x4e\xe5\x7c\x13\x87\x1e\xb5\x29"
+ "\xc0\x57\xee\x62\xf9\x90\x04\x9b"
+ "\x32\xc9\x3d\xd4\x6b\x02\x76\x0d"
+ "\xa4\x18\xaf\x46\xdd\x51\xe8\x7f"
+ "\x16\x8a\x21\xb8\x2c\xc3\x5a\xf1"
+ "\x65\xfc\x93\x07\x9e\x35\xcc\x40"
+ "\xd7\x6e\x05\x79\x10\xa7\x1b\xb2"
+ "\x49\xe0\x54\xeb\x82\x19\x8d\x24"
+ "\xbb\x2f\xc6\x5d\xf4\x68\xff\x96"
+ "\x0a\xa1\x38\xcf\x43\xda\x71\x08"
+ "\x7c\x13\xaa\x1e\xb5\x4c\xe3\x57"
+ "\xee\x85\x1c\x90\x27\xbe\x32\xc9"
+ "\x60\xf7\x6b\x02\x99\x0d\xa4\x3b"
+ "\xd2\x46\xdd\x74\x0b\x7f\x16\xad"
+ "\x21\xb8\x4f\xe6\x5a\xf1\x88\x1f"
+ "\x93\x2a\xc1\x35\xcc\x63\xfa\x6e"
+ "\x05\x9c\x10\xa7\x3e\xd5\x49\xe0"
+ "\x77\x0e\x82\x19\xb0\x24\xbb\x52"
+ "\xe9\x5d\xf4\x8b\x22\x96\x2d\xc4"
+ "\x38\xcf\x66\xfd\x71\x08\x9f\x13"
+ "\xaa\x41\xd8\x4c\xe3\x7a\x11\x85"
+ "\x1c\xb3\x27\xbe\x55\xec\x60\xf7"
+ "\x8e\x02\x99\x30\xc7\x3b\xd2\x69"
+ "\x00\x74\x0b\xa2\x16\xad\x44\xdb"
+ "\x4f\xe6\x7d\x14\x88\x1f\xb6\x2a"
+ "\xc1\x58\xef\x63\xfa\x91\x05\x9c"
+ "\x33\xca\x3e\xd5\x6c\x03\x77\x0e"
+ "\xa5\x19\xb0\x47\xde\x52\xe9\x80"
+ "\x17\x8b\x22\xb9\x2d\xc4\x5b\xf2"
+ "\x66\xfd\x94\x08\x9f\x36\xcd\x41"
+ "\xd8\x6f\x06\x7a\x11\xa8\x1c\xb3"
+ "\x4a\xe1\x55\xec\x83\x1a\x8e\x25"
+ "\xbc\x30\xc7\x5e\xf5\x69\x00\x97"
+ "\x0b\xa2\x39\xd0\x44\xdb\x72\x09"
+ "\x7d\x14\xab\x1f\xb6\x4d\xe4\x58"
+ "\xef\x86\x1d\x91\x28\xbf\x33\xca"
+ "\x61\xf8\x6c\x03\x9a\x0e\xa5\x3c"
+ "\xd3\x47\xde\x75\x0c\x80\x17\xae"
+ "\x22\xb9\x50\xe7\x5b\xf2\x89\x20"
+ "\x94\x2b\xc2\x36\xcd\x64\xfb\x6f"
+ "\x06\x9d\x11\xa8\x3f\xd6\x4a\xe1"
+ "\x78\x0f\x83\x1a\xb1\x25\xbc\x53"
+ "\xea\x5e\xf5\x8c\x00\x97\x2e\xc5"
+ "\x39\xd0\x67\xfe\x72\x09\xa0\x14"
+ "\xab\x42\xd9\x4d\xe4\x7b\x12\x86"
+ "\x1d\xb4\x28\xbf\x56\xed\x61\xf8"
+ "\x8f\x03\x9a\x31\xc8\x3c\xd3\x6a"
+ "\x01\x75\x0c\xa3\x17\xae\x45\xdc"
+ "\x50\xe7\x7e\x15\x89\x20\xb7\x2b"
+ "\xc2\x59\xf0\x64\xfb\x92\x06\x9d"
+ "\x34\xcb\x3f\xd6\x6d\x04\x78\x0f"
+ "\xa6\x1a\xb1\x48\xdf\x53\xea\x81"
+ "\x18\x8c\x23\xba\x2e\xc5\x5c\xf3"
+ "\x67\xfe\x95\x09\xa0\x37\xce\x42"
+ "\xd9\x70\x07\x7b\x12\xa9\x1d\xb4"
+ "\x4b\xe2\x56\xed\x84\x1b\x8f\x26"
+ "\xbd\x31\xc8\x5f\xf6\x6a\x01\x98",
+ .psize = 2048,
+ .digest = "\x81\x14\x33\x6e\x7b\x97\x0b\xc6",
+ }
+};
+
static const u8 zeroes[4096] = { [0 ... 4095] = 0 };
static const u8 ones[4096] = { [0 ... 4095] = 0xff };
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/5] dt-bindings: crypto: Add binding for TI MCRC64 driver
2023-07-30 18:55 [PATCH 0/5] Add support for Texas Instruments MCRC64 engine Kamlesh Gurudasani
2023-07-30 18:55 ` [PATCH 1/5] crypto: crc64 - add crc64-iso test vectors Kamlesh Gurudasani
@ 2023-07-30 18:55 ` Kamlesh Gurudasani
2023-07-30 19:15 ` Krzysztof Kozlowski
2023-07-30 19:28 ` Rob Herring
2023-07-30 18:55 ` [PATCH 3/5] crypto: ti - add driver for MCRC64 engine Kamlesh Gurudasani
` (3 subsequent siblings)
5 siblings, 2 replies; 14+ messages in thread
From: Kamlesh Gurudasani @ 2023-07-30 18:55 UTC (permalink / raw
To: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Catalin Marinas, Will Deacon
Cc: linux-crypto, linux-kernel, devicetree, linux-arm-kernel,
Kamlesh Gurudasani
Add binding for Texas Instruments MCRC64 driver
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
---
Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml | 42 ++++++++++++++++++++++++++++++++++++++++++
MAINTAINERS | 5 +++++
2 files changed, 47 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml b/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml
new file mode 100644
index 000000000000..1d1e3f87638c
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/ti,mcrc64.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments MCRC64 bindings
+
+maintainers:
+ - Kamlesh Gurudasani <kamlesh@ti.com>
+
+properties:
+ compatible:
+ const: ti,mcrc64
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ mcrc64: mcrc64@30300000 {
+ compatible = "ti,mcrc64";
+ reg = <0x00 0x30300000 0x00 0x1000>;
+ clocks = <&k3_clks 116 0>;
+ power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 733bcfa0209a..d8680f6969e3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21462,6 +21462,11 @@ S: Maintained
F: Documentation/devicetree/bindings/iio/adc/ti,lmp92064.yaml
F: drivers/iio/adc/ti-lmp92064.c
+TI MEMORY CYCLIC REDUNDANCY CHECK (MCRC64) DRIVER
+M: Kamlesh Gurudasani <kamlesh@ti.com>
+S: Maintained
+F: Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml
+
TI PCM3060 ASoC CODEC DRIVER
M: Kirill Marinushkin <kmarinushkin@birdec.com>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/5] crypto: ti - add driver for MCRC64 engine
2023-07-30 18:55 [PATCH 0/5] Add support for Texas Instruments MCRC64 engine Kamlesh Gurudasani
2023-07-30 18:55 ` [PATCH 1/5] crypto: crc64 - add crc64-iso test vectors Kamlesh Gurudasani
2023-07-30 18:55 ` [PATCH 2/5] dt-bindings: crypto: Add binding for TI MCRC64 driver Kamlesh Gurudasani
@ 2023-07-30 18:55 ` Kamlesh Gurudasani
2023-07-30 19:18 ` Krzysztof Kozlowski
2023-07-31 17:50 ` Ard Biesheuvel
2023-07-30 18:55 ` [PATCH 4/5] arm64: dts: ti: k3-am62: Add dt node, cbass_main ranges for MCRC64 Kamlesh Gurudasani
` (2 subsequent siblings)
5 siblings, 2 replies; 14+ messages in thread
From: Kamlesh Gurudasani @ 2023-07-30 18:55 UTC (permalink / raw
To: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Catalin Marinas, Will Deacon
Cc: linux-crypto, linux-kernel, devicetree, linux-arm-kernel,
Kamlesh Gurudasani
Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode.
In Full-CPU mode, the CPU does the data patterns transfer and signature
verification all by itself, only CRC calculation is being done by MCRC64
engine.
MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
according to the ISO 3309 standard.
Generator polynomial: x^64 + x^4 + x^3 + x + 1
Polynomial value: 0x000000000000001b
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
---
MAINTAINERS | 2 +
drivers/crypto/Kconfig | 1 +
drivers/crypto/Makefile | 1 +
drivers/crypto/ti/Kconfig | 10 +++
drivers/crypto/ti/Makefile | 2 +
drivers/crypto/ti/mcrc64.c | 360 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
6 files changed, 376 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d8680f6969e3..a2f50adb51ac 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21464,8 +21464,10 @@ F: drivers/iio/adc/ti-lmp92064.c
TI MEMORY CYCLIC REDUNDANCY CHECK (MCRC64) DRIVER
M: Kamlesh Gurudasani <kamlesh@ti.com>
+L: linux-crypto@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml
+F: drivers/crypto/ti/mcrc64.c
TI PCM3060 ASoC CODEC DRIVER
M: Kirill Marinushkin <kmarinushkin@birdec.com>
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index c761952f0dc6..2101f92ead66 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -796,5 +796,6 @@ config CRYPTO_DEV_SA2UL
source "drivers/crypto/aspeed/Kconfig"
source "drivers/crypto/starfive/Kconfig"
+source "drivers/crypto/ti/Kconfig"
endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index d859d6a5f3a4..f1a151b73ff1 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
obj-$(CONFIG_CRYPTO_DEV_SL3516) += gemini/
obj-y += stm32/
obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
+obj-$(CONFIG_ARCH_K3) += ti/
obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/
obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
diff --git a/drivers/crypto/ti/Kconfig b/drivers/crypto/ti/Kconfig
new file mode 100644
index 000000000000..8e3b2b8b7623
--- /dev/null
+++ b/drivers/crypto/ti/Kconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config CRYPTO_DEV_TI_MCRC64
+ tristate "Support for TI MCRC64 crc64 accelerators"
+ depends on ARCH_K3
+ select CRYPTO_HASH
+ help
+ This enables support for the MCRC64 hw accelerator
+ which can be found on TI SOC.
+ MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
+ according to the ISO 3309 standard using Full-CPU mode.
\ No newline at end of file
diff --git a/drivers/crypto/ti/Makefile b/drivers/crypto/ti/Makefile
new file mode 100644
index 000000000000..94ffc2576137
--- /dev/null
+++ b/drivers/crypto/ti/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_CRYPTO_DEV_TI_MCRC64) += mcrc64.o
diff --git a/drivers/crypto/ti/mcrc64.c b/drivers/crypto/ti/mcrc64.c
new file mode 100644
index 000000000000..45f8ae6078ff
--- /dev/null
+++ b/drivers/crypto/ti/mcrc64.c
@@ -0,0 +1,360 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) Texas Instruments 2023 - http://www.ti.com
+ * Author: Kamlesh Gurudasani <kamlesh@ti.com>
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include <crypto/internal/hash.h>
+
+#include <asm/unaligned.h>
+
+#define DRIVER_NAME "mcrc64"
+#define CHKSUM_DIGEST_SIZE 8
+#define CHKSUM_BLOCK_SIZE 1
+
+/* Registers */
+#define CRC_CTRL0 0x0000 /* CRC Global Control Register 0 */
+#define CH_PSA_SWRE(ch) BIT(((ch) - 1) << 3) /* PSA Software Reset */
+
+#define CRC_CTRL1 0x0008 /* CRC Global Control Register 1 */
+#define PWDN BIT(0) /* Power Down */
+
+#define CRC_CTRL2 0x0010 /* CRC Global Control Register 2 */
+#define CH_MODE(ch, m) ((m) << (((ch) - 1) << 3))
+
+#define PSA_SIGREGL(ch) ((0x6 + (4 * ((ch) - 1))) << 4) /* Signature register */
+
+#define MCRC64_ALG_MASK 0x8000000000000000
+#define MCRC64_CRC64_POLY 0x000000000000001b
+
+#define MCRC64_AUTOSUSPEND_DELAY 50
+
+static struct device *mcrc64_k3_dev;
+
+enum mcrc64_mode {
+ MCRC64_MODE_DATA_CAPTURE = 0,
+ MCRC64_MODE_AUTO,
+ MCRC64_MODE_SEMI_CPU,
+ MCRC64_MODE_FULL_CPU,
+ MCRC64_MODE_INVALID,
+};
+
+enum mcrc64_channel {
+ MCRC64_CHANNEL_1 = 1,
+ MCRC64_CHANNEL_2,
+ MCRC64_CHANNEL_3,
+ MCRC64_CHANNEL_4,
+ MCRC64_CHANNEL_INVALID,
+};
+
+struct mcrc64_data {
+ struct device *dev;
+ void __iomem *regs;
+};
+
+struct mcrc64_ctx {
+ u32 key;
+};
+
+struct mcrc64_desc_ctx {
+ u64 signature;
+};
+
+static int mcrc64_set_mode(void __iomem *regs, u32 channel, u32 mode)
+{
+ u32 mode_set_val;
+ u32 crc_ctrl2_reg = 0;
+
+ if (mode < 0 || mode >= MCRC64_MODE_INVALID)
+ return -EINVAL;
+
+ if (channel <= 0 || channel >= MCRC64_CHANNEL_INVALID)
+ return -EINVAL;
+
+ mode_set_val = crc_ctrl2_reg | CH_MODE(channel, mode);
+
+ /* Write CRC_CTRL2, set mode */
+ writel_relaxed(mode_set_val, regs + CRC_CTRL2);
+
+ return 0;
+}
+
+static int mcrc64_reset_signature(void __iomem *regs, u32 channel)
+{
+ u32 crc_ctrl0_reg, reset_val, reset_undo_val;
+
+ if (channel <= 0 || channel >= MCRC64_CHANNEL_INVALID)
+ return -EINVAL;
+
+ /* reset PSA */
+ crc_ctrl0_reg = readl_relaxed(regs + CRC_CTRL0);
+
+ reset_val = crc_ctrl0_reg | CH_PSA_SWRE(channel);
+ reset_undo_val = crc_ctrl0_reg & ~CH_PSA_SWRE(channel);
+
+ /* Write CRC_CTRL0 register, reset PSA register */
+ writel_relaxed(reset_val, regs + CRC_CTRL0);
+ writel_relaxed(reset_undo_val, regs + CRC_CTRL0);
+
+ return 0;
+}
+
+/* This helper implements crc64 calculation using CPU */
+static u64 mcrc64_calculate_sw_crc(u64 crc, u8 byte)
+{
+ u64 bit = 0;
+ u8 j;
+
+ for (j = 0; j < 8; j++) {
+ bit = crc & MCRC64_ALG_MASK;
+ crc <<= 1;
+ if (byte & (0x80 >> j))
+ bit ^= MCRC64_ALG_MASK;
+ if (bit)
+ crc ^= MCRC64_CRC64_POLY;
+ }
+
+ return crc;
+}
+
+static int mcrc64_calculate_crc(void __iomem *regs, u32 channel,
+ const u8 *d8, size_t length, u64 *crc64)
+{
+ void __iomem *psa_reg;
+ u64 signature = 0;
+
+ if (channel <= 0 || channel >= MCRC64_CHANNEL_INVALID)
+ return -EINVAL;
+
+ psa_reg = regs + PSA_SIGREGL(channel);
+
+ for (; length >= sizeof(u64); d8 += sizeof(u64), length -= sizeof(u64))
+ writeq_relaxed(cpu_to_be64p((u64 *)d8), psa_reg);
+
+ signature = readq_relaxed(psa_reg);
+
+ if (length) {
+ while (length--)
+ signature = mcrc64_calculate_sw_crc(signature, *d8++);
+
+ /* set capture mode */
+ int ret = mcrc64_set_mode(regs, MCRC64_CHANNEL_1,
+ MCRC64_MODE_DATA_CAPTURE);
+ if (ret)
+ return ret;
+
+ ret = mcrc64_reset_signature(regs, MCRC64_CHANNEL_1);
+ if (ret)
+ return ret;
+
+ writeq_relaxed(signature, psa_reg);
+
+ ret = mcrc64_set_mode(regs, MCRC64_CHANNEL_1,
+ MCRC64_MODE_FULL_CPU);
+ if (ret)
+ return ret;
+ }
+
+ *crc64 = signature;
+
+ return 0;
+}
+
+static int mcrc64_cra_init(struct crypto_tfm *tfm)
+{
+ struct mcrc64_ctx *mctx = crypto_tfm_ctx(tfm);
+
+ struct mcrc64_data *dev_data = dev_get_drvdata(mcrc64_k3_dev);
+
+ pm_runtime_get_sync(dev_data->dev);
+
+ mctx->key = 0;
+
+ return 0;
+}
+
+static void mcrc64_cra_exit(struct crypto_tfm *tfm)
+{
+ struct mcrc64_data *dev_data = dev_get_drvdata(mcrc64_k3_dev);
+
+ pm_runtime_mark_last_busy(dev_data->dev);
+ pm_runtime_put_autosuspend(dev_data->dev);
+}
+
+static int mcrc64_setkey(struct crypto_shash *tfm, const u8 *key,
+ unsigned int keylen)
+{
+ struct mcrc64_ctx *mctx = crypto_shash_ctx(tfm);
+
+ if (keylen != sizeof(u32))
+ return -EINVAL;
+
+ mctx->key = get_unaligned_le32(key);
+
+ return 0;
+}
+
+static int mcrc64_init(struct shash_desc *desc)
+{
+ struct mcrc64_data *dev_data = dev_get_drvdata(mcrc64_k3_dev);
+
+ /* set full cpu mode */
+ int ret = mcrc64_set_mode(dev_data->regs, MCRC64_CHANNEL_1,
+ MCRC64_MODE_FULL_CPU);
+ if (ret)
+ return ret;
+
+ /* reset PSA */
+ return mcrc64_reset_signature(dev_data->regs, MCRC64_CHANNEL_1);
+}
+
+static int mcrc64_update(struct shash_desc *desc, const u8 *d8,
+ unsigned int length)
+{
+ struct mcrc64_desc_ctx *ctx = shash_desc_ctx(desc);
+ struct mcrc64_data *dev_data = dev_get_drvdata(mcrc64_k3_dev);
+
+ return mcrc64_calculate_crc(dev_data->regs, MCRC64_CHANNEL_1,
+ d8, length, &ctx->signature);
+}
+
+static int mcrc64_final(struct shash_desc *desc, u8 *out)
+{
+ struct mcrc64_desc_ctx *ctx = shash_desc_ctx(desc);
+
+ /* Send computed CRC */
+ put_unaligned_le64(ctx->signature, out);
+ return 0;
+}
+
+static int mcrc64_finup(struct shash_desc *desc, const u8 *data,
+ unsigned int length, u8 *out)
+{
+ return mcrc64_update(desc, data, length) ?:
+ mcrc64_final(desc, out);
+}
+
+static int mcrc64_digest(struct shash_desc *desc, const u8 *data,
+ unsigned int length, u8 *out)
+{
+ return mcrc64_init(desc) ?: mcrc64_finup(desc, data, length, out);
+}
+
+static struct shash_alg algs[] = {
+ /* CRC-64 */
+ {
+ .setkey = mcrc64_setkey,
+ .init = mcrc64_init,
+ .update = mcrc64_update,
+ .final = mcrc64_final,
+ .finup = mcrc64_finup,
+ .digest = mcrc64_digest,
+ .descsize = sizeof(struct mcrc64_desc_ctx),
+ .digestsize = CHKSUM_DIGEST_SIZE,
+ .base = {
+ .cra_name = "crc64-iso",
+ .cra_driver_name = "mcrc64",
+ .cra_priority = 200,
+ .cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
+ .cra_blocksize = CHKSUM_BLOCK_SIZE,
+ .cra_alignmask = 7,
+ .cra_ctxsize = sizeof(struct mcrc64_ctx),
+ .cra_module = THIS_MODULE,
+ .cra_init = mcrc64_cra_init,
+ .cra_exit = mcrc64_cra_exit,
+ }
+ }
+};
+
+static int mcrc64_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mcrc64_data *dev_data;
+
+ dev_data = devm_kzalloc(dev, sizeof(*dev_data), GFP_KERNEL);
+ if (!dev_data)
+ return -ENOMEM;
+
+ mcrc64_k3_dev = dev;
+ dev_data->dev = dev;
+ dev_data->regs = devm_platform_ioremap_resource(pdev, 0);
+
+ platform_set_drvdata(pdev, dev_data);
+ dev_set_drvdata(mcrc64_k3_dev, dev_data);
+
+ crypto_register_shashes(algs, ARRAY_SIZE(algs));
+
+ pm_runtime_set_autosuspend_delay(dev, MCRC64_AUTOSUSPEND_DELAY);
+ pm_runtime_use_autosuspend(dev);
+
+ pm_runtime_get_noresume(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+
+ pm_runtime_put_sync(dev);
+
+ return 0;
+}
+
+static int mcrc64_remove(struct platform_device *pdev)
+{
+ struct mcrc64_data *dev_data = platform_get_drvdata(pdev);
+
+ int ret = pm_runtime_get_sync(dev_data->dev);
+
+ if (ret < 0) {
+ pm_runtime_put_noidle(dev_data->dev);
+ return ret;
+ }
+
+ crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
+
+ pm_runtime_disable(dev_data->dev);
+ pm_runtime_put_noidle(dev_data->dev);
+
+ return 0;
+}
+
+static int __maybe_unused mcrc64_suspend(struct device *dev)
+{
+ return pm_runtime_force_suspend(dev);
+}
+
+static int __maybe_unused mcrc64_resume(struct device *dev)
+{
+ return pm_runtime_force_resume(dev);
+}
+
+static const struct dev_pm_ops mcrc64_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(mcrc64_suspend,
+ mcrc64_resume)
+};
+
+static const struct of_device_id of_match[] = {
+ { .compatible = "ti,mcrc64", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, of_match);
+
+static struct platform_driver mcrc64_driver = {
+ .probe = mcrc64_probe,
+ .remove = mcrc64_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .pm = &mcrc64_pm_ops,
+ .of_match_table = of_match,
+ },
+};
+
+module_platform_driver(mcrc64_driver);
+
+MODULE_AUTHOR("Kamlesh Gurudasani <kamlesh@ti.com>");
+MODULE_DESCRIPTION("Texas Instruments MCRC64 hardware driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/5] arm64: dts: ti: k3-am62: Add dt node, cbass_main ranges for MCRC64
2023-07-30 18:55 [PATCH 0/5] Add support for Texas Instruments MCRC64 engine Kamlesh Gurudasani
` (2 preceding siblings ...)
2023-07-30 18:55 ` [PATCH 3/5] crypto: ti - add driver for MCRC64 engine Kamlesh Gurudasani
@ 2023-07-30 18:55 ` Kamlesh Gurudasani
2023-07-30 18:55 ` [PATCH 5/5] arm64: defconfig: enable MCRC module Kamlesh Gurudasani
2023-07-31 17:48 ` [PATCH 0/5] Add support for Texas Instruments MCRC64 engine Ard Biesheuvel
5 siblings, 0 replies; 14+ messages in thread
From: Kamlesh Gurudasani @ 2023-07-30 18:55 UTC (permalink / raw
To: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Catalin Marinas, Will Deacon
Cc: linux-crypto, linux-kernel, devicetree, linux-arm-kernel,
Kamlesh Gurudasani
Add the address space for MCRC64 to the ranges property of the
cbass_main node and add dt node for MCRC64 engine
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
---
arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 7 +++++++
arch/arm64/boot/dts/ti/k3-am62.dtsi | 1 +
2 files changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
index 33b6aadc9083..bd12616a120c 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
@@ -183,6 +183,13 @@ crypto: crypto@40900000 {
dma-names = "tx", "rx1", "rx2";
};
+ mcrc64: mcrc64@30300000 {
+ compatible = "ti,mcrc64";
+ reg = <0x00 0x30300000 0x00 0x1000>;
+ clocks = <&k3_clks 116 0>;
+ power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
+ };
+
secure_proxy_sa3: mailbox@43600000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi
index 5e72c445f37a..1511e649a916 100644
--- a/arch/arm64/boot/dts/ti/k3-am62.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi
@@ -65,6 +65,7 @@ cbass_main: bus@f0000 {
<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
<0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
+ <0x00 0x30300000 0x00 0x30300000 0x00 0x00001000>, /* MCRC */
<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 5/5] arm64: defconfig: enable MCRC module
2023-07-30 18:55 [PATCH 0/5] Add support for Texas Instruments MCRC64 engine Kamlesh Gurudasani
` (3 preceding siblings ...)
2023-07-30 18:55 ` [PATCH 4/5] arm64: dts: ti: k3-am62: Add dt node, cbass_main ranges for MCRC64 Kamlesh Gurudasani
@ 2023-07-30 18:55 ` Kamlesh Gurudasani
2023-07-31 17:48 ` [PATCH 0/5] Add support for Texas Instruments MCRC64 engine Ard Biesheuvel
5 siblings, 0 replies; 14+ messages in thread
From: Kamlesh Gurudasani @ 2023-07-30 18:55 UTC (permalink / raw
To: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Catalin Marinas, Will Deacon
Cc: linux-crypto, linux-kernel, devicetree, linux-arm-kernel,
Kamlesh Gurudasani
K3 devices include MCRC engine for crc64 calculation.
Enable module to be built for K3 devices.
Also enable algif_hash module, which is needed to access MCRC module
from userspace.
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6cbf6eb59378..6006983b313e 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1505,6 +1505,7 @@ CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_RNG=m
CONFIG_CRYPTO_CHACHA20_NEON=m
CONFIG_CRYPTO_GHASH_ARM64_CE=y
@@ -1528,6 +1529,7 @@ CONFIG_CRYPTO_DEV_HISI_ZIP=m
CONFIG_CRYPTO_DEV_HISI_HPRE=m
CONFIG_CRYPTO_DEV_HISI_TRNG=m
CONFIG_CRYPTO_DEV_SA2UL=m
+CONFIG_CRYPTO_DEV_TI_MCRC64=m
CONFIG_DMA_RESTRICTED_POOL=y
CONFIG_CMA_SIZE_MBYTES=32
CONFIG_PRINTK_TIME=y
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 2/5] dt-bindings: crypto: Add binding for TI MCRC64 driver
2023-07-30 18:55 ` [PATCH 2/5] dt-bindings: crypto: Add binding for TI MCRC64 driver Kamlesh Gurudasani
@ 2023-07-30 19:15 ` Krzysztof Kozlowski
2023-07-30 19:28 ` Rob Herring
1 sibling, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2023-07-30 19:15 UTC (permalink / raw
To: Kamlesh Gurudasani, Herbert Xu, David S. Miller, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Nishanth Menon,
Vignesh Raghavendra, Tero Kristo, Catalin Marinas, Will Deacon
Cc: linux-crypto, linux-kernel, devicetree, linux-arm-kernel
On 30/07/2023 20:55, Kamlesh Gurudasani wrote:
> Add binding for Texas Instruments MCRC64 driver
A nit, subject: drop second/last, redundant "binding for". The
"dt-bindings" prefix is already stating that these are bindings.
Here and subject: drop driver. Bindings are for hardware.
Neither commit nor bindings in description: field explain what is this
hardware.
>
> Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
> ---
> Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml | 42 ++++++++++++++++++++++++++++++++++++++++++
> MAINTAINERS | 5 +++++
> 2 files changed, 47 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml b/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml
> new file mode 100644
> index 000000000000..1d1e3f87638c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml
> @@ -0,0 +1,42 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/crypto/ti,mcrc64.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Texas Instruments MCRC64 bindings
Drop bindings. If you tested your code, you would see a warning, so:
It does not look like you tested the bindings, at least after quick
look. Please run `make dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
Maybe you need to update your dtschema and yamllint.
> +
> +maintainers:
> + - Kamlesh Gurudasani <kamlesh@ti.com>
> +
> +properties:
> + compatible:
> + const: ti,mcrc64
What's this? Part of SoC? Then the compatible is not correct.
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + mcrc64: mcrc64@30300000 {
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "ti,mcrc64";
> + reg = <0x00 0x30300000 0x00 0x1000>;
> + clocks = <&k3_clks 116 0>;
> + power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
> + };
Indentation is messed up.
>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/5] crypto: ti - add driver for MCRC64 engine
2023-07-30 18:55 ` [PATCH 3/5] crypto: ti - add driver for MCRC64 engine Kamlesh Gurudasani
@ 2023-07-30 19:18 ` Krzysztof Kozlowski
2023-07-31 17:50 ` Ard Biesheuvel
1 sibling, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2023-07-30 19:18 UTC (permalink / raw
To: Kamlesh Gurudasani, Herbert Xu, David S. Miller, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Nishanth Menon,
Vignesh Raghavendra, Tero Kristo, Catalin Marinas, Will Deacon
Cc: linux-crypto, linux-kernel, devicetree, linux-arm-kernel
On 30/07/2023 20:55, Kamlesh Gurudasani wrote:
> Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode.
>
> In Full-CPU mode, the CPU does the data patterns transfer and signature
> verification all by itself, only CRC calculation is being done by MCRC64
> engine.
>
> MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
> according to the ISO 3309 standard.
>
> Generator polynomial: x^64 + x^4 + x^3 + x + 1
> Polynomial value: 0x000000000000001b
>
> Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
> ---
> MAINTAINERS | 2 +
> drivers/crypto/Kconfig | 1 +
> drivers/crypto/Makefile | 1 +
> drivers/crypto/ti/Kconfig | 10 +++
> drivers/crypto/ti/Makefile | 2 +
> drivers/crypto/ti/mcrc64.c | 360 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 6 files changed, 376 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index d8680f6969e3..a2f50adb51ac 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -21464,8 +21464,10 @@ F: drivers/iio/adc/ti-lmp92064.c
>
> TI MEMORY CYCLIC REDUNDANCY CHECK (MCRC64) DRIVER
> M: Kamlesh Gurudasani <kamlesh@ti.com>
> +L: linux-crypto@vger.kernel.org
> S: Maintained
> F: Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml
> +F: drivers/crypto/ti/mcrc64.c
>
> TI PCM3060 ASoC CODEC DRIVER
> M: Kirill Marinushkin <kmarinushkin@birdec.com>
> diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
> index c761952f0dc6..2101f92ead66 100644
> --- a/drivers/crypto/Kconfig
> +++ b/drivers/crypto/Kconfig
> @@ -796,5 +796,6 @@ config CRYPTO_DEV_SA2UL
>
> source "drivers/crypto/aspeed/Kconfig"
> source "drivers/crypto/starfive/Kconfig"
> +source "drivers/crypto/ti/Kconfig"
>
> endif # CRYPTO_HW
> diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
> index d859d6a5f3a4..f1a151b73ff1 100644
> --- a/drivers/crypto/Makefile
> +++ b/drivers/crypto/Makefile
> @@ -41,6 +41,7 @@ obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
> obj-$(CONFIG_CRYPTO_DEV_SL3516) += gemini/
> obj-y += stm32/
> obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
> +obj-$(CONFIG_ARCH_K3) += ti/
> obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/
> obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
> obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
> diff --git a/drivers/crypto/ti/Kconfig b/drivers/crypto/ti/Kconfig
> new file mode 100644
> index 000000000000..8e3b2b8b7623
> --- /dev/null
> +++ b/drivers/crypto/ti/Kconfig
> @@ -0,0 +1,10 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +config CRYPTO_DEV_TI_MCRC64
> + tristate "Support for TI MCRC64 crc64 accelerators"
> + depends on ARCH_K3
So it is a part of Soc. Fix the compatible.
> + select CRYPTO_HASH
> + help
> + This enables support for the MCRC64 hw accelerator
> + which can be found on TI SOC.
> + MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
> + according to the ISO 3309 standard using Full-CPU mode.
> \ No newline at end of file
You have warnings...
> diff --git a/drivers/crypto/ti/Makefile b/drivers/crypto/ti/Makefile
> new file mode 100644
> index 000000000000..94ffc2576137
> --- /dev/null
> +++ b/drivers/crypto/ti/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +obj-$(CONFIG_CRYPTO_DEV_TI_MCRC64) += mcrc64.o
> diff --git a/drivers/crypto/ti/mcrc64.c b/drivers/crypto/ti/mcrc64.c
> new file mode 100644
> index 000000000000..45f8ae6078ff
> --- /dev/null
> +++ b/drivers/crypto/ti/mcrc64.c
> @@ -0,0 +1,360 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) Texas Instruments 2023 - http://www.ti.com
> + * Author: Kamlesh Gurudasani <kamlesh@ti.com>
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +
> +#include <crypto/internal/hash.h>
> +
> +#include <asm/unaligned.h>
> +
> +#define DRIVER_NAME "mcrc64"
> +#define CHKSUM_DIGEST_SIZE 8
> +#define CHKSUM_BLOCK_SIZE 1
> +
> +/* Registers */
> +#define CRC_CTRL0 0x0000 /* CRC Global Control Register 0 */
> +#define CH_PSA_SWRE(ch) BIT(((ch) - 1) << 3) /* PSA Software Reset */
> +
> +#define CRC_CTRL1 0x0008 /* CRC Global Control Register 1 */
> +#define PWDN BIT(0) /* Power Down */
> +
> +#define CRC_CTRL2 0x0010 /* CRC Global Control Register 2 */
> +#define CH_MODE(ch, m) ((m) << (((ch) - 1) << 3))
> +
> +#define PSA_SIGREGL(ch) ((0x6 + (4 * ((ch) - 1))) << 4) /* Signature register */
> +
> +#define MCRC64_ALG_MASK 0x8000000000000000
> +#define MCRC64_CRC64_POLY 0x000000000000001b
> +
> +#define MCRC64_AUTOSUSPEND_DELAY 50
> +
> +static struct device *mcrc64_k3_dev;
Nope. How do you support two devices? No, no, drop such approach
entirely from *all your drivers before upstreaming*.
> +
> +enum mcrc64_mode {
> + MCRC64_MODE_DATA_CAPTURE = 0,
> + MCRC64_MODE_AUTO,
> + MCRC64_MODE_SEMI_CPU,
> + MCRC64_MODE_FULL_CPU,
> + MCRC64_MODE_INVALID,
> +};
> +
> +enum mcrc64_channel {
> + MCRC64_CHANNEL_1 = 1,
> + MCRC64_CHANNEL_2,
> + MCRC64_CHANNEL_3,
> + MCRC64_CHANNEL_4,
> + MCRC64_CHANNEL_INVALID,
> +};
> +
> +struct mcrc64_data {
> + struct device *dev;
> + void __iomem *regs;
> +};
> +
> +struct mcrc64_ctx {
> + u32 key;
> +};
> +
> +struct mcrc64_desc_ctx {
> + u64 signature;
Keep consistent indentation/alignment in structures.
> +};
> +
...
> +
> +static int mcrc64_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mcrc64_data *dev_data;
> +
> + dev_data = devm_kzalloc(dev, sizeof(*dev_data), GFP_KERNEL);
> + if (!dev_data)
> + return -ENOMEM;
> +
> + mcrc64_k3_dev = dev;
> + dev_data->dev = dev;
> + dev_data->regs = devm_platform_ioremap_resource(pdev, 0);
> +
> + platform_set_drvdata(pdev, dev_data);
> + dev_set_drvdata(mcrc64_k3_dev, dev_data);
> +
> + crypto_register_shashes(algs, ARRAY_SIZE(algs));
> +
> + pm_runtime_set_autosuspend_delay(dev, MCRC64_AUTOSUSPEND_DELAY);
> + pm_runtime_use_autosuspend(dev);
> +
> + pm_runtime_get_noresume(dev);
> + pm_runtime_set_active(dev);
> + pm_runtime_enable(dev);
> +
> + pm_runtime_put_sync(dev);
> +
> + return 0;
> +}
> +
> +static int mcrc64_remove(struct platform_device *pdev)
> +{
> + struct mcrc64_data *dev_data = platform_get_drvdata(pdev);
> +
> + int ret = pm_runtime_get_sync(dev_data->dev);
> +
> + if (ret < 0) {
> + pm_runtime_put_noidle(dev_data->dev);
> + return ret;
> + }
Isn't there helper doing this for you?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/5] dt-bindings: crypto: Add binding for TI MCRC64 driver
2023-07-30 18:55 ` [PATCH 2/5] dt-bindings: crypto: Add binding for TI MCRC64 driver Kamlesh Gurudasani
2023-07-30 19:15 ` Krzysztof Kozlowski
@ 2023-07-30 19:28 ` Rob Herring
1 sibling, 0 replies; 14+ messages in thread
From: Rob Herring @ 2023-07-30 19:28 UTC (permalink / raw
To: Kamlesh Gurudasani
Cc: David S. Miller, linux-kernel, Rob Herring, Will Deacon,
devicetree, Catalin Marinas, Tero Kristo, linux-arm-kernel,
Herbert Xu, Vignesh Raghavendra, Krzysztof Kozlowski,
Nishanth Menon, linux-crypto, Conor Dooley
On Mon, 31 Jul 2023 00:25:55 +0530, Kamlesh Gurudasani wrote:
> Add binding for Texas Instruments MCRC64 driver
>
> Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
> ---
> Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml | 42 ++++++++++++++++++++++++++++++++++++++++++
> MAINTAINERS | 5 +++++
> 2 files changed, 47 insertions(+)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml: title: 'Texas Instruments MCRC64 bindings' should not be valid under {'pattern': '([Bb]inding| [Ss]chema)'}
hint: Everything is a binding/schema, no need to say it. Describe what hardware the binding is for.
from schema $id: http://devicetree.org/meta-schemas/base.yaml#
Error: Documentation/devicetree/bindings/crypto/ti,mcrc64.example.dts:22.40-41 syntax error
FATAL ERROR: Unable to parse input tree
make[2]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/crypto/ti,mcrc64.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1500: dt_binding_check] Error 2
make: *** [Makefile:234: __sub-make] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230719-mcrc-upstream-v1-2-dc8798a24c47@ti.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 0/5] Add support for Texas Instruments MCRC64 engine
2023-07-30 18:55 [PATCH 0/5] Add support for Texas Instruments MCRC64 engine Kamlesh Gurudasani
` (4 preceding siblings ...)
2023-07-30 18:55 ` [PATCH 5/5] arm64: defconfig: enable MCRC module Kamlesh Gurudasani
@ 2023-07-31 17:48 ` Ard Biesheuvel
2023-08-01 6:22 ` [EXTERNAL] " Kamlesh Gurudasani
5 siblings, 1 reply; 14+ messages in thread
From: Ard Biesheuvel @ 2023-07-31 17:48 UTC (permalink / raw
To: Kamlesh Gurudasani
Cc: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Catalin Marinas, Will Deacon, linux-crypto, linux-kernel,
devicetree, linux-arm-kernel
On Sun, 30 Jul 2023 at 20:56, Kamlesh Gurudasani <kamlesh@ti.com> wrote:
>
> Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode
>
> MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
> according to the ISO 3309 standard.
>
> Generator polynomial: x^64 + x^4 + x^3 + x + 1
> Polynomial value: 0x000000000000001b
>
How will this code be used? WIthout a user of the crc64-iso crypto API
algorithm, there is no point in having a driver that implements it.
Also, *if* such a user exists, we'd need to have a generic C
implementation as well - we don't add new algorithms unless they can
be enabled on all platforms and architectures.
> Tested with
>
> and tcrypt,
> sudo modprobe tcrypt mode=329 sec=1
>
> Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
> ---
> Kamlesh Gurudasani (5):
> crypto: crc64 - add crc64-iso test vectors
> dt-bindings: crypto: Add binding for TI MCRC64 driver
> crypto: ti - add driver for MCRC64 engine
> arm64: dts: ti: k3-am62: Add dt node, cbass_main ranges for MCRC64
> arm64: defconfig: enable MCRC module
>
> Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml | 42 +++++++
> MAINTAINERS | 7 ++
> arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 7 ++
> arch/arm64/boot/dts/ti/k3-am62.dtsi | 1 +
> arch/arm64/configs/defconfig | 2 +
> crypto/tcrypt.c | 5 +
> crypto/testmgr.c | 7 ++
> crypto/testmgr.h | 401 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> drivers/crypto/Kconfig | 1 +
> drivers/crypto/Makefile | 1 +
> drivers/crypto/ti/Kconfig | 10 ++
> drivers/crypto/ti/Makefile | 2 +
> drivers/crypto/ti/mcrc64.c | 360 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 13 files changed, 846 insertions(+)
> ---
> base-commit: d7b3af5a77e8d8da28f435f313e069aea5bcf172
> change-id: 20230719-mcrc-upstream-7ae9a75cab37
>
> Best regards,
> --
> Kamlesh Gurudasani <kamlesh@ti.com>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/5] crypto: ti - add driver for MCRC64 engine
2023-07-30 18:55 ` [PATCH 3/5] crypto: ti - add driver for MCRC64 engine Kamlesh Gurudasani
2023-07-30 19:18 ` Krzysztof Kozlowski
@ 2023-07-31 17:50 ` Ard Biesheuvel
1 sibling, 0 replies; 14+ messages in thread
From: Ard Biesheuvel @ 2023-07-31 17:50 UTC (permalink / raw
To: Kamlesh Gurudasani
Cc: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Catalin Marinas, Will Deacon, linux-crypto, linux-kernel,
devicetree, linux-arm-kernel
On Sun, 30 Jul 2023 at 20:56, Kamlesh Gurudasani <kamlesh@ti.com> wrote:
>
> Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode.
>
> In Full-CPU mode, the CPU does the data patterns transfer and signature
> verification all by itself, only CRC calculation is being done by MCRC64
> engine.
>
> MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
> according to the ISO 3309 standard.
>
> Generator polynomial: x^64 + x^4 + x^3 + x + 1
> Polynomial value: 0x000000000000001b
>
> Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
> ---
> MAINTAINERS | 2 +
> drivers/crypto/Kconfig | 1 +
> drivers/crypto/Makefile | 1 +
> drivers/crypto/ti/Kconfig | 10 +++
> drivers/crypto/ti/Makefile | 2 +
> drivers/crypto/ti/mcrc64.c | 360 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 6 files changed, 376 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index d8680f6969e3..a2f50adb51ac 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -21464,8 +21464,10 @@ F: drivers/iio/adc/ti-lmp92064.c
>
> TI MEMORY CYCLIC REDUNDANCY CHECK (MCRC64) DRIVER
> M: Kamlesh Gurudasani <kamlesh@ti.com>
> +L: linux-crypto@vger.kernel.org
> S: Maintained
> F: Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml
> +F: drivers/crypto/ti/mcrc64.c
>
> TI PCM3060 ASoC CODEC DRIVER
> M: Kirill Marinushkin <kmarinushkin@birdec.com>
> diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
> index c761952f0dc6..2101f92ead66 100644
> --- a/drivers/crypto/Kconfig
> +++ b/drivers/crypto/Kconfig
> @@ -796,5 +796,6 @@ config CRYPTO_DEV_SA2UL
>
> source "drivers/crypto/aspeed/Kconfig"
> source "drivers/crypto/starfive/Kconfig"
> +source "drivers/crypto/ti/Kconfig"
>
> endif # CRYPTO_HW
> diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
> index d859d6a5f3a4..f1a151b73ff1 100644
> --- a/drivers/crypto/Makefile
> +++ b/drivers/crypto/Makefile
> @@ -41,6 +41,7 @@ obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
> obj-$(CONFIG_CRYPTO_DEV_SL3516) += gemini/
> obj-y += stm32/
> obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
> +obj-$(CONFIG_ARCH_K3) += ti/
> obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/
> obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
> obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
> diff --git a/drivers/crypto/ti/Kconfig b/drivers/crypto/ti/Kconfig
> new file mode 100644
> index 000000000000..8e3b2b8b7623
> --- /dev/null
> +++ b/drivers/crypto/ti/Kconfig
> @@ -0,0 +1,10 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +config CRYPTO_DEV_TI_MCRC64
> + tristate "Support for TI MCRC64 crc64 accelerators"
> + depends on ARCH_K3
> + select CRYPTO_HASH
> + help
> + This enables support for the MCRC64 hw accelerator
> + which can be found on TI SOC.
> + MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
> + according to the ISO 3309 standard using Full-CPU mode.
> \ No newline at end of file
> diff --git a/drivers/crypto/ti/Makefile b/drivers/crypto/ti/Makefile
> new file mode 100644
> index 000000000000..94ffc2576137
> --- /dev/null
> +++ b/drivers/crypto/ti/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +obj-$(CONFIG_CRYPTO_DEV_TI_MCRC64) += mcrc64.o
> diff --git a/drivers/crypto/ti/mcrc64.c b/drivers/crypto/ti/mcrc64.c
> new file mode 100644
> index 000000000000..45f8ae6078ff
> --- /dev/null
> +++ b/drivers/crypto/ti/mcrc64.c
> @@ -0,0 +1,360 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) Texas Instruments 2023 - http://www.ti.com
> + * Author: Kamlesh Gurudasani <kamlesh@ti.com>
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +
> +#include <crypto/internal/hash.h>
> +
> +#include <asm/unaligned.h>
> +
> +#define DRIVER_NAME "mcrc64"
> +#define CHKSUM_DIGEST_SIZE 8
> +#define CHKSUM_BLOCK_SIZE 1
> +
> +/* Registers */
> +#define CRC_CTRL0 0x0000 /* CRC Global Control Register 0 */
> +#define CH_PSA_SWRE(ch) BIT(((ch) - 1) << 3) /* PSA Software Reset */
> +
> +#define CRC_CTRL1 0x0008 /* CRC Global Control Register 1 */
> +#define PWDN BIT(0) /* Power Down */
> +
> +#define CRC_CTRL2 0x0010 /* CRC Global Control Register 2 */
> +#define CH_MODE(ch, m) ((m) << (((ch) - 1) << 3))
> +
> +#define PSA_SIGREGL(ch) ((0x6 + (4 * ((ch) - 1))) << 4) /* Signature register */
> +
> +#define MCRC64_ALG_MASK 0x8000000000000000
> +#define MCRC64_CRC64_POLY 0x000000000000001b
> +
> +#define MCRC64_AUTOSUSPEND_DELAY 50
> +
> +static struct device *mcrc64_k3_dev;
> +
> +enum mcrc64_mode {
> + MCRC64_MODE_DATA_CAPTURE = 0,
> + MCRC64_MODE_AUTO,
> + MCRC64_MODE_SEMI_CPU,
> + MCRC64_MODE_FULL_CPU,
> + MCRC64_MODE_INVALID,
> +};
> +
> +enum mcrc64_channel {
> + MCRC64_CHANNEL_1 = 1,
> + MCRC64_CHANNEL_2,
> + MCRC64_CHANNEL_3,
> + MCRC64_CHANNEL_4,
> + MCRC64_CHANNEL_INVALID,
> +};
> +
> +struct mcrc64_data {
> + struct device *dev;
> + void __iomem *regs;
> +};
> +
> +struct mcrc64_ctx {
> + u32 key;
> +};
> +
> +struct mcrc64_desc_ctx {
> + u64 signature;
> +};
> +
> +static int mcrc64_set_mode(void __iomem *regs, u32 channel, u32 mode)
> +{
> + u32 mode_set_val;
> + u32 crc_ctrl2_reg = 0;
> +
> + if (mode < 0 || mode >= MCRC64_MODE_INVALID)
> + return -EINVAL;
> +
> + if (channel <= 0 || channel >= MCRC64_CHANNEL_INVALID)
> + return -EINVAL;
> +
> + mode_set_val = crc_ctrl2_reg | CH_MODE(channel, mode);
> +
> + /* Write CRC_CTRL2, set mode */
> + writel_relaxed(mode_set_val, regs + CRC_CTRL2);
> +
> + return 0;
> +}
> +
> +static int mcrc64_reset_signature(void __iomem *regs, u32 channel)
> +{
> + u32 crc_ctrl0_reg, reset_val, reset_undo_val;
> +
> + if (channel <= 0 || channel >= MCRC64_CHANNEL_INVALID)
> + return -EINVAL;
> +
> + /* reset PSA */
> + crc_ctrl0_reg = readl_relaxed(regs + CRC_CTRL0);
> +
> + reset_val = crc_ctrl0_reg | CH_PSA_SWRE(channel);
> + reset_undo_val = crc_ctrl0_reg & ~CH_PSA_SWRE(channel);
> +
> + /* Write CRC_CTRL0 register, reset PSA register */
> + writel_relaxed(reset_val, regs + CRC_CTRL0);
> + writel_relaxed(reset_undo_val, regs + CRC_CTRL0);
> +
> + return 0;
> +}
> +
> +/* This helper implements crc64 calculation using CPU */
> +static u64 mcrc64_calculate_sw_crc(u64 crc, u8 byte)
> +{
> + u64 bit = 0;
> + u8 j;
> +
> + for (j = 0; j < 8; j++) {
> + bit = crc & MCRC64_ALG_MASK;
> + crc <<= 1;
> + if (byte & (0x80 >> j))
> + bit ^= MCRC64_ALG_MASK;
> + if (bit)
> + crc ^= MCRC64_CRC64_POLY;
> + }
> +
> + return crc;
> +}
> +
> +static int mcrc64_calculate_crc(void __iomem *regs, u32 channel,
> + const u8 *d8, size_t length, u64 *crc64)
> +{
> + void __iomem *psa_reg;
> + u64 signature = 0;
> +
> + if (channel <= 0 || channel >= MCRC64_CHANNEL_INVALID)
> + return -EINVAL;
> +
> + psa_reg = regs + PSA_SIGREGL(channel);
> +
> + for (; length >= sizeof(u64); d8 += sizeof(u64), length -= sizeof(u64))
> + writeq_relaxed(cpu_to_be64p((u64 *)d8), psa_reg);
> +
> + signature = readq_relaxed(psa_reg);
> +
> + if (length) {
> + while (length--)
> + signature = mcrc64_calculate_sw_crc(signature, *d8++);
> +
> + /* set capture mode */
> + int ret = mcrc64_set_mode(regs, MCRC64_CHANNEL_1,
> + MCRC64_MODE_DATA_CAPTURE);
> + if (ret)
> + return ret;
> +
> + ret = mcrc64_reset_signature(regs, MCRC64_CHANNEL_1);
> + if (ret)
> + return ret;
> +
> + writeq_relaxed(signature, psa_reg);
> +
> + ret = mcrc64_set_mode(regs, MCRC64_CHANNEL_1,
> + MCRC64_MODE_FULL_CPU);
> + if (ret)
> + return ret;
> + }
> +
> + *crc64 = signature;
> +
> + return 0;
> +}
> +
> +static int mcrc64_cra_init(struct crypto_tfm *tfm)
> +{
> + struct mcrc64_ctx *mctx = crypto_tfm_ctx(tfm);
> +
> + struct mcrc64_data *dev_data = dev_get_drvdata(mcrc64_k3_dev);
> +
> + pm_runtime_get_sync(dev_data->dev);
> +
> + mctx->key = 0;
> +
> + return 0;
> +}
> +
> +static void mcrc64_cra_exit(struct crypto_tfm *tfm)
> +{
> + struct mcrc64_data *dev_data = dev_get_drvdata(mcrc64_k3_dev);
> +
> + pm_runtime_mark_last_busy(dev_data->dev);
> + pm_runtime_put_autosuspend(dev_data->dev);
> +}
> +
> +static int mcrc64_setkey(struct crypto_shash *tfm, const u8 *key,
> + unsigned int keylen)
> +{
> + struct mcrc64_ctx *mctx = crypto_shash_ctx(tfm);
> +
> + if (keylen != sizeof(u32))
> + return -EINVAL;
> +
> + mctx->key = get_unaligned_le32(key);
> +
What is the point of this key?
> + return 0;
> +}
> +
> +static int mcrc64_init(struct shash_desc *desc)
> +{
> + struct mcrc64_data *dev_data = dev_get_drvdata(mcrc64_k3_dev);
> +
> + /* set full cpu mode */
> + int ret = mcrc64_set_mode(dev_data->regs, MCRC64_CHANNEL_1,
> + MCRC64_MODE_FULL_CPU);
> + if (ret)
> + return ret;
> +
> + /* reset PSA */
> + return mcrc64_reset_signature(dev_data->regs, MCRC64_CHANNEL_1);
> +}
> +
> +static int mcrc64_update(struct shash_desc *desc, const u8 *d8,
> + unsigned int length)
> +{
> + struct mcrc64_desc_ctx *ctx = shash_desc_ctx(desc);
> + struct mcrc64_data *dev_data = dev_get_drvdata(mcrc64_k3_dev);
> +
> + return mcrc64_calculate_crc(dev_data->regs, MCRC64_CHANNEL_1,
> + d8, length, &ctx->signature);
> +}
> +
> +static int mcrc64_final(struct shash_desc *desc, u8 *out)
> +{
> + struct mcrc64_desc_ctx *ctx = shash_desc_ctx(desc);
> +
> + /* Send computed CRC */
> + put_unaligned_le64(ctx->signature, out);
> + return 0;
> +}
> +
> +static int mcrc64_finup(struct shash_desc *desc, const u8 *data,
> + unsigned int length, u8 *out)
> +{
> + return mcrc64_update(desc, data, length) ?:
> + mcrc64_final(desc, out);
> +}
> +
> +static int mcrc64_digest(struct shash_desc *desc, const u8 *data,
> + unsigned int length, u8 *out)
> +{
> + return mcrc64_init(desc) ?: mcrc64_finup(desc, data, length, out);
> +}
> +
> +static struct shash_alg algs[] = {
> + /* CRC-64 */
> + {
> + .setkey = mcrc64_setkey,
> + .init = mcrc64_init,
> + .update = mcrc64_update,
> + .final = mcrc64_final,
> + .finup = mcrc64_finup,
> + .digest = mcrc64_digest,
> + .descsize = sizeof(struct mcrc64_desc_ctx),
> + .digestsize = CHKSUM_DIGEST_SIZE,
> + .base = {
> + .cra_name = "crc64-iso",
> + .cra_driver_name = "mcrc64",
> + .cra_priority = 200,
> + .cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
> + .cra_blocksize = CHKSUM_BLOCK_SIZE,
> + .cra_alignmask = 7,
> + .cra_ctxsize = sizeof(struct mcrc64_ctx),
> + .cra_module = THIS_MODULE,
> + .cra_init = mcrc64_cra_init,
> + .cra_exit = mcrc64_cra_exit,
> + }
> + }
> +};
> +
> +static int mcrc64_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mcrc64_data *dev_data;
> +
> + dev_data = devm_kzalloc(dev, sizeof(*dev_data), GFP_KERNEL);
> + if (!dev_data)
> + return -ENOMEM;
> +
> + mcrc64_k3_dev = dev;
> + dev_data->dev = dev;
> + dev_data->regs = devm_platform_ioremap_resource(pdev, 0);
> +
> + platform_set_drvdata(pdev, dev_data);
> + dev_set_drvdata(mcrc64_k3_dev, dev_data);
> +
> + crypto_register_shashes(algs, ARRAY_SIZE(algs));
> +
> + pm_runtime_set_autosuspend_delay(dev, MCRC64_AUTOSUSPEND_DELAY);
> + pm_runtime_use_autosuspend(dev);
> +
> + pm_runtime_get_noresume(dev);
> + pm_runtime_set_active(dev);
> + pm_runtime_enable(dev);
> +
> + pm_runtime_put_sync(dev);
> +
> + return 0;
> +}
> +
> +static int mcrc64_remove(struct platform_device *pdev)
> +{
> + struct mcrc64_data *dev_data = platform_get_drvdata(pdev);
> +
> + int ret = pm_runtime_get_sync(dev_data->dev);
> +
> + if (ret < 0) {
> + pm_runtime_put_noidle(dev_data->dev);
> + return ret;
> + }
> +
> + crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
> +
> + pm_runtime_disable(dev_data->dev);
> + pm_runtime_put_noidle(dev_data->dev);
> +
> + return 0;
> +}
> +
> +static int __maybe_unused mcrc64_suspend(struct device *dev)
> +{
> + return pm_runtime_force_suspend(dev);
> +}
> +
> +static int __maybe_unused mcrc64_resume(struct device *dev)
> +{
> + return pm_runtime_force_resume(dev);
> +}
> +
> +static const struct dev_pm_ops mcrc64_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(mcrc64_suspend,
> + mcrc64_resume)
> +};
> +
> +static const struct of_device_id of_match[] = {
> + { .compatible = "ti,mcrc64", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, of_match);
> +
> +static struct platform_driver mcrc64_driver = {
> + .probe = mcrc64_probe,
> + .remove = mcrc64_remove,
> + .driver = {
> + .name = DRIVER_NAME,
> + .pm = &mcrc64_pm_ops,
> + .of_match_table = of_match,
> + },
> +};
> +
> +module_platform_driver(mcrc64_driver);
> +
> +MODULE_AUTHOR("Kamlesh Gurudasani <kamlesh@ti.com>");
> +MODULE_DESCRIPTION("Texas Instruments MCRC64 hardware driver");
> +MODULE_LICENSE("GPL");
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [EXTERNAL] Re: [PATCH 0/5] Add support for Texas Instruments MCRC64 engine
2023-07-31 17:48 ` [PATCH 0/5] Add support for Texas Instruments MCRC64 engine Ard Biesheuvel
@ 2023-08-01 6:22 ` Kamlesh Gurudasani
2023-08-01 6:42 ` Ard Biesheuvel
0 siblings, 1 reply; 14+ messages in thread
From: Kamlesh Gurudasani @ 2023-08-01 6:22 UTC (permalink / raw
To: Ard Biesheuvel
Cc: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Menon, Nishanth, Raghavendra, Vignesh, Tero Kristo,
Catalin Marinas, Will Deacon, linux-crypto@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Ard Biesheuvel <ardb@kernel.org> writes:
> On Sun, 30 Jul 2023 at 20:56, Kamlesh Gurudasani <kamlesh@ti.com> wrote:
>>
>> Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode
>>
>> MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
>> according to the ISO 3309 standard.
>>
>> Generator polynomial: x^64 + x^4 + x^3 + x + 1
>> Polynomial value: 0x000000000000001b
>>
>
> How will this code be used? WIthout a user of the crc64-iso crypto API
> algorithm, there is no point in having a driver that implements it.
Thanks for the review.
MCRC64 will be used to check the integrity of memory blocks.
On TI K3 SOCs, users can use MCRC64 to accelerate the integrity check.
>
> Also, *if* such a user exists, we'd need to have a generic C
> implementation as well - we don't add new algorithms unless they can
> be enabled on all platforms and architectures.
If it is must, will implement generic C code.
>
>
>> Tested with
>>
>> and tcrypt,
>> sudo modprobe tcrypt mode=329 sec=1
>>
>> Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
>> ---
>> Kamlesh Gurudasani (5):
>> crypto: crc64 - add crc64-iso test vectors
>> dt-bindings: crypto: Add binding for TI MCRC64 driver
>> crypto: ti - add driver for MCRC64 engine
>> arm64: dts: ti: k3-am62: Add dt node, cbass_main ranges for MCRC64
>> arm64: defconfig: enable MCRC module
>>
>> Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml | 42 +++++++
>> MAINTAINERS | 7 ++
>> arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 7 ++
>> arch/arm64/boot/dts/ti/k3-am62.dtsi | 1 +
>> arch/arm64/configs/defconfig | 2 +
>> crypto/tcrypt.c | 5 +
>> crypto/testmgr.c | 7 ++
>> crypto/testmgr.h | 401 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>> drivers/crypto/Kconfig | 1 +
>> drivers/crypto/Makefile | 1 +
>> drivers/crypto/ti/Kconfig | 10 ++
>> drivers/crypto/ti/Makefile | 2 +
>> drivers/crypto/ti/mcrc64.c | 360 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>> 13 files changed, 846 insertions(+)
>> ---
>> base-commit: d7b3af5a77e8d8da28f435f313e069aea5bcf172
>> change-id: 20230719-mcrc-upstream-7ae9a75cab37
>>
>> Best regards,
>> --
>> Kamlesh Gurudasani <kamlesh@ti.com>
>>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [EXTERNAL] Re: [PATCH 0/5] Add support for Texas Instruments MCRC64 engine
2023-08-01 6:22 ` [EXTERNAL] " Kamlesh Gurudasani
@ 2023-08-01 6:42 ` Ard Biesheuvel
2023-08-01 7:02 ` [EXTERNAL] " Kamlesh Gurudasani
0 siblings, 1 reply; 14+ messages in thread
From: Ard Biesheuvel @ 2023-08-01 6:42 UTC (permalink / raw
To: Kamlesh Gurudasani
Cc: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Menon, Nishanth, Raghavendra, Vignesh, Tero Kristo,
Catalin Marinas, Will Deacon, linux-crypto@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
On Tue, 1 Aug 2023 at 08:22, Kamlesh Gurudasani <kamlesh@ti.com> wrote:
>
> Ard Biesheuvel <ardb@kernel.org> writes:
>
> > On Sun, 30 Jul 2023 at 20:56, Kamlesh Gurudasani <kamlesh@ti.com> wrote:
> >>
> >> Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode
> >>
> >> MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
> >> according to the ISO 3309 standard.
> >>
> >> Generator polynomial: x^64 + x^4 + x^3 + x + 1
> >> Polynomial value: 0x000000000000001b
> >>
> >
> > How will this code be used? WIthout a user of the crc64-iso crypto API
> > algorithm, there is no point in having a driver that implements it.
>
> Thanks for the review.
>
> MCRC64 will be used to check the integrity of memory blocks.
> On TI K3 SOCs, users can use MCRC64 to accelerate the integrity check.
>
Where is the implementation of this logic? Does it use the shash/ahash API?
If so, it should be part of this series.
> >
> > Also, *if* such a user exists, we'd need to have a generic C
> > implementation as well - we don't add new algorithms unless they can
> > be enabled on all platforms and architectures.
>
> If it is must, will implement generic C code.
>
> >
> >
> >> Tested with
> >>
> >> and tcrypt,
> >> sudo modprobe tcrypt mode=329 sec=1
> >>
> >> Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
> >> ---
> >> Kamlesh Gurudasani (5):
> >> crypto: crc64 - add crc64-iso test vectors
> >> dt-bindings: crypto: Add binding for TI MCRC64 driver
> >> crypto: ti - add driver for MCRC64 engine
> >> arm64: dts: ti: k3-am62: Add dt node, cbass_main ranges for MCRC64
> >> arm64: defconfig: enable MCRC module
> >>
> >> Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml | 42 +++++++
> >> MAINTAINERS | 7 ++
> >> arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 7 ++
> >> arch/arm64/boot/dts/ti/k3-am62.dtsi | 1 +
> >> arch/arm64/configs/defconfig | 2 +
> >> crypto/tcrypt.c | 5 +
> >> crypto/testmgr.c | 7 ++
> >> crypto/testmgr.h | 401 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> >> drivers/crypto/Kconfig | 1 +
> >> drivers/crypto/Makefile | 1 +
> >> drivers/crypto/ti/Kconfig | 10 ++
> >> drivers/crypto/ti/Makefile | 2 +
> >> drivers/crypto/ti/mcrc64.c | 360 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> >> 13 files changed, 846 insertions(+)
> >> ---
> >> base-commit: d7b3af5a77e8d8da28f435f313e069aea5bcf172
> >> change-id: 20230719-mcrc-upstream-7ae9a75cab37
> >>
> >> Best regards,
> >> --
> >> Kamlesh Gurudasani <kamlesh@ti.com>
> >>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [EXTERNAL] Re: [EXTERNAL] Re: [PATCH 0/5] Add support for Texas Instruments MCRC64 engine
2023-08-01 6:42 ` Ard Biesheuvel
@ 2023-08-01 7:02 ` Kamlesh Gurudasani
0 siblings, 0 replies; 14+ messages in thread
From: Kamlesh Gurudasani @ 2023-08-01 7:02 UTC (permalink / raw
To: Ard Biesheuvel
Cc: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Menon, Nishanth, Raghavendra, Vignesh, Tero Kristo,
Catalin Marinas, Will Deacon, linux-crypto@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Ard Biesheuvel <ardb@kernel.org> writes:
> On Tue, 1 Aug 2023 at 08:22, Kamlesh Gurudasani <kamlesh@ti.com> wrote:
>>
>> Ard Biesheuvel <ardb@kernel.org> writes:
>>
>> > On Sun, 30 Jul 2023 at 20:56, Kamlesh Gurudasani <kamlesh@ti.com> wrote:
>> >>
>> >> Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode
>> >>
>> >> MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
>> >> according to the ISO 3309 standard.
>> >>
>> >> Generator polynomial: x^64 + x^4 + x^3 + x + 1
>> >> Polynomial value: 0x000000000000001b
>> >>
>> >
>> > How will this code be used? WIthout a user of the crc64-iso crypto API
>> > algorithm, there is no point in having a driver that implements it.
>>
>> Thanks for the review.
>>
>> MCRC64 will be used to check the integrity of memory blocks.
>> On TI K3 SOCs, users can use MCRC64 to accelerate the integrity check.
>>
>
> Where is the implementation of this logic? Does it use the shash/ahash API?
>
> If so, it should be part of this series.
We have implemented user-space application to utilize crc64-iso using below kernel module
algif_hash: User-space interface for hash algorithms
https://gist.github.com/ti-kamlesh/73abfcc1a33318bb3b199d36b6209e59
>
>
>> >
>> > Also, *if* such a user exists, we'd need to have a generic C
>> > implementation as well - we don't add new algorithms unless they can
>> > be enabled on all platforms and architectures.
>>
>> If it is must, will implement generic C code.
>>
>> >
>> >
>> >> Tested with
>> >>
>> >> and tcrypt,
>> >> sudo modprobe tcrypt mode=329 sec=1
>> >>
>> >> Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
>> >> ---
>> >> Kamlesh Gurudasani (5):
>> >> crypto: crc64 - add crc64-iso test vectors
>> >> dt-bindings: crypto: Add binding for TI MCRC64 driver
>> >> crypto: ti - add driver for MCRC64 engine
>> >> arm64: dts: ti: k3-am62: Add dt node, cbass_main ranges for MCRC64
>> >> arm64: defconfig: enable MCRC module
>> >>
>> >> Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml | 42 +++++++
>> >> MAINTAINERS | 7 ++
>> >> arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 7 ++
>> >> arch/arm64/boot/dts/ti/k3-am62.dtsi | 1 +
>> >> arch/arm64/configs/defconfig | 2 +
>> >> crypto/tcrypt.c | 5 +
>> >> crypto/testmgr.c | 7 ++
>> >> crypto/testmgr.h | 401 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>> >> drivers/crypto/Kconfig | 1 +
>> >> drivers/crypto/Makefile | 1 +
>> >> drivers/crypto/ti/Kconfig | 10 ++
>> >> drivers/crypto/ti/Makefile | 2 +
>> >> drivers/crypto/ti/mcrc64.c | 360 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>> >> 13 files changed, 846 insertions(+)
>> >> ---
>> >> base-commit: d7b3af5a77e8d8da28f435f313e069aea5bcf172
>> >> change-id: 20230719-mcrc-upstream-7ae9a75cab37
>> >>
>> >> Best regards,
>> >> --
>> >> Kamlesh Gurudasani <kamlesh@ti.com>
>> >>
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2023-08-01 7:03 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-07-30 18:55 [PATCH 0/5] Add support for Texas Instruments MCRC64 engine Kamlesh Gurudasani
2023-07-30 18:55 ` [PATCH 1/5] crypto: crc64 - add crc64-iso test vectors Kamlesh Gurudasani
2023-07-30 18:55 ` [PATCH 2/5] dt-bindings: crypto: Add binding for TI MCRC64 driver Kamlesh Gurudasani
2023-07-30 19:15 ` Krzysztof Kozlowski
2023-07-30 19:28 ` Rob Herring
2023-07-30 18:55 ` [PATCH 3/5] crypto: ti - add driver for MCRC64 engine Kamlesh Gurudasani
2023-07-30 19:18 ` Krzysztof Kozlowski
2023-07-31 17:50 ` Ard Biesheuvel
2023-07-30 18:55 ` [PATCH 4/5] arm64: dts: ti: k3-am62: Add dt node, cbass_main ranges for MCRC64 Kamlesh Gurudasani
2023-07-30 18:55 ` [PATCH 5/5] arm64: defconfig: enable MCRC module Kamlesh Gurudasani
2023-07-31 17:48 ` [PATCH 0/5] Add support for Texas Instruments MCRC64 engine Ard Biesheuvel
2023-08-01 6:22 ` [EXTERNAL] " Kamlesh Gurudasani
2023-08-01 6:42 ` Ard Biesheuvel
2023-08-01 7:02 ` [EXTERNAL] " Kamlesh Gurudasani
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