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Wed, 24 Apr 2024 16:39:52 -0700 (PDT) Received: from ziepe.ca ([12.97.180.36]) by smtp.gmail.com with ESMTPSA id pv10-20020a0568709d8a00b0023b50a85913sm78072oab.38.2024.04.24.16.39.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Apr 2024 16:39:51 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.95) (envelope-from ) id 1rzmDO-00A1fN-HT; Wed, 24 Apr 2024 20:39:50 -0300 Date: Wed, 24 Apr 2024 20:39:50 -0300 From: Jason Gunthorpe To: Tomasz Jeznach Cc: Joerg Roedel , Will Deacon , Robin Murphy , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Sunil V L , Nick Kossifidis , Sebastien Boeuf , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, iommu@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux@rivosinc.com Subject: Re: [PATCH v2 7/7] iommu/riscv: Paging domain support Message-ID: <20240424233950.GJ231144@ziepe.ca> References: <301244bc3ff5da484b46d3fecc931cdad7d2806f.1713456598.git.tjeznach@rivosinc.com> <20240419125627.GD223006@ziepe.ca> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, Apr 24, 2024 at 04:30:45PM -0700, Tomasz Jeznach wrote: > > > @@ -46,6 +46,10 @@ MODULE_LICENSE("GPL"); > > > #define dev_to_iommu(dev) \ > > > container_of((dev)->iommu->iommu_dev, struct riscv_iommu_device, iommu) > > > > > > +/* IOMMU PSCID allocation namespace. */ > > > +static DEFINE_IDA(riscv_iommu_pscids); > > > +#define RISCV_IOMMU_MAX_PSCID BIT(20) > > > + > > > > You may consider putting this IDA in the riscv_iommu_device() and move > > the pscid from the domain to the bond? > > > > I've been considering containing IDA inside riscv_iommu_device at some > point, but it made PCSID management more complicated. In the follow > up patches it is desired for PSCID to be unique across all IOMMUs in > the system (within guest's GSCID), as the protection domains might > (and will) be shared between more than single IOMMU device. The PCSID isn't scoped under the GSCID? That doesn't sound very good, it means VM's can't direct issue invalidation with their local view of the PCSID space? > > This seems suboptimal, you probably want to copy the new design that > > Intel is doing where you allocate "bonds" that are already > > de-duplicated. Ie if I have 10 devices on the same iommu sharing the > > domain the above will invalidate the PSCID 10 times. It should only be > > done once. > > > > ie add a "bond" for the (iommu,pscid) and refcount that based on how > > many devices are used. Then another "bond" for the ATS stuff eventually. > > > > Agree, not perfect to send duplicate invalidations. > This should improve with follow up patchsets introducing of SVA > (reusing the same, extended bond structure) and update to send IOTLB > range invalidations. > > For this change I've decided to go with as simple as possible > implementation and over-invalidate for domains with multiple devices > attached. Hope this makes sense. It is fine as long as you do fix it.. Jason