From: Conor Dooley <conor@kernel.org>
To: Charlie Jenkins <charlie@rivosinc.com>
Cc: "Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
"Palmer Dabbelt" <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v3 04/17] riscv: vector: Use vlenb from DT
Date: Fri, 26 Apr 2024 16:17:52 +0100 [thread overview]
Message-ID: <20240426-unfocused-amount-e4e74e66962f@spud> (raw)
In-Reply-To: <20240420-dev-charlie-support_thead_vector_6_9-v3-4-67cff4271d1d@rivosinc.com>
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On Sat, Apr 20, 2024 at 06:04:36PM -0700, Charlie Jenkins wrote:
> If vlenb is provided in the device tree, prefer that over reading the
> vlenb csr.
>
> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> ---
> arch/riscv/include/asm/cpufeature.h | 2 ++
> arch/riscv/kernel/cpufeature.c | 26 ++++++++++++++++++++++++++
> arch/riscv/kernel/vector.c | 13 +++++++++----
> 3 files changed, 37 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> index 347805446151..809f61ffb667 100644
> --- a/arch/riscv/include/asm/cpufeature.h
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
> /* Per-cpu ISA extensions. */
> extern struct riscv_isainfo hart_isa[NR_CPUS];
>
> +extern u32 riscv_vlenb_dt[NR_CPUS];
> +
> void riscv_user_isa_enable(void);
>
> #if defined(CONFIG_RISCV_MISALIGNED)
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index c6e27b45e192..48874aac4871 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -35,6 +35,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
> /* Per-cpu ISA extensions. */
> struct riscv_isainfo hart_isa[NR_CPUS];
>
> +u32 riscv_vlenb_dt[NR_CPUS];
> +
> /**
> * riscv_isa_extension_base() - Get base extension word
> *
> @@ -656,6 +658,28 @@ static int __init riscv_isa_fallback_setup(char *__unused)
> early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
> #endif
>
> +static void riscv_set_vlenb_from_dt(void)
I'd expect to see a name here that had "of" in it, not "dt".
> +{
> + int cpu;
> +
> + for_each_possible_cpu(cpu) {
> + struct device_node *cpu_node;
> +
> + cpu_node = of_cpu_device_node_get(cpu);
> + if (!cpu_node) {
> + pr_warn("Unable to find cpu node\n");
> + continue;
> + }
> +
> + if (!of_property_read_u32(cpu_node, "riscv,vlenb", &riscv_vlenb_dt[cpu])) {
> + of_node_put(cpu_node);
> + continue;
> + }
> +
> + of_node_put(cpu_node);
> + }
> +}
> +
> void __init riscv_fill_hwcap(void)
> {
> char print_str[NUM_ALPHA_EXTS + 1];
> @@ -675,6 +699,8 @@ void __init riscv_fill_hwcap(void)
> } else {
> int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap);
>
> + riscv_set_vlenb_from_dt();
Hmm, I think we can go a step further here. We know all of the CPUs
widths by the time we get to the first call to riscv_v_setup_vsize(), can
we examine the whole list and decide not to enable vector if they do
not match, rather than continuing and failing to online CPUs that having
the mismatched size?
I guess that can go into the `if (elf_hwcap & COMPAT_HWCAP_ISA_V)`
condition we already have, and would require clearing the bit from the
mask we have at the moment.
Cheers,
Conor.
> +
> if (ret && riscv_isa_fallback) {
> pr_info("Falling back to deprecated \"riscv,isa\"\n");
> riscv_fill_hwcap_from_isa_string(isa2hwcap);
> diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
> index 6727d1d3b8f2..fb7f3ca80d9e 100644
> --- a/arch/riscv/kernel/vector.c
> +++ b/arch/riscv/kernel/vector.c
> @@ -32,11 +32,16 @@ EXPORT_SYMBOL_GPL(riscv_v_vsize);
> int riscv_v_setup_vsize(void)
> {
> unsigned long this_vsize;
> + int cpu = smp_processor_id();
>
> - /* There are 32 vector registers with vlenb length. */
> - riscv_v_enable();
> - this_vsize = csr_read(CSR_VLENB) * 32;
> - riscv_v_disable();
> + if (riscv_vlenb_dt[cpu]) {
> + this_vsize = riscv_vlenb_dt[cpu];
> + } else {
> + /* There are 32 vector registers with vlenb length. */
> + riscv_v_enable();
> + this_vsize = csr_read(CSR_VLENB) * 32;
> + riscv_v_disable();
> + }
>
> if (!riscv_v_vsize) {
> riscv_v_vsize = this_vsize;
>
> --
> 2.44.0
>
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next prev parent reply other threads:[~2024-04-26 15:17 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-21 1:04 [PATCH v3 00/17] riscv: Support vendor extensions and xtheadvector Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 01/17] riscv: cpufeature: Fix thead vector hwcap removal Charlie Jenkins
2024-04-26 8:15 ` Guo Ren
2024-04-21 1:04 ` [PATCH v3 02/17] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 03/17] dt-bindings: riscv: cpus: add a vlen register length property Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 04/17] riscv: vector: Use vlenb from DT Charlie Jenkins
2024-04-26 15:17 ` Conor Dooley [this message]
2024-04-26 16:21 ` Conor Dooley
2024-04-26 17:03 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 05/17] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 06/17] riscv: Fix extension subset checking Charlie Jenkins
2024-04-24 14:22 ` Alexandre Ghiti
2024-04-24 14:51 ` Conor Dooley
2024-04-24 15:13 ` Charlie Jenkins
2024-04-24 15:21 ` Conor Dooley
2024-04-24 15:36 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 07/17] riscv: Extend cpufeature.c to detect vendor extensions Charlie Jenkins
2024-04-26 16:00 ` Conor Dooley
2024-04-26 18:00 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 08/17] riscv: Introduce vendor variants of extension helpers Charlie Jenkins
2024-04-26 16:19 ` Conor Dooley
2024-04-26 20:01 ` Charlie Jenkins
2024-04-26 20:37 ` Conor Dooley
2024-04-21 1:04 ` [PATCH v3 09/17] riscv: drivers: Convert xandespmu to use the vendor extension framework Charlie Jenkins
2024-04-26 16:25 ` Conor Dooley
2024-04-26 20:34 ` Charlie Jenkins
2024-04-26 20:46 ` Conor Dooley
2024-04-21 1:04 ` [PATCH v3 10/17] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 11/17] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 12/17] riscv: Add xtheadvector instruction definitions Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 13/17] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 14/17] riscv: hwprobe: Add thead vendor extension probing Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 15/17] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 16/17] selftests: riscv: Fix vector tests Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 17/17] selftests: riscv: Support xtheadvector in " Charlie Jenkins
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