From: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
To: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Greg KH <greg@kroah.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Krishna Kurapati <quic_kriskura@quicinc.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Linux Next Mailing List <linux-next@vger.kernel.org>,
Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Subject: Re: linux-next: manual merge of the usb tree with the usb.current tree
Date: Fri, 26 Apr 2024 21:39:27 +0000 [thread overview]
Message-ID: <20240426213923.tyeddub4xszypeju@synopsys.com> (raw)
In-Reply-To: <20240426144848.42539084@canb.auug.org.au>
Hi Stephen,
On Fri, Apr 26, 2024, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the usb tree got a conflict in:
>
> drivers/usb/dwc3/core.c
>
> between commit:
>
> 6d735722063a ("usb: dwc3: core: Prevent phy suspend during init")
>
> from the usb.current tree and commit:
>
> 30a46746ca5a ("usb: dwc3: core: Refactor PHY logic to support Multiport Controller")
>
> from the usb tree.
>
> I fixed it up (I think - see below) and can carry the fix as
> necessary. This is now fixed as far as linux-next is concerned, but any
> non trivial conflicts should be mentioned to your upstream maintainer
> when your tree is submitted for merging. You may also want to consider
> cooperating with the maintainer of the conflicting tree to minimise any
> particularly complex conflicts.
>
> --
> Cheers,
> Stephen Rothwell
>
> diff --cc drivers/usb/dwc3/core.c
> index 100041320e8d,4dc6fc79c6d9..000000000000
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@@ -104,27 -105,6 +105,30 @@@ static int dwc3_get_dr_mode(struct dwc
> return 0;
> }
>
> +void dwc3_enable_susphy(struct dwc3 *dwc, bool enable)
> +{
> + u32 reg;
> ++ int i;
> +
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
> - if (enable && !dwc->dis_u3_susphy_quirk)
> - reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> - else
> - reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
> ++ for (i = 0; i < dwc->num_usb3_ports; i++) {
> ++ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i));
> ++ if (enable && !dwc->dis_u3_susphy_quirk)
> ++ reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> ++ else
> ++ reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
> ++ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg);
> ++ }
> +
> - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
> -
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
> - if (enable && !dwc->dis_u2_susphy_quirk)
> - reg |= DWC3_GUSB2PHYCFG_SUSPHY;
> - else
> - reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
> -
> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
> ++ for (i = 0; i < dwc->num_usb2_ports; i++) {
> ++ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
> ++ if (enable && !dwc->dis_u2_susphy_quirk)
> ++ reg |= DWC3_GUSB2PHYCFG_SUSPHY;
> ++ else
> ++ reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
> ++ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
> ++ }
> +}
> +
> void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
> {
> u32 reg;
> @@@ -596,19 -594,14 +618,11 @@@ static int dwc3_core_ulpi_init(struct d
> return ret;
> }
>
> - /**
> - * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
> - * @dwc: Pointer to our controller context structure
> - *
> - * Returns 0 on success. The USB PHY interfaces are configured but not
> - * initialized. The PHY interfaces and the PHYs get initialized together with
> - * the core in dwc3_core_init.
> - */
> - static int dwc3_phy_setup(struct dwc3 *dwc)
> + static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index)
> {
> - unsigned int hw_mode;
> u32 reg;
>
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
> - hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
> -
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index));
>
> /*
> * Make sure UX_EXIT_PX is cleared as that causes issues with some
Thanks for reporting. There's a slight adjustment to remove hw_mode that
was missed for dwc3_hs_phy_setup(). It should look more like this:
diff --cc drivers/usb/dwc3/core.c
index edb0a6aa1f9f,4dc6fc79c6d9..000000000000
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@@ -105,27 -105,6 +105,32 @@@ static int dwc3_get_dr_mode(struct dwc
return 0;
}
+void dwc3_enable_susphy(struct dwc3 *dwc, bool enable)
+{
+ u32 reg;
++ int i;
+
- reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
- if (enable && !dwc->dis_u3_susphy_quirk)
- reg |= DWC3_GUSB3PIPECTL_SUSPHY;
- else
- reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
++ for (i = 0; i < dwc->num_usb3_ports; i++) {
++ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i));
++ if (enable && !dwc->dis_u3_susphy_quirk)
++ reg |= DWC3_GUSB3PIPECTL_SUSPHY;
++ else
++ reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
+
- dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
++ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg);
++ }
+
- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
- if (enable && !dwc->dis_u2_susphy_quirk)
- reg |= DWC3_GUSB2PHYCFG_SUSPHY;
- else
- reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
++ for (i = 0; i < dwc->num_usb2_ports; i++) {
++ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
++ if (enable && !dwc->dis_u2_susphy_quirk)
++ reg |= DWC3_GUSB2PHYCFG_SUSPHY;
++ else
++ reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
+
- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
++ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
++ }
+}
+
void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
{
u32 reg;
@@@ -610,19 -594,14 +620,11 @@@ static int dwc3_core_ulpi_init(struct d
return ret;
}
- /**
- * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
- * @dwc: Pointer to our controller context structure
- *
- * Returns 0 on success. The USB PHY interfaces are configured but not
- * initialized. The PHY interfaces and the PHYs get initialized together with
- * the core in dwc3_core_init.
- */
- static int dwc3_phy_setup(struct dwc3 *dwc)
+ static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index)
{
- unsigned int hw_mode;
u32 reg;
- reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
- hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
-
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index));
/*
* Make sure UX_EXIT_PX is cleared as that causes issues with some
@@@ -669,9 -653,22 +671,16 @@@
if (dwc->dis_del_phy_power_chg_quirk)
reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
- dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg);
- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
+ return 0;
+ }
+
+ static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index)
+ {
- unsigned int hw_mode;
+ u32 reg;
+
- hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
-
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index));
/* Select the HS PHY interface */
switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
--
Thanks,
Thinh
next prev parent reply other threads:[~2024-04-26 21:39 UTC|newest]
Thread overview: 87+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-26 4:48 linux-next: manual merge of the usb tree with the usb.current tree Stephen Rothwell
2024-04-26 21:39 ` Thinh Nguyen [this message]
-- strict thread matches above, loose matches on Subject: below --
2024-04-12 4:25 Stephen Rothwell
2024-04-12 7:58 ` Greg KH
2024-04-24 6:12 ` Stephen Rothwell
2024-04-30 16:11 ` Greg KH
2024-02-20 3:39 Stephen Rothwell
2024-02-20 8:18 ` Greg KH
2024-02-26 5:55 ` Greg KH
2023-05-15 2:50 Stephen Rothwell
2023-05-28 14:28 ` Greg KH
2023-05-15 2:35 Stephen Rothwell
2023-05-15 3:50 ` Greg KH
2023-05-15 5:22 ` Krishna Kurapati PSSNV
2023-05-15 11:01 ` Roger Quadros
2023-05-15 11:36 ` Stephen Rothwell
2023-05-28 14:28 ` Greg KH
2023-05-28 15:48 ` Roger Quadros
2023-05-28 16:07 ` Greg KH
2023-03-31 3:01 Stephen Rothwell
2023-03-31 7:52 ` Greg KH
2023-04-10 6:56 ` Greg KH
2023-01-19 3:48 Stephen Rothwell
2023-01-18 0:56 Stephen Rothwell
2023-01-18 7:48 ` Greg KH
2023-01-23 14:40 ` Greg KH
2022-09-01 3:52 Stephen Rothwell
2022-09-05 6:04 ` Greg KH
2022-04-26 5:08 Stephen Rothwell
2022-04-26 9:41 ` Greg KH
2022-05-03 14:36 ` Greg KH
2022-02-21 20:39 broonie
2022-02-22 7:44 ` Greg KH
2021-07-22 4:12 Stephen Rothwell
2021-07-23 12:29 ` Greg KH
2021-07-27 14:45 ` Greg KH
2021-01-20 2:06 Stephen Rothwell
2021-01-20 8:02 ` Greg KH
2021-01-06 0:50 Stephen Rothwell
2021-01-11 7:11 ` Greg KH
2020-06-26 3:29 Stephen Rothwell
2020-06-26 15:14 ` Greg KH
2020-06-29 6:23 ` Greg KH
2018-06-29 4:57 Stephen Rothwell
2018-07-01 8:43 ` Greg KH
2018-07-01 15:11 ` Randy Dunlap
2018-04-23 3:04 Stephen Rothwell
2018-04-23 8:30 ` Johan Hovold
2018-04-23 8:41 ` Greg KH
2018-04-30 1:34 ` Stephen Rothwell
2018-04-30 11:55 ` Sebastian Reichel
2018-04-30 12:16 ` Greg KH
2018-04-30 12:00 ` Greg KH
2017-12-20 2:09 Stephen Rothwell
2017-12-20 9:36 ` Greg KH
2018-01-03 0:56 ` Stephen Rothwell
2018-01-04 16:06 ` Greg KH
2014-11-05 4:18 Stephen Rothwell
2014-11-05 4:30 ` Greg KH
2014-11-05 8:33 ` Paul Bolle
2014-11-06 2:19 ` Greg KH
2014-11-06 5:02 ` Stephen Rothwell
2013-12-18 5:53 Stephen Rothwell
2013-03-21 4:24 Stephen Rothwell
2012-11-14 4:07 Stephen Rothwell
2012-11-16 2:14 ` Greg KH
2012-11-13 3:37 Stephen Rothwell
2012-11-13 18:49 ` Greg KH
2012-10-25 2:05 Stephen Rothwell
2012-10-25 2:17 ` Greg KH
2012-09-12 5:37 Stephen Rothwell
2012-09-12 16:14 ` Greg KH
2012-09-12 5:37 Stephen Rothwell
2012-05-03 4:44 Stephen Rothwell
2012-05-04 23:18 ` Greg KH
2012-05-07 16:05 ` Greg KH
2012-05-07 16:05 ` Greg KH
2012-04-19 5:14 Stephen Rothwell
2012-04-19 20:07 ` Greg KH
2012-04-22 22:27 ` Greg KH
2012-03-05 6:00 Stephen Rothwell
2012-03-05 16:42 ` Greg KH
2011-08-25 4:52 Stephen Rothwell
2011-08-25 15:39 ` Greg KH
2011-08-29 15:52 ` Greg KH
2010-12-20 5:28 Stephen Rothwell
2010-12-20 18:30 ` Greg KH
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