* [PATCH v3 0/4] mips: bmips: improve handling of RAC and CBR addr
@ 2024-05-08 17:07 Christian Marangi
2024-05-08 17:07 ` [PATCH v3 1/4] mips: bmips: rework and cache CBR addr handling Christian Marangi
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Christian Marangi @ 2024-05-08 17:07 UTC (permalink / raw
To: Hauke Mehrtens, Rafał Miłecki, Thomas Bogendoerfer,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Florian Fainelli,
Broadcom internal kernel review list, Christian Marangi,
linux-mips, devicetree, linux-kernel
Hi,
this simple series improve handling of RAC and CBR address and try to
upstream these simple patch we have in OpenWrt for a while.
The first patch fix a straight kernel panic where some Bootloader might
enable RAC but misconfigure the CBR address. The current logic only
check if RAC is enabled but doesn't verify if the CBR address is usable.
The DMA sync function cause a kernel panic for invalid write. (as CBR is
0 or something like 0xa)
The second is preparation for making the CBR address configurable in DT.
Since this address doesn't change, we can cache it and reference it with
a local variable instead of calling the register to access the value.
The 4th patch make it configurable with 2 DT property, one to actually
set the reg and the other to force set it.
The first property is used when CBR is set to 0. The second property is
to force it if the Bootloader sets it to something wrong.
If the CBR value is not 0 and is not forced with the second property a
WARN is printed and the DT value is ignored.
The 4th patch enable RAC on BMIPS4350.
These has been tested on BCM6358 (HG556a) and BCM6368 (VH4032N) and
reported correct functionality.
Changes v3:
- Drop broken-cbr-reg property
- Fix anyOf+const with enum
Changes v2:
- Prefix brcm vendor in the added property
- Drop last patch (cpu switch from DMA sync)
- Validate CBR addr from DT to be outside DRAM
- Reduce indentation in DT CBR check
- Reduce delta and use local variable for CBR where possible
- Fix and improve typo and spelling mistake
- Use 0xf instead of 0xa for BCM6358 RAC enable
Christian Marangi (3):
mips: bmips: rework and cache CBR addr handling
dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property
mips: bmips: setup: make CBR address configurable
Daniel González Cabanelas (1):
mips: bmips: enable RAC on BMIPS4350
.../devicetree/bindings/mips/brcm/soc.yaml | 23 +++++++++++++
arch/mips/bmips/dma.c | 2 +-
arch/mips/bmips/setup.c | 34 +++++++++++++++++--
arch/mips/include/asm/bmips.h | 1 +
arch/mips/kernel/smp-bmips.c | 21 ++++++++++--
5 files changed, 76 insertions(+), 5 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 1/4] mips: bmips: rework and cache CBR addr handling
2024-05-08 17:07 [PATCH v3 0/4] mips: bmips: improve handling of RAC and CBR addr Christian Marangi
@ 2024-05-08 17:07 ` Christian Marangi
2024-05-08 17:07 ` [PATCH v3 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property Christian Marangi
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: Christian Marangi @ 2024-05-08 17:07 UTC (permalink / raw
To: Hauke Mehrtens, Rafał Miłecki, Thomas Bogendoerfer,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Florian Fainelli,
Broadcom internal kernel review list, Christian Marangi,
linux-mips, devicetree, linux-kernel
Rework the handling of the CBR address and cache it. This address
doesn't change and can be cached instead of reading the register every
time.
This is in preparation of permitting to tweak the CBR address in DT with
broken SoC or bootloader.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
---
arch/mips/bmips/dma.c | 2 +-
arch/mips/bmips/setup.c | 6 +++++-
arch/mips/include/asm/bmips.h | 1 +
arch/mips/kernel/smp-bmips.c | 4 ++--
4 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/mips/bmips/dma.c b/arch/mips/bmips/dma.c
index 3779e7855bd7..2bc9c0d4402f 100644
--- a/arch/mips/bmips/dma.c
+++ b/arch/mips/bmips/dma.c
@@ -9,7 +9,7 @@ bool bmips_rac_flush_disable;
void arch_sync_dma_for_cpu_all(void)
{
- void __iomem *cbr = BMIPS_GET_CBR();
+ void __iomem *cbr = bmips_cbr_addr;
u32 cfg;
if (boot_cpu_type() != CPU_BMIPS3300 &&
diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c
index 66a8ba19c287..5e024399222f 100644
--- a/arch/mips/bmips/setup.c
+++ b/arch/mips/bmips/setup.c
@@ -34,6 +34,8 @@
#define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
#define BCM6328_TP1_DISABLED BIT(9)
+/* CBR addr doesn't change and we can cache it */
+void __iomem *bmips_cbr_addr __ro_after_init __read_mostly;
extern bool bmips_rac_flush_disable;
static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
@@ -111,7 +113,7 @@ static void bcm6358_quirks(void)
* because the bootloader is not initializing it properly.
*/
bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) ||
- !!BMIPS_GET_CBR();
+ !!bmips_cbr_addr;
}
static void bcm6368_quirks(void)
@@ -144,6 +146,8 @@ static void __init bmips_init_cfe(void)
void __init prom_init(void)
{
+ /* Cache CBR addr before CPU/DMA setup */
+ bmips_cbr_addr = BMIPS_GET_CBR();
bmips_init_cfe();
bmips_cpu_setup();
register_bmips_smp_ops();
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index 581a6a3c66e4..3a1cdfddb987 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -81,6 +81,7 @@ extern char bmips_smp_movevec[];
extern char bmips_smp_int_vec[];
extern char bmips_smp_int_vec_end[];
+extern void __iomem *bmips_cbr_addr;
extern int bmips_smp_enabled;
extern int bmips_cpu_offset;
extern cpumask_t bmips_booted_mask;
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index b3dbf9ecb0d6..a4f84667a901 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -518,7 +518,7 @@ static void bmips_set_reset_vec(int cpu, u32 val)
info.val = val;
bmips_set_reset_vec_remote(&info);
} else {
- void __iomem *cbr = BMIPS_GET_CBR();
+ void __iomem *cbr = bmips_cbr_addr;
if (cpu == 0)
__raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
@@ -591,7 +591,7 @@ asmlinkage void __weak plat_wired_tlb_setup(void)
void bmips_cpu_setup(void)
{
- void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
+ void __iomem __maybe_unused *cbr = bmips_cbr_addr;
u32 __maybe_unused cfg;
switch (current_cpu_type()) {
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property
2024-05-08 17:07 [PATCH v3 0/4] mips: bmips: improve handling of RAC and CBR addr Christian Marangi
2024-05-08 17:07 ` [PATCH v3 1/4] mips: bmips: rework and cache CBR addr handling Christian Marangi
@ 2024-05-08 17:07 ` Christian Marangi
2024-05-08 17:14 ` Conor Dooley
2024-05-08 17:07 ` [PATCH v3 3/4] mips: bmips: setup: make CBR address configurable Christian Marangi
2024-05-08 17:07 ` [PATCH v3 4/4] mips: bmips: enable RAC on BMIPS4350 Christian Marangi
3 siblings, 1 reply; 8+ messages in thread
From: Christian Marangi @ 2024-05-08 17:07 UTC (permalink / raw
To: Hauke Mehrtens, Rafał Miłecki, Thomas Bogendoerfer,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Florian Fainelli,
Broadcom internal kernel review list, Christian Marangi,
linux-mips, devicetree, linux-kernel
Document brcm,bmips-cbr-reg property.
Some SoC suffer from a BUG where read_c0_brcm_cbr() might return 0
if called from TP1. The CBR address is always the same on the SoC
hence it can be provided in DT to handle broken case where bootloader
doesn't init it or SMP where read_c0_brcm_cbr() returns 0 from TP1.
Usage of this property is to give an address also in these broken
configuration/bootloader.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
.../devicetree/bindings/mips/brcm/soc.yaml | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
index 975945ca2888..77f73ab48c11 100644
--- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml
+++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
@@ -55,6 +55,15 @@ properties:
under the "cpus" node.
$ref: /schemas/types.yaml#/definitions/uint32
+ brcm,bmips-cbr-reg:
+ description: Reference address of the CBR.
+ Some SoC suffer from a BUG where read_c0_brcm_cbr() might
+ return 0 if called from TP1. The CBR address is always the
+ same on the SoC hence it can be provided in DT to handle
+ broken case where bootloader doesn't initialise it or SMP
+ where read_c0_brcm_cbr() returns 0 from TP1.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
patternProperties:
"^cpu@[0-9]$":
type: object
@@ -64,6 +73,20 @@ properties:
required:
- mips-hpt-frequency
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,bcm6358
+ - brcm,bcm6368
+
+then:
+ properties:
+ cpus:
+ required:
+ - brcm,bmips-cbr-reg
+
additionalProperties: true
examples:
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 3/4] mips: bmips: setup: make CBR address configurable
2024-05-08 17:07 [PATCH v3 0/4] mips: bmips: improve handling of RAC and CBR addr Christian Marangi
2024-05-08 17:07 ` [PATCH v3 1/4] mips: bmips: rework and cache CBR addr handling Christian Marangi
2024-05-08 17:07 ` [PATCH v3 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property Christian Marangi
@ 2024-05-08 17:07 ` Christian Marangi
2024-05-08 17:07 ` [PATCH v3 4/4] mips: bmips: enable RAC on BMIPS4350 Christian Marangi
3 siblings, 0 replies; 8+ messages in thread
From: Christian Marangi @ 2024-05-08 17:07 UTC (permalink / raw
To: Hauke Mehrtens, Rafał Miłecki, Thomas Bogendoerfer,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Florian Fainelli,
Broadcom internal kernel review list, Christian Marangi,
linux-mips, devicetree, linux-kernel
Add support to provide CBR address from DT to handle broken
SoC/Bootloader that doesn't correctly init it. This permits to use the
RAC flush even in these condition.
To provide a CBR address from DT, the property "brcm,bmips-cbr-reg"
needs to be set in the "cpus" node. On DT init, this property presence
will be checked and will set the bmips_cbr_addr value accordingly. Also
bmips_rac_flush_disable will be set to false as RAC flush can be
correctly supported.
The CBR address from DT will overwrite the cached one and the
one set in the CBR register will be ignored.
Also the DT CBR address is validated on being outside DRAM window.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/mips/bmips/setup.c | 30 ++++++++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c
index 5e024399222f..01463b2f125d 100644
--- a/arch/mips/bmips/setup.c
+++ b/arch/mips/bmips/setup.c
@@ -34,7 +34,11 @@
#define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
#define BCM6328_TP1_DISABLED BIT(9)
-/* CBR addr doesn't change and we can cache it */
+/*
+ * CBR addr doesn't change and we can cache it.
+ * For broken SoC/Bootloader CBR addr might also be provided via DT
+ * with "brcm,bmips-cbr-reg" in the "cpus" node.
+ */
void __iomem *bmips_cbr_addr __ro_after_init __read_mostly;
extern bool bmips_rac_flush_disable;
@@ -207,13 +211,35 @@ void __init plat_mem_setup(void)
void __init device_tree_init(void)
{
struct device_node *np;
+ u32 addr;
unflatten_and_copy_device_tree();
/* Disable SMP boot unless both CPUs are listed in DT and !disabled */
np = of_find_node_by_name(NULL, "cpus");
- if (np && of_get_available_child_count(np) <= 1)
+ if (!np)
+ return;
+
+ if (of_get_available_child_count(np) <= 1)
bmips_smp_enabled = 0;
+
+ /* Check if DT provide a CBR address */
+ if (of_property_read_u32(np, "brcm,bmips-cbr-reg", &addr))
+ goto exit;
+
+ /* Make sure CBR address is outside DRAM window */
+ if (addr >= (u32)memblock_start_of_DRAM() &&
+ addr < (u32)memblock_end_of_DRAM()) {
+ WARN(1, "DT CBR %x inside DRAM window. Ignoring DT CBR.\n",
+ addr);
+ goto exit;
+ }
+
+ bmips_cbr_addr = (void __iomem *)addr;
+ /* Since CBR is provided by DT, enable RAC flush */
+ bmips_rac_flush_disable = false;
+
+exit:
of_node_put(np);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 4/4] mips: bmips: enable RAC on BMIPS4350
2024-05-08 17:07 [PATCH v3 0/4] mips: bmips: improve handling of RAC and CBR addr Christian Marangi
` (2 preceding siblings ...)
2024-05-08 17:07 ` [PATCH v3 3/4] mips: bmips: setup: make CBR address configurable Christian Marangi
@ 2024-05-08 17:07 ` Christian Marangi
3 siblings, 0 replies; 8+ messages in thread
From: Christian Marangi @ 2024-05-08 17:07 UTC (permalink / raw
To: Hauke Mehrtens, Rafał Miłecki, Thomas Bogendoerfer,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Florian Fainelli,
Broadcom internal kernel review list, Christian Marangi,
linux-mips, devicetree, linux-kernel
Cc: Daniel González Cabanelas, Álvaro Fernández Rojas
From: Daniel González Cabanelas <dgcbueu@gmail.com>
The data RAC is left disabled by the bootloader in some SoCs, at least in
the core it boots from.
Enabling this feature increases the performance up to +30% depending on the
task.
Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
[ rework code and reduce code duplication ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
---
arch/mips/kernel/smp-bmips.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index a4f84667a901..0f93963c08e4 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -620,6 +620,23 @@ void bmips_cpu_setup(void)
__raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
break;
+ case CPU_BMIPS4350:
+ u32 rac_addr = BMIPS_RAC_CONFIG_1;
+
+ if (!(read_c0_brcm_cmt_local() & (1 << 31)))
+ rac_addr = BMIPS_RAC_CONFIG;
+
+ /* Enable data RAC */
+ cfg = __raw_readl(bmips_cbr_addr + rac_addr);
+ __raw_writel(cfg | 0xf, bmips_cbr_addr + rac_addr);
+ __raw_readl(bmips_cbr_addr + rac_addr);
+
+ /* Flush stale data out of the readahead cache */
+ cfg = __raw_readl(bmips_cbr_addr + BMIPS_RAC_CONFIG);
+ __raw_writel(cfg | 0x100, bmips_cbr_addr + BMIPS_RAC_CONFIG);
+ __raw_readl(bmips_cbr_addr + BMIPS_RAC_CONFIG);
+ break;
+
case CPU_BMIPS4380:
/* CBG workaround for early BMIPS4380 CPUs */
switch (read_c0_prid()) {
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property
2024-05-08 17:07 ` [PATCH v3 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property Christian Marangi
@ 2024-05-08 17:14 ` Conor Dooley
2024-05-08 17:17 ` Christian Marangi
0 siblings, 1 reply; 8+ messages in thread
From: Conor Dooley @ 2024-05-08 17:14 UTC (permalink / raw
To: Christian Marangi
Cc: Hauke Mehrtens, Rafał Miłecki, Thomas Bogendoerfer,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Florian Fainelli,
Broadcom internal kernel review list, linux-mips, devicetree,
linux-kernel
[-- Attachment #1: Type: text/plain, Size: 2437 bytes --]
On Wed, May 08, 2024 at 07:07:18PM +0200, Christian Marangi wrote:
> Document brcm,bmips-cbr-reg property.
>
> Some SoC suffer from a BUG where read_c0_brcm_cbr() might return 0
> if called from TP1. The CBR address is always the same on the SoC
> hence it can be provided in DT to handle broken case where bootloader
> doesn't init it or SMP where read_c0_brcm_cbr() returns 0 from TP1.
>
> Usage of this property is to give an address also in these broken
> configuration/bootloader.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
> .../devicetree/bindings/mips/brcm/soc.yaml | 23 +++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> index 975945ca2888..77f73ab48c11 100644
> --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> @@ -55,6 +55,15 @@ properties:
> under the "cpus" node.
> $ref: /schemas/types.yaml#/definitions/uint32
>
> + brcm,bmips-cbr-reg:
> + description: Reference address of the CBR.
Pretty sure that Rob commented last time that there's no definition
anywhere here of CBR, but I don't see either a response to him or an
explanation in v3 as to what CBR means.
> + Some SoC suffer from a BUG where read_c0_brcm_cbr() might
> + return 0 if called from TP1. The CBR address is always the
> + same on the SoC hence it can be provided in DT to handle
> + broken case where bootloader doesn't initialise it or SMP
> + where read_c0_brcm_cbr() returns 0 from TP1.
Why is a ?linux? function name in the binding? Surely this is just
"or in SMP systems where reading CBR returns 0 from...", no? Ditto
above.
Thanks,
Conor.
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> patternProperties:
> "^cpu@[0-9]$":
> type: object
> @@ -64,6 +73,20 @@ properties:
> required:
> - mips-hpt-frequency
>
> +if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - brcm,bcm6358
> + - brcm,bcm6368
> +
> +then:
> + properties:
> + cpus:
> + required:
> + - brcm,bmips-cbr-reg
> +
> additionalProperties: true
>
> examples:
> --
> 2.43.0
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property
2024-05-08 17:14 ` Conor Dooley
@ 2024-05-08 17:17 ` Christian Marangi
2024-05-09 16:01 ` Florian Fainelli
0 siblings, 1 reply; 8+ messages in thread
From: Christian Marangi @ 2024-05-08 17:17 UTC (permalink / raw
To: Conor Dooley
Cc: Hauke Mehrtens, Rafał Miłecki, Thomas Bogendoerfer,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Florian Fainelli,
Broadcom internal kernel review list, linux-mips, devicetree,
linux-kernel
On Wed, May 08, 2024 at 06:14:34PM +0100, Conor Dooley wrote:
> On Wed, May 08, 2024 at 07:07:18PM +0200, Christian Marangi wrote:
> > Document brcm,bmips-cbr-reg property.
> >
> > Some SoC suffer from a BUG where read_c0_brcm_cbr() might return 0
> > if called from TP1. The CBR address is always the same on the SoC
> > hence it can be provided in DT to handle broken case where bootloader
> > doesn't init it or SMP where read_c0_brcm_cbr() returns 0 from TP1.
> >
> > Usage of this property is to give an address also in these broken
> > configuration/bootloader.
> >
> > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> > ---
> > .../devicetree/bindings/mips/brcm/soc.yaml | 23 +++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> > index 975945ca2888..77f73ab48c11 100644
> > --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> > +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> > @@ -55,6 +55,15 @@ properties:
> > under the "cpus" node.
> > $ref: /schemas/types.yaml#/definitions/uint32
> >
> > + brcm,bmips-cbr-reg:
> > + description: Reference address of the CBR.
>
> Pretty sure that Rob commented last time that there's no definition
> anywhere here of CBR, but I don't see either a response to him or an
> explanation in v3 as to what CBR means.
>
Sorry I missed it.
> > + Some SoC suffer from a BUG where read_c0_brcm_cbr() might
> > + return 0 if called from TP1. The CBR address is always the
> > + same on the SoC hence it can be provided in DT to handle
> > + broken case where bootloader doesn't initialise it or SMP
> > + where read_c0_brcm_cbr() returns 0 from TP1.
>
> Why is a ?linux? function name in the binding? Surely this is just
> "or in SMP systems where reading CBR returns 0 from...", no? Ditto
> above.
>
It's really just a reference to reading c0 register at an offset, that
is why I was so specific. Ok I will be more verbose.
>
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > patternProperties:
> > "^cpu@[0-9]$":
> > type: object
> > @@ -64,6 +73,20 @@ properties:
> > required:
> > - mips-hpt-frequency
> >
> > +if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - brcm,bcm6358
> > + - brcm,bcm6368
> > +
> > +then:
> > + properties:
> > + cpus:
> > + required:
> > + - brcm,bmips-cbr-reg
> > +
> > additionalProperties: true
> >
> > examples:
> > --
> > 2.43.0
> >
--
Ansuel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property
2024-05-08 17:17 ` Christian Marangi
@ 2024-05-09 16:01 ` Florian Fainelli
0 siblings, 0 replies; 8+ messages in thread
From: Florian Fainelli @ 2024-05-09 16:01 UTC (permalink / raw
To: Christian Marangi, Conor Dooley
Cc: Hauke Mehrtens, Rafał Miłecki, Thomas Bogendoerfer,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Broadcom internal kernel review list, linux-mips, devicetree,
linux-kernel
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On 5/8/24 10:17, Christian Marangi wrote:
> On Wed, May 08, 2024 at 06:14:34PM +0100, Conor Dooley wrote:
>> On Wed, May 08, 2024 at 07:07:18PM +0200, Christian Marangi wrote:
>>> Document brcm,bmips-cbr-reg property.
>>>
>>> Some SoC suffer from a BUG where read_c0_brcm_cbr() might return 0
>>> if called from TP1. The CBR address is always the same on the SoC
>>> hence it can be provided in DT to handle broken case where bootloader
>>> doesn't init it or SMP where read_c0_brcm_cbr() returns 0 from TP1.
>>>
>>> Usage of this property is to give an address also in these broken
>>> configuration/bootloader.
>>>
>>> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
>>> ---
>>> .../devicetree/bindings/mips/brcm/soc.yaml | 23 +++++++++++++++++++
>>> 1 file changed, 23 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
>>> index 975945ca2888..77f73ab48c11 100644
>>> --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml
>>> +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
>>> @@ -55,6 +55,15 @@ properties:
>>> under the "cpus" node.
>>> $ref: /schemas/types.yaml#/definitions/uint32
>>>
>>> + brcm,bmips-cbr-reg:
>>> + description: Reference address of the CBR.
>>
>> Pretty sure that Rob commented last time that there's no definition
>> anywhere here of CBR, but I don't see either a response to him or an
>> explanation in v3 as to what CBR means.
>>
>
> Sorry I missed it.
FWIW, CBR mean Core Base Register. It is accessed via co-processor 0,
register 22, selector 6 using the MIPS processor's way of adding custom
co-processor registers.
--
Florian
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-05-09 16:02 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-05-08 17:07 [PATCH v3 0/4] mips: bmips: improve handling of RAC and CBR addr Christian Marangi
2024-05-08 17:07 ` [PATCH v3 1/4] mips: bmips: rework and cache CBR addr handling Christian Marangi
2024-05-08 17:07 ` [PATCH v3 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property Christian Marangi
2024-05-08 17:14 ` Conor Dooley
2024-05-08 17:17 ` Christian Marangi
2024-05-09 16:01 ` Florian Fainelli
2024-05-08 17:07 ` [PATCH v3 3/4] mips: bmips: setup: make CBR address configurable Christian Marangi
2024-05-08 17:07 ` [PATCH v3 4/4] mips: bmips: enable RAC on BMIPS4350 Christian Marangi
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