* [PATCH v6 0/9] Enable CPR for IPQ9574
@ 2024-07-10 6:10 Varadarajan Narayanan
2024-07-10 6:10 ` [PATCH v6 1/9] soc: qcom: cpr3: Fix 'acc_desc' usage Varadarajan Narayanan
` (8 more replies)
0 siblings, 9 replies; 21+ messages in thread
From: Varadarajan Narayanan @ 2024-07-10 6:10 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, andersson, konrad.dybcio, mturquette,
sboyd, ilia.lin, rafael, viresh.kumar, ulf.hansson, quic_sibis,
quic_rjendra, danila, quic_varada, neil.armstrong, otto.pflueger,
abel.vesa, luca, geert+renesas, stephan.gerhold, linux-arm-msm,
devicetree, linux-kernel, linux-pm, linux-clk
This series tries to enable CPR on IPQ9574 based on the drivers
posted in [1] - Add support for Core Power Reduction v3, v4 and Hardened.
dt_binding_check and dtbs_check passed.
Depends:
[1] https://lore.kernel.org/lkml/20240708-topic-cpr3h-v15-0-5bc8b8936489@linaro.org/T/
[2] https://lore.kernel.org/linux-arm-msm/20240703091651.2820236-10-quic_varada@quicinc.com/
v6: Update depends to Konrad's V15
Rebase on top of V15
Change 'acc_desc' check to accomodate v15 changes
v5:
This series tries to enable CPR on IPQ9574, that implements
CPRv4. Since [1] is older, faced few minor issues. Those are
addressed in [2].
Depends:
[1] https://lore.kernel.org/lkml/20230217-topic-cpr3h-v14-0-9fd23241493d@linaro.org/T/
[2] https://github.com/quic-varada/cpr/tree/4de50be55a89eb29ab0d40d3fcfe9aa7a9ccf910
[3] https://lore.kernel.org/linux-arm-msm/20240703091651.2820236-10-quic_varada@quicinc.com/
Drop 'dt-bindings: opp: v2-qcom-level: Update minItems for oloop-vadj & cloop-vadj',
the [3] dependency listed above. It should be squashed into [1]
Add acc_desc is not NULL check in one more place in cpr_probe
Update one commit message and add acked-by, reviewd-by
v4: s/cprh/cpr4/
Create new match data for ipq9574 that includes genpd_names
Update cloop-vadj & oloop-vadj with minItems
v3: Fix patch authorship for 2 patches
Include CPR3 file changes done to Konrad's patches in https://github.com/quic-varada/cpr/commits/konrad/
Change url for [2] to skip the cpr3 file changes
v2: Fix Signed-off-by order in 2 patches
Update constraints in qcom,cpr3.yaml
Add rbcpr_clk_src registration
Add Reviewed-by to one of the patches
Not adding Acked-by as the file has changed
Praveenkumar I (2):
pmdomain: qcom: rpmpd: Add IPQ9574 power domains
soc: qcom: cpr3: Add IPQ9574 definitions
Varadarajan Narayanan (7):
soc: qcom: cpr3: Fix 'acc_desc' usage
cpufreq: qcom-nvmem: Add support for IPQ9574
dt-bindings: power: rpmpd: Add IPQ9574 power domains
dt-bindings: soc: qcom: cpr3: Add bindings for IPQ9574
dt-bindings: clock: Add CPR clock defines for IPQ9574
clk: qcom: gcc-ipq9574: Add CPR clock definition
arm64: dts: qcom: ipq9574: Enable CPR
.../devicetree/bindings/power/qcom,rpmpd.yaml | 1 +
.../bindings/soc/qcom/qcom,cpr3.yaml | 35 +++
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 269 ++++++++++++++++--
drivers/clk/qcom/gcc-ipq9574.c | 39 +++
drivers/cpufreq/qcom-cpufreq-nvmem.c | 7 +-
drivers/pmdomain/qcom/cpr3.c | 149 +++++++++-
drivers/pmdomain/qcom/rpmpd.c | 19 ++
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 +
include/dt-bindings/power/qcom-rpmpd.h | 3 +
9 files changed, 502 insertions(+), 22 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v6 1/9] soc: qcom: cpr3: Fix 'acc_desc' usage
2024-07-10 6:10 [PATCH v6 0/9] Enable CPR for IPQ9574 Varadarajan Narayanan
@ 2024-07-10 6:10 ` Varadarajan Narayanan
2024-07-10 11:05 ` Konrad Dybcio
2024-07-10 6:10 ` [PATCH v6 2/9] cpufreq: qcom-nvmem: Add support for IPQ9574 Varadarajan Narayanan
` (7 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Varadarajan Narayanan @ 2024-07-10 6:10 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, andersson, konrad.dybcio, mturquette,
sboyd, ilia.lin, rafael, viresh.kumar, ulf.hansson, quic_sibis,
quic_rjendra, danila, quic_varada, neil.armstrong, otto.pflueger,
abel.vesa, luca, geert+renesas, stephan.gerhold, linux-arm-msm,
devicetree, linux-kernel, linux-pm, linux-clk
cpr3 code assumes that 'acc_desc' is available for SoCs
implementing CPR version 4 or less. However, IPQ9574 SoC
implements CPRv4 without ACC. This causes NULL pointer accesses
resulting in crashes. Hence, check if 'acc_desc' is populated
before using it.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v6: Changes done in the previous version of this patch got squashed
into Konrad's V15
- https://lore.kernel.org/lkml/20240708-topic-cpr3h-v15-9-5bc8b8936489@linaro.org/
In v14, cpr_set_acc() was invoked from cpr_pre_voltage() or
cpr_post_voltage(). Both of those functions invoked cpr_set_acc()
only if drv->tcsr was not NULL (and that implied acc_desc != NULL).
In v15, cpr_pre_voltage() & cpr_post_voltage() have been
removed and cpr_set_acc() is called even though acc_desc
is NULL resulting in NULL pointer access.
Hence allow cpr_set_acc() to proceed only if acc_desc is set.
v5: Add acc_desc check in a different way without breaking other SoC
v4: Undo the acc_desc validation in probe function as that could
affect other SoC.
---
drivers/pmdomain/qcom/cpr3.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/pmdomain/qcom/cpr3.c b/drivers/pmdomain/qcom/cpr3.c
index de24973978b7..d594bc79be1c 100644
--- a/drivers/pmdomain/qcom/cpr3.c
+++ b/drivers/pmdomain/qcom/cpr3.c
@@ -536,12 +536,15 @@ static void cpr_corner_restore(struct cpr_thread *thread,
static void cpr_set_acc(struct cpr_drv *drv, int f)
{
const struct acc_desc *desc = drv->acc_desc;
- struct reg_sequence *s = desc->settings;
- int n = desc->num_regs_per_fuse;
+ struct reg_sequence *s;
+ int n;
- if (!drv->tcsr)
+ if (!desc || !drv->tcsr)
return;
+ s = desc->settings;
+ n = desc->num_regs_per_fuse;
+
if (!s || f == drv->fuse_level_set)
return;
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v6 2/9] cpufreq: qcom-nvmem: Add support for IPQ9574
2024-07-10 6:10 [PATCH v6 0/9] Enable CPR for IPQ9574 Varadarajan Narayanan
2024-07-10 6:10 ` [PATCH v6 1/9] soc: qcom: cpr3: Fix 'acc_desc' usage Varadarajan Narayanan
@ 2024-07-10 6:10 ` Varadarajan Narayanan
2024-07-10 11:05 ` Konrad Dybcio
2024-07-10 6:10 ` [PATCH v6 3/9] dt-bindings: power: rpmpd: Add IPQ9574 power domains Varadarajan Narayanan
` (6 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Varadarajan Narayanan @ 2024-07-10 6:10 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, andersson, konrad.dybcio, mturquette,
sboyd, ilia.lin, rafael, viresh.kumar, ulf.hansson, quic_sibis,
quic_rjendra, danila, quic_varada, neil.armstrong, otto.pflueger,
abel.vesa, luca, geert+renesas, stephan.gerhold, linux-arm-msm,
devicetree, linux-kernel, linux-pm, linux-clk
Cc: Dmitry Baryshkov
IPQ9574 uses CPR4 power domain to manage core supplies. Use
device-specific match data for this platform that includes
genpd_names configuration.
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v5: Change commit message and add Acked-by
v4: Update commit log to include stack trace
Introduce qcom_cpufreq_match_data for IPQ9574
---
drivers/cpufreq/qcom-cpufreq-nvmem.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 939702dfa73f..95558586c2e6 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -428,6 +428,11 @@ static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
.get_version = qcom_cpufreq_ipq8074_name_version,
};
+static const struct qcom_cpufreq_match_data match_data_ipq9574 = {
+ .get_version = qcom_cpufreq_kryo_name_version,
+ .genpd_names = generic_genpd_names,
+};
+
static void qcom_cpufreq_suspend_virt_devs(struct qcom_cpufreq_drv *drv, unsigned int cpu)
{
const char * const *name = drv->data->genpd_names;
@@ -621,7 +626,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
{ .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 },
{ .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
{ .compatible = "qcom,apq8064", .data = &match_data_krait },
- { .compatible = "qcom,ipq9574", .data = &match_data_kryo },
+ { .compatible = "qcom,ipq9574", .data = &match_data_ipq9574 },
{ .compatible = "qcom,msm8974", .data = &match_data_krait },
{ .compatible = "qcom,msm8960", .data = &match_data_krait },
{},
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v6 3/9] dt-bindings: power: rpmpd: Add IPQ9574 power domains
2024-07-10 6:10 [PATCH v6 0/9] Enable CPR for IPQ9574 Varadarajan Narayanan
2024-07-10 6:10 ` [PATCH v6 1/9] soc: qcom: cpr3: Fix 'acc_desc' usage Varadarajan Narayanan
2024-07-10 6:10 ` [PATCH v6 2/9] cpufreq: qcom-nvmem: Add support for IPQ9574 Varadarajan Narayanan
@ 2024-07-10 6:10 ` Varadarajan Narayanan
2024-07-10 6:10 ` [PATCH v6 4/9] dt-bindings: soc: qcom: cpr3: Add bindings for IPQ9574 Varadarajan Narayanan
` (5 subsequent siblings)
8 siblings, 0 replies; 21+ messages in thread
From: Varadarajan Narayanan @ 2024-07-10 6:10 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, andersson, konrad.dybcio, mturquette,
sboyd, ilia.lin, rafael, viresh.kumar, ulf.hansson, quic_sibis,
quic_rjendra, danila, quic_varada, neil.armstrong, otto.pflueger,
abel.vesa, luca, geert+renesas, stephan.gerhold, linux-arm-msm,
devicetree, linux-kernel, linux-pm, linux-clk
Cc: Krzysztof Kozlowski
Add the compatibles and indexes for the rpmpd in IPQ9574.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v3 & v4: no changes
v2: Add Reviewed-by
---
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 +
include/dt-bindings/power/qcom-rpmpd.h | 3 +++
2 files changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
index 929b7ef9c1bc..e20ba25fa094 100644
--- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
+++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
@@ -17,6 +17,7 @@ properties:
compatible:
oneOf:
- enum:
+ - qcom,ipq9574-rpmpd
- qcom,mdm9607-rpmpd
- qcom,msm8226-rpmpd
- qcom,msm8909-rpmpd
diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
index 608087fb9a3d..0538370bfbb4 100644
--- a/include/dt-bindings/power/qcom-rpmpd.h
+++ b/include/dt-bindings/power/qcom-rpmpd.h
@@ -402,6 +402,9 @@
#define QCM2290_VDD_LPI_CX 6
#define QCM2290_VDD_LPI_MX 7
+/* IPQ9574 Power Domains */
+#define IPQ9574_VDDAPC 0
+
/* RPM SMD Power Domain performance levels */
#define RPM_SMD_LEVEL_RETENTION 16
#define RPM_SMD_LEVEL_RETENTION_PLUS 32
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v6 4/9] dt-bindings: soc: qcom: cpr3: Add bindings for IPQ9574
2024-07-10 6:10 [PATCH v6 0/9] Enable CPR for IPQ9574 Varadarajan Narayanan
` (2 preceding siblings ...)
2024-07-10 6:10 ` [PATCH v6 3/9] dt-bindings: power: rpmpd: Add IPQ9574 power domains Varadarajan Narayanan
@ 2024-07-10 6:10 ` Varadarajan Narayanan
2024-07-10 6:10 ` [PATCH v6 5/9] pmdomain: qcom: rpmpd: Add IPQ9574 power domains Varadarajan Narayanan
` (4 subsequent siblings)
8 siblings, 0 replies; 21+ messages in thread
From: Varadarajan Narayanan @ 2024-07-10 6:10 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, andersson, konrad.dybcio, mturquette,
sboyd, ilia.lin, rafael, viresh.kumar, ulf.hansson, quic_sibis,
quic_rjendra, danila, quic_varada, neil.armstrong, otto.pflueger,
abel.vesa, luca, geert+renesas, stephan.gerhold, linux-arm-msm,
devicetree, linux-kernel, linux-pm, linux-clk
Cc: Krzysztof Kozlowski
Add the bindings for the IPQ9574 CPR3 driver to the documentation.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v5: Add Reviewed-by
v4: Change compatible string to cpr4 instead of cprh
Not adding Reviewed-By as compatible string changed
v2: Constrained nvmem-cells and the other variant.
Removed unnecessary blank line.
---
.../bindings/soc/qcom/qcom,cpr3.yaml | 35 +++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
index 2e6712aa1c58..c00373948901 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
@@ -24,6 +24,7 @@ properties:
- const: qcom,cpr4
- items:
- enum:
+ - qcom,ipq9574-cpr4
- qcom,msm8998-cprh
- qcom,sdm630-cprh
- const: qcom,cprh
@@ -52,9 +53,11 @@ properties:
nvmem-cells:
description: Cells containing the fuse corners and revision data
+ minItems: 17
maxItems: 32
nvmem-cell-names:
+ minItems: 17
maxItems: 32
operating-points-v2: true
@@ -74,6 +77,36 @@ required:
additionalProperties: false
allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq9574-cpr4
+ then:
+ properties:
+ nvmem-cells:
+ maxItems: 17
+ nvmem-cell-names:
+ items:
+ - const: cpr_speed_bin
+ - const: cpr_fuse_revision
+ - const: cpr0_quotient1
+ - const: cpr0_quotient2
+ - const: cpr0_quotient3
+ - const: cpr0_quotient4
+ - const: cpr0_quotient_offset2
+ - const: cpr0_quotient_offset3
+ - const: cpr0_quotient_offset4
+ - const: cpr0_init_voltage1
+ - const: cpr0_init_voltage2
+ - const: cpr0_init_voltage3
+ - const: cpr0_init_voltage4
+ - const: cpr0_ring_osc1
+ - const: cpr0_ring_osc2
+ - const: cpr0_ring_osc3
+ - const: cpr0_ring_osc4
+
- if:
properties:
compatible:
@@ -82,6 +115,8 @@ allOf:
- qcom,msm8998-cprh
then:
properties:
+ nvmem-cells:
+ minItems: 32
nvmem-cell-names:
items:
- const: cpr_speed_bin
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v6 5/9] pmdomain: qcom: rpmpd: Add IPQ9574 power domains
2024-07-10 6:10 [PATCH v6 0/9] Enable CPR for IPQ9574 Varadarajan Narayanan
` (3 preceding siblings ...)
2024-07-10 6:10 ` [PATCH v6 4/9] dt-bindings: soc: qcom: cpr3: Add bindings for IPQ9574 Varadarajan Narayanan
@ 2024-07-10 6:10 ` Varadarajan Narayanan
2024-07-16 12:15 ` Konrad Dybcio
2024-07-10 6:10 ` [PATCH v6 6/9] dt-bindings: clock: Add CPR clock defines for IPQ9574 Varadarajan Narayanan
` (3 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Varadarajan Narayanan @ 2024-07-10 6:10 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, andersson, konrad.dybcio, mturquette,
sboyd, ilia.lin, rafael, viresh.kumar, ulf.hansson, quic_sibis,
quic_rjendra, danila, quic_varada, neil.armstrong, otto.pflueger,
abel.vesa, luca, geert+renesas, stephan.gerhold, linux-arm-msm,
devicetree, linux-kernel, linux-pm, linux-clk
Cc: Praveenkumar I, Dmitry Baryshkov
From: Praveenkumar I <quic_ipkumar@quicinc.com>
Add the APC power domain definitions used in IPQ9574.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v4: Add Reviewed-by: Dmitry Baryshkov
v3: Fix patch author
v2: Fix Signed-off-by order
---
drivers/pmdomain/qcom/rpmpd.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/pmdomain/qcom/rpmpd.c b/drivers/pmdomain/qcom/rpmpd.c
index 5e6280b4cf70..947d6a9c3897 100644
--- a/drivers/pmdomain/qcom/rpmpd.c
+++ b/drivers/pmdomain/qcom/rpmpd.c
@@ -38,6 +38,7 @@ static struct qcom_smd_rpm *rpmpd_smd_rpm;
#define KEY_FLOOR_CORNER 0x636676 /* vfc */
#define KEY_FLOOR_LEVEL 0x6c6676 /* vfl */
#define KEY_LEVEL 0x6c766c76 /* vlvl */
+#define RPM_KEY_UV 0x00007675 /* "uv" */
#define MAX_CORNER_RPMPD_STATE 6
@@ -644,6 +645,23 @@ static const struct rpmpd_desc mdm9607_desc = {
.max_state = RPM_SMD_LEVEL_TURBO,
};
+static struct rpmpd apc_s1_lvl = {
+ .pd = { .name = "apc", },
+ .res_type = RPMPD_SMPA,
+ .res_id = 1,
+ .key = RPM_KEY_UV,
+};
+
+static struct rpmpd *ipq9574_rpmpds[] = {
+ [IPQ9574_VDDAPC] = &apc_s1_lvl,
+};
+
+static const struct rpmpd_desc ipq9574_desc = {
+ .rpmpds = ipq9574_rpmpds,
+ .num_pds = ARRAY_SIZE(ipq9574_rpmpds),
+ .max_state = RPM_SMD_LEVEL_TURBO_HIGH,
+};
+
static struct rpmpd *msm8226_rpmpds[] = {
[MSM8226_VDDCX] = &cx_s1a_corner,
[MSM8226_VDDCX_AO] = &cx_s1a_corner_ao,
@@ -931,6 +949,7 @@ static const struct rpmpd_desc qcm2290_desc = {
};
static const struct of_device_id rpmpd_match_table[] = {
+ { .compatible = "qcom,ipq9574-rpmpd", .data = &ipq9574_desc },
{ .compatible = "qcom,mdm9607-rpmpd", .data = &mdm9607_desc },
{ .compatible = "qcom,msm8226-rpmpd", .data = &msm8226_desc },
{ .compatible = "qcom,msm8909-rpmpd", .data = &msm8916_desc },
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v6 6/9] dt-bindings: clock: Add CPR clock defines for IPQ9574
2024-07-10 6:10 [PATCH v6 0/9] Enable CPR for IPQ9574 Varadarajan Narayanan
` (4 preceding siblings ...)
2024-07-10 6:10 ` [PATCH v6 5/9] pmdomain: qcom: rpmpd: Add IPQ9574 power domains Varadarajan Narayanan
@ 2024-07-10 6:10 ` Varadarajan Narayanan
2024-07-10 6:11 ` [PATCH v6 7/9] clk: qcom: gcc-ipq9574: Add CPR clock definition Varadarajan Narayanan
` (2 subsequent siblings)
8 siblings, 0 replies; 21+ messages in thread
From: Varadarajan Narayanan @ 2024-07-10 6:10 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, andersson, konrad.dybcio, mturquette,
sboyd, ilia.lin, rafael, viresh.kumar, ulf.hansson, quic_sibis,
quic_rjendra, danila, quic_varada, neil.armstrong, otto.pflueger,
abel.vesa, luca, geert+renesas, stephan.gerhold, linux-arm-msm,
devicetree, linux-kernel, linux-pm, linux-clk
Cc: Krzysztof Kozlowski
Add defines for the CPR block present in IPQ9574.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v4: No change
v3: Add Acked-By
v2: Add GCC_RBCPR_CLK_SRC define.
Not adding 'Acked-by: Krzysztof Kozlowski' as the file changed.
---
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
index 52123c5a09fa..4c65de04cb7b 100644
--- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
@@ -220,4 +220,6 @@
#define GCC_PCIE1_PIPE_CLK 211
#define GCC_PCIE2_PIPE_CLK 212
#define GCC_PCIE3_PIPE_CLK 213
+#define GCC_RBCPR_CLK_SRC 214
+#define GCC_RBCPR_CLK 215
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v6 7/9] clk: qcom: gcc-ipq9574: Add CPR clock definition
2024-07-10 6:10 [PATCH v6 0/9] Enable CPR for IPQ9574 Varadarajan Narayanan
` (5 preceding siblings ...)
2024-07-10 6:10 ` [PATCH v6 6/9] dt-bindings: clock: Add CPR clock defines for IPQ9574 Varadarajan Narayanan
@ 2024-07-10 6:11 ` Varadarajan Narayanan
2024-07-10 6:11 ` [PATCH v6 8/9] soc: qcom: cpr3: Add IPQ9574 definitions Varadarajan Narayanan
2024-07-10 6:11 ` [PATCH v6 9/9] arm64: dts: qcom: ipq9574: Enable CPR Varadarajan Narayanan
8 siblings, 0 replies; 21+ messages in thread
From: Varadarajan Narayanan @ 2024-07-10 6:11 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, andersson, konrad.dybcio, mturquette,
sboyd, ilia.lin, rafael, viresh.kumar, ulf.hansson, quic_sibis,
quic_rjendra, danila, quic_varada, neil.armstrong, otto.pflueger,
abel.vesa, luca, geert+renesas, stephan.gerhold, linux-arm-msm,
devicetree, linux-kernel, linux-pm, linux-clk
Cc: Dmitry Baryshkov
Add the CPR clock definition needed for enabling access to
CPR register space.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
drivers/clk/qcom/gcc-ipq9574.c | 39 ++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index e1dc74d04ed1..eac557937fd3 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -3994,6 +3994,43 @@ static struct clk_branch gcc_xo_div4_clk = {
},
};
+static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 rbcpr_clk_src = {
+ .cmd_rcgr = 0x48044,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_xo_map,
+ .freq_tbl = ftbl_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "rbcpr_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll4,
+ .num_parents = ARRAY_SIZE(gcc_xo_map),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_rbcpr_clk = {
+ .halt_reg = 0x48008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x48008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_rbcpr_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &rbcpr_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_hw *gcc_ipq9574_hws[] = {
&gpll0_out_main_div2.hw,
&gcc_xo_div4_clk_src.hw,
@@ -4219,6 +4256,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
[GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
[GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
[GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
+ [GCC_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
+ [GCC_RBCPR_CLK] = &gcc_rbcpr_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq9574_resets[] = {
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v6 8/9] soc: qcom: cpr3: Add IPQ9574 definitions
2024-07-10 6:10 [PATCH v6 0/9] Enable CPR for IPQ9574 Varadarajan Narayanan
` (6 preceding siblings ...)
2024-07-10 6:11 ` [PATCH v6 7/9] clk: qcom: gcc-ipq9574: Add CPR clock definition Varadarajan Narayanan
@ 2024-07-10 6:11 ` Varadarajan Narayanan
2024-07-10 11:12 ` Konrad Dybcio
2024-07-10 6:11 ` [PATCH v6 9/9] arm64: dts: qcom: ipq9574: Enable CPR Varadarajan Narayanan
8 siblings, 1 reply; 21+ messages in thread
From: Varadarajan Narayanan @ 2024-07-10 6:11 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, andersson, konrad.dybcio, mturquette,
sboyd, ilia.lin, rafael, viresh.kumar, ulf.hansson, quic_sibis,
quic_rjendra, danila, quic_varada, neil.armstrong, otto.pflueger,
abel.vesa, luca, geert+renesas, stephan.gerhold, linux-arm-msm,
devicetree, linux-kernel, linux-pm, linux-clk
Cc: Praveenkumar I
From: Praveenkumar I <quic_ipkumar@quicinc.com>
* Add thread, scaling factor, CPR descriptor defines to enable
CPR on IPQ9574.
* Skip 'acc' usage since IPQ9574 does not have acc
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v6: Rebase on top of Konrad's v15
- https://lore.kernel.org/lkml/20240708-topic-cpr3h-v15-0-5bc8b8936489@linaro.org/T/
v5: Move the 'acc_desc' usage check to first patch
v4: s/silver//, s/cprh/cpr4/
Skip 'acc' related code as IPQ9574 does not have acc
v3: Fix patch author
Included below information in cover letter
v2: Fix Signed-off-by order
Depends:
[1] https://lore.kernel.org/lkml/20230217-topic-cpr3h-v14-0-9fd23241493d@linaro.org/T/
[2] https://github.com/quic-varada/cpr/commits/konrad/
---
drivers/pmdomain/qcom/cpr3.c | 140 ++++++++++++++++++++++++++++++++++-
1 file changed, 139 insertions(+), 1 deletion(-)
diff --git a/drivers/pmdomain/qcom/cpr3.c b/drivers/pmdomain/qcom/cpr3.c
index d594bc79be1c..0e24ee1556df 100644
--- a/drivers/pmdomain/qcom/cpr3.c
+++ b/drivers/pmdomain/qcom/cpr3.c
@@ -1942,6 +1942,142 @@ static const struct cpr_acc_desc msm8998_cpr_acc_desc = {
.cpr_desc = &msm8998_cpr_desc,
};
+static const int ipq9574_scaling_factor[][CPR3_RO_COUNT] = {
+ /* Fuse Corner 0 */
+ {
+ 2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949,
+ 2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332
+ },
+ /* Fuse Corner 1 */
+ {
+ 2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949,
+ 2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332
+ },
+ /* Fuse Corner 2 */
+ {
+ 2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949,
+ 2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332
+ },
+ /* Fuse Corner 3 */
+ {
+ 2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949,
+ 2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332
+ },
+};
+
+static const struct cpr_thread_desc ipq9574_thread = {
+ .controller_id = 0,
+ .hw_tid = 0,
+ .ro_scaling_factor = ipq9574_scaling_factor,
+ .sensor_range_start = 0,
+ .sensor_range_end = 6,
+ .init_voltage_step = 10000,
+ .init_voltage_width = 6,
+ .step_quot_init_min = 0,
+ .step_quot_init_max = 15,
+ .num_fuse_corners = 4,
+ .fuse_corner_data = (struct fuse_corner_data[]){
+ /* fuse corner 0 */
+ {
+ .ref_uV = 725000,
+ .max_uV = 725000,
+ .min_uV = 725000,
+ .range_uV = 0,
+ .volt_cloop_adjust = 0,
+ .volt_oloop_adjust = 0,
+ .max_volt_scale = 4,
+ .max_quot_scale = 10,
+ .quot_offset = 0,
+ .quot_scale = 1,
+ .quot_adjust = 0,
+ .quot_offset_scale = 5,
+ .quot_offset_adjust = 0,
+ },
+ /* fuse corner 1 */
+ {
+ .ref_uV = 862500,
+ .max_uV = 862500,
+ .min_uV = 725000,
+ .range_uV = 0,
+ .volt_cloop_adjust = 0,
+ .volt_oloop_adjust = 0,
+ .max_volt_scale = 500,
+ .max_quot_scale = 800,
+ .quot_offset = 0,
+ .quot_scale = 1,
+ .quot_adjust = 0,
+ .quot_offset_scale = 5,
+ .quot_offset_adjust = 0,
+ },
+ /* fuse corner 2 */
+ {
+ .ref_uV = 987500,
+ .max_uV = 987500,
+ .min_uV = 787500,
+ .range_uV = 0,
+ .volt_cloop_adjust = 0,
+ .volt_oloop_adjust = 0,
+ .max_volt_scale = 280,
+ .max_quot_scale = 650,
+ .quot_offset = 0,
+ .quot_scale = 1,
+ .quot_adjust = 0,
+ .quot_offset_scale = 5,
+ .quot_offset_adjust = 0,
+
+ },
+ /* fuse corner 3 */
+ {
+ .ref_uV = 1062500,
+ .max_uV = 1062500,
+ .min_uV = 850000,
+ .range_uV = 0,
+ .volt_cloop_adjust = 0,
+ .volt_oloop_adjust = 0,
+ .max_volt_scale = 430,
+ .max_quot_scale = 800,
+ .quot_offset = 0,
+ .quot_scale = 1,
+ .quot_adjust = 0,
+ .quot_offset_scale = 5,
+ .quot_offset_adjust = 0,
+ },
+ },
+};
+
+static const struct cpr_desc ipq9574_cpr_desc = {
+ .cpr_type = CTRL_TYPE_CPR4,
+ .num_threads = 1,
+ .apm_threshold = 850000,
+ .apm_crossover = 880000,
+ .apm_hysteresis = 0,
+ .cpr_base_voltage = 700000,
+ .cpr_max_voltage = 1100000,
+ .timer_delay_us = 5000,
+ .timer_cons_up = 0,
+ .timer_cons_down = 0,
+ .up_threshold = 2,
+ .down_threshold = 2,
+ .idle_clocks = 15,
+ .count_mode = CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN,
+ .count_repeat = 1,
+ .gcnt_us = 1,
+ .vreg_step_fixed = 12500,
+ .vreg_step_up_limit = 1,
+ .vreg_step_down_limit = 1,
+ .vdd_settle_time_us = 34,
+ .corner_settle_time_us = 6,
+ .reduce_to_corner_uV = true,
+ .hw_closed_loop_en = false,
+ .threads = (const struct cpr_thread_desc *[]) {
+ &ipq9574_thread,
+ },
+};
+
+static const struct cpr_acc_desc ipq9574_cpr_acc_desc = {
+ .cpr_desc = &ipq9574_cpr_desc,
+};
+
static const int sdm630_gold_scaling_factor[][CPR3_RO_COUNT] = {
/* Same RO factors for all fuse corners */
{
@@ -2544,7 +2680,8 @@ static int cpr_probe(struct platform_device *pdev)
desc = data->cpr_desc;
/* CPRh disallows MEM-ACC access from the HLOS */
- if (!(data->acc_desc || desc->cpr_type == CTRL_TYPE_CPRH))
+ if (!(data->acc_desc || desc->cpr_type == CTRL_TYPE_CPRH ||
+ of_device_is_compatible(dev->of_node, "qcom,ipq9574-cpr4")))
return dev_err_probe(dev, -EINVAL, "Invalid ACC data\n");
drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
@@ -2694,6 +2831,7 @@ static void cpr_remove(struct platform_device *pdev)
}
static const struct of_device_id cpr3_match_table[] = {
+ { .compatible = "qcom,ipq9574-cpr4", .data = &ipq9574_cpr_acc_desc },
{ .compatible = "qcom,msm8998-cprh", .data = &msm8998_cpr_acc_desc },
{ .compatible = "qcom,sdm630-cprh", .data = &sdm630_cpr_acc_desc },
{ }
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v6 9/9] arm64: dts: qcom: ipq9574: Enable CPR
2024-07-10 6:10 [PATCH v6 0/9] Enable CPR for IPQ9574 Varadarajan Narayanan
` (7 preceding siblings ...)
2024-07-10 6:11 ` [PATCH v6 8/9] soc: qcom: cpr3: Add IPQ9574 definitions Varadarajan Narayanan
@ 2024-07-10 6:11 ` Varadarajan Narayanan
8 siblings, 0 replies; 21+ messages in thread
From: Varadarajan Narayanan @ 2024-07-10 6:11 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, andersson, konrad.dybcio, mturquette,
sboyd, ilia.lin, rafael, viresh.kumar, ulf.hansson, quic_sibis,
quic_rjendra, danila, quic_varada, neil.armstrong, otto.pflueger,
abel.vesa, luca, geert+renesas, stephan.gerhold, linux-arm-msm,
devicetree, linux-kernel, linux-pm, linux-clk
* Add CPR, RPMPD, OPP table nodes as applicable to IPQ9574 to
enable CPR functionality on IPQ9574.
* Bootloader set frequency 792MHz is added to the OPP table to
the avoid 'need at least 2 OPPs to use CPR' error
* Remove 1.2GHz as it is not supported in any of the IPQ9574 SKUs.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v6: Fix subject prefix
v4: s/cprh/cpr4/
v2: Update commit log. No code change.
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 269 ++++++++++++++++++++++++--
1 file changed, 252 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 04ba09a9156c..cda30a877877 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
/ {
interrupt-parent = <&intc>;
@@ -42,8 +43,9 @@ CPU0: cpu@0 {
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
- cpu-supply = <&ipq9574_s1>;
#cooling-cells = <2>;
+ power-domains = <&apc_cpr4 0>;
+ power-domain-names = "perf";
};
CPU1: cpu@1 {
@@ -55,8 +57,9 @@ CPU1: cpu@1 {
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
- cpu-supply = <&ipq9574_s1>;
#cooling-cells = <2>;
+ power-domains = <&apc_cpr4 0>;
+ power-domain-names = "perf";
};
CPU2: cpu@2 {
@@ -68,8 +71,9 @@ CPU2: cpu@2 {
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
- cpu-supply = <&ipq9574_s1>;
#cooling-cells = <2>;
+ power-domains = <&apc_cpr4 0>;
+ power-domain-names = "perf";
};
CPU3: cpu@3 {
@@ -81,8 +85,9 @@ CPU3: cpu@3 {
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
- cpu-supply = <&ipq9574_s1>;
#cooling-cells = <2>;
+ power-domains = <&apc_cpr4 0>;
+ power-domain-names = "perf";
};
L2_0: l2-cache {
@@ -105,58 +110,111 @@ memory@40000000 {
reg = <0x0 0x40000000 0x0 0x0>;
};
+ cpr4_opp_table: opp-table-cpr4 {
+ compatible = "operating-points-v2-qcom-level";
+
+ cpr4_opp0: opp-0 {
+ opp-level = <1>;
+ qcom,opp-fuse-level = <1>;
+ qcom,opp-cloop-vadj = <0>;
+ qcom,opp-oloop-vadj = <0>;
+ };
+
+ cpr4_opp1: opp-1 {
+ opp-level = <2>;
+ qcom,opp-fuse-level = <1>;
+ qcom,opp-cloop-vadj = <0>;
+ qcom,opp-oloop-vadj = <0>;
+ };
+
+ cpr4_opp2: opp-2 {
+ opp-level = <3>;
+ qcom,opp-fuse-level = <1>;
+ qcom,opp-cloop-vadj = <0>;
+ qcom,opp-oloop-vadj = <0>;
+ };
+
+ cpr4_opp3: opp-3 {
+ opp-level = <4>;
+ qcom,opp-fuse-level = <2>;
+ qcom,opp-cloop-vadj = <0>;
+ qcom,opp-oloop-vadj = <0>;
+ };
+
+ cpr4_opp4: opp-4 {
+ opp-level = <5>;
+ qcom,opp-fuse-level = <2>;
+ qcom,opp-cloop-vadj = <0>;
+ qcom,opp-oloop-vadj = <0>;
+ };
+
+ cpr4_opp5: opp-5 {
+ opp-level = <6>;
+ qcom,opp-fuse-level = <3>;
+ qcom,opp-cloop-vadj = <0>;
+ qcom,opp-oloop-vadj = <0>;
+ };
+
+ cpr4_opp6: opp-6 {
+ opp-level = <7>;
+ qcom,opp-fuse-level = <4>;
+ qcom,opp-cloop-vadj = <0>;
+ qcom,opp-oloop-vadj = <0>;
+ };
+ };
+
cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2-kryo-cpu";
opp-shared;
nvmem-cells = <&cpu_speed_bin>;
+ opp-792000000 {
+ opp-hz = /bits/ 64 <792000000>;
+ opp-supported-hw = <0x0>;
+ clock-latency-ns = <200000>;
+ required-opps = <&cpr4_opp0>;
+ };
+
opp-936000000 {
opp-hz = /bits/ 64 <936000000>;
- opp-microvolt = <725000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ required-opps = <&cpr4_opp1>;
};
opp-1104000000 {
opp-hz = /bits/ 64 <1104000000>;
- opp-microvolt = <787500>;
- opp-supported-hw = <0xf>;
- clock-latency-ns = <200000>;
- };
-
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <862500>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ required-opps = <&cpr4_opp2>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
- opp-microvolt = <862500>;
opp-supported-hw = <0x7>;
clock-latency-ns = <200000>;
+ required-opps = <&cpr4_opp3>;
};
opp-1488000000 {
opp-hz = /bits/ 64 <1488000000>;
- opp-microvolt = <925000>;
opp-supported-hw = <0x7>;
clock-latency-ns = <200000>;
+ required-opps = <&cpr4_opp4>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <987500>;
opp-supported-hw = <0x5>;
clock-latency-ns = <200000>;
+ required-opps = <&cpr4_opp5>;
};
opp-2208000000 {
opp-hz = /bits/ 64 <2208000000>;
- opp-microvolt = <1062500>;
opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
+ required-opps = <&cpr4_opp6>;
};
};
@@ -182,6 +240,40 @@ glink-edge {
rpm_requests: rpm-requests {
compatible = "qcom,rpm-ipq9574";
qcom,glink-channels = "rpm_requests";
+
+ rpmpd: power-controller {
+ compatible = "qcom,ipq9574-rpmpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmpd_opp_table>;
+
+ rpmpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmpd_opp_svs: opp1 {
+ opp-level = <RPM_SMD_LEVEL_SVS>;
+ };
+
+ rpmpd_opp_svs_plus: opp2 {
+ opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
+ };
+
+ rpmpd_opp_nom: opp3 {
+ opp-level = <RPM_SMD_LEVEL_NOM>;
+ };
+
+ rpmpd_opp_nom_plus: opp4 {
+ opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+ };
+
+ rpmpd_opp_turbo: opp5 {
+ opp-level = <RPM_SMD_LEVEL_TURBO>;
+ };
+
+ rpmpd_opp_turbo_high: opp6 {
+ opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>;
+ };
+ };
+ };
};
};
};
@@ -252,6 +344,95 @@ cpu_speed_bin: cpu-speed-bin@15 {
reg = <0x15 0x2>;
bits = <7 2>;
};
+
+ cpr_efuse_speedbin: speedbin@5 {
+ reg = <0x5 0x8>;
+ bits = <0 3>;
+ };
+
+ cpr_fuse_revision: cpr-fusing-rev@7 {
+ reg = <0x7 0x8>;
+ bits = <1 5>;
+ };
+
+ /* CPR Ring Oscillator: Power Cluster */
+ cpr_ro_sel0_pwrcl: rosel0-pwrcl@358 { /* ROSEL_SVS */
+ reg = <0x358 0x1>;
+ bits = <4 4>;
+ };
+
+ cpr_ro_sel1_pwrcl: rosel1-pwrcl@358 { /* ROSEL_NOM */
+ reg = <0x358 0x1>;
+ bits = <0 4>;
+ };
+
+ cpr_ro_sel2_pwrcl: rosel2-pwrcl@350 { /* ROSEL_TUR */
+ reg = <0x350 0x1>;
+ bits = <4 4>;
+ };
+
+ cpr_ro_sel3_pwrcl: rosel3-pwrcl@350 { /* ROSEL_STUR */
+ reg = <0x350 0x1>;
+ bits = <0 4>;
+ };
+
+ /* CPR Init Voltage: Power Cluster */
+ cpr_init_voltage0_pwrcl: ivolt0-pwrcl@343 { /* VOLT_SVS */
+ reg = <0x343 0x1>;
+ bits = <0 6>;
+ };
+
+ cpr_init_voltage1_pwrcl: ivolt1-pwrcl@342 { /* VOLT_NOM */
+ reg = <0x342 0x1>;
+ bits = <2 6>;
+ };
+
+ cpr_init_voltage2_pwrcl: ivolt2-pwrcl@341 { /* VOLT_TUR */
+ reg = <0x341 0x2>;
+ bits = <4 6>;
+ };
+
+ cpr_init_voltage3_pwrcl: ivolt3-pwrcl@340 { /* VOLT_STUR */
+ reg = <0x340 0x2>;
+ bits = <6 6>;
+ };
+
+ /* CPR Target Quotients: Power Cluster */
+ cpr_quot0_pwrcl: quot0-pwrcl@354 { /* QUOT_VMIN_SVS */
+ reg = <0x354 0x2>;
+ bits = <0 12>;
+ };
+
+ cpr_quot1_pwrcl: quot1-pwrcl@352 { /* QUOT_VMIN_NOM */
+ reg = <0x352 0x2>;
+ bits = <4 12>;
+ };
+
+ cpr_quot2_pwrcl: quot2-pwrcl@351 { /* QUOT_VMIN_TUR */
+ reg = <0x351 0x2>;
+ bits = <0 12>;
+ };
+
+ cpr_quot3_pwrcl: quot3-pwrcl@355 { /* QUOT_VMIN_STUR */
+ reg = <0x355 0x2>;
+ bits = <4 12>;
+ };
+
+ /* CPR Quotient Offsets: Power Cluster */
+ cpr_quot_offset1_pwrcl: qoff1-pwrcl@34e { /* QUOT_OFFSET_NOM_SVS */
+ reg = <0x34e 0x1>;
+ bits = <0 8>;
+ };
+
+ cpr_quot_offset2_pwrcl: qoff2-pwrcl@34d { /* QUOT_OFFSET_TUR_NOM */
+ reg = <0x34d 0x1>;
+ bits = <0 8>;
+ };
+
+ cpr_quot_offset3_pwrcl: qoff0-pwrcl@34c { /* QUOT_OFFSET_STUR_TUR */
+ reg = <0x34c 0x1>;
+ bits = <0 8>;
+ };
};
cryptobam: dma-controller@704000 {
@@ -639,6 +820,60 @@ usb_0_dwc3: usb@8a00000 {
};
};
+ apc_cpr4: power-controller@b018000 {
+ compatible = "qcom,ipq9574-cpr4", "qcom,cprh";
+ reg = <0x0b018000 0x4000>,
+ <0x00048000 0x4000>;
+
+ clocks = <&gcc GCC_RBCPR_CLK>;
+
+ interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
+ vdd-supply = <&ipq9574_s1>;
+
+ /* Set the CPR clock here, it needs to match XO */
+ assigned-clocks = <&gcc GCC_RBCPR_CLK>;
+ assigned-clock-rates = <24000000>;
+
+ operating-points-v2 = <&cpr4_opp_table>;
+ power-domains = <&rpmpd IPQ9574_VDDAPC>;
+ #power-domain-cells = <1>;
+
+ nvmem-cells = <&cpr_efuse_speedbin>,
+ <&cpr_fuse_revision>,
+ <&cpr_quot0_pwrcl>,
+ <&cpr_quot1_pwrcl>,
+ <&cpr_quot2_pwrcl>,
+ <&cpr_quot3_pwrcl>,
+ <&cpr_quot_offset1_pwrcl>,
+ <&cpr_quot_offset2_pwrcl>,
+ <&cpr_quot_offset3_pwrcl>,
+ <&cpr_init_voltage0_pwrcl>,
+ <&cpr_init_voltage1_pwrcl>,
+ <&cpr_init_voltage2_pwrcl>,
+ <&cpr_init_voltage3_pwrcl>,
+ <&cpr_ro_sel0_pwrcl>,
+ <&cpr_ro_sel1_pwrcl>,
+ <&cpr_ro_sel2_pwrcl>,
+ <&cpr_ro_sel3_pwrcl>;
+ nvmem-cell-names = "cpr_speed_bin",
+ "cpr_fuse_revision",
+ "cpr0_quotient1",
+ "cpr0_quotient2",
+ "cpr0_quotient3",
+ "cpr0_quotient4",
+ "cpr0_quotient_offset2",
+ "cpr0_quotient_offset3",
+ "cpr0_quotient_offset4",
+ "cpr0_init_voltage1",
+ "cpr0_init_voltage2",
+ "cpr0_init_voltage3",
+ "cpr0_init_voltage4",
+ "cpr0_ring_osc1",
+ "cpr0_ring_osc2",
+ "cpr0_ring_osc3",
+ "cpr0_ring_osc4";
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v6 1/9] soc: qcom: cpr3: Fix 'acc_desc' usage
2024-07-10 6:10 ` [PATCH v6 1/9] soc: qcom: cpr3: Fix 'acc_desc' usage Varadarajan Narayanan
@ 2024-07-10 11:05 ` Konrad Dybcio
2024-07-10 11:10 ` Varadarajan Narayanan
0 siblings, 1 reply; 21+ messages in thread
From: Konrad Dybcio @ 2024-07-10 11:05 UTC (permalink / raw)
To: Varadarajan Narayanan, robh, krzk+dt, conor+dt, andersson,
mturquette, sboyd, ilia.lin, rafael, viresh.kumar, ulf.hansson,
quic_sibis, quic_rjendra, danila, neil.armstrong, otto.pflueger,
abel.vesa, luca, geert+renesas, stephan.gerhold, linux-arm-msm,
devicetree, linux-kernel, linux-pm, linux-clk
On 10.07.2024 8:10 AM, Varadarajan Narayanan wrote:
> cpr3 code assumes that 'acc_desc' is available for SoCs
> implementing CPR version 4 or less. However, IPQ9574 SoC
> implements CPRv4 without ACC. This causes NULL pointer accesses
> resulting in crashes. Hence, check if 'acc_desc' is populated
> before using it.
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
Does it not work if you drop this patch?
In v15, drv->tcsr is left NULL (from kzalloc), unless data->acc_desc
is present
Konrad
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 2/9] cpufreq: qcom-nvmem: Add support for IPQ9574
2024-07-10 6:10 ` [PATCH v6 2/9] cpufreq: qcom-nvmem: Add support for IPQ9574 Varadarajan Narayanan
@ 2024-07-10 11:05 ` Konrad Dybcio
0 siblings, 0 replies; 21+ messages in thread
From: Konrad Dybcio @ 2024-07-10 11:05 UTC (permalink / raw)
To: Varadarajan Narayanan, robh, krzk+dt, conor+dt, andersson,
mturquette, sboyd, ilia.lin, rafael, viresh.kumar, ulf.hansson,
quic_sibis, quic_rjendra, danila, neil.armstrong, otto.pflueger,
abel.vesa, luca, geert+renesas, stephan.gerhold, linux-arm-msm,
devicetree, linux-kernel, linux-pm, linux-clk
Cc: Dmitry Baryshkov
On 10.07.2024 8:10 AM, Varadarajan Narayanan wrote:
> IPQ9574 uses CPR4 power domain to manage core supplies. Use
> device-specific match data for this platform that includes
> genpd_names configuration.
>
> Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 1/9] soc: qcom: cpr3: Fix 'acc_desc' usage
2024-07-10 11:05 ` Konrad Dybcio
@ 2024-07-10 11:10 ` Varadarajan Narayanan
0 siblings, 0 replies; 21+ messages in thread
From: Varadarajan Narayanan @ 2024-07-10 11:10 UTC (permalink / raw)
To: Konrad Dybcio
Cc: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, ilia.lin,
rafael, viresh.kumar, ulf.hansson, quic_sibis, quic_rjendra,
danila, neil.armstrong, otto.pflueger, abel.vesa, luca,
geert+renesas, stephan.gerhold, linux-arm-msm, devicetree,
linux-kernel, linux-pm, linux-clk
On Wed, Jul 10, 2024 at 01:05:12PM +0200, Konrad Dybcio wrote:
> On 10.07.2024 8:10 AM, Varadarajan Narayanan wrote:
> > cpr3 code assumes that 'acc_desc' is available for SoCs
> > implementing CPR version 4 or less. However, IPQ9574 SoC
> > implements CPRv4 without ACC. This causes NULL pointer accesses
> > resulting in crashes. Hence, check if 'acc_desc' is populated
> > before using it.
> >
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
>
> Does it not work if you drop this patch?
>
> In v15, drv->tcsr is left NULL (from kzalloc), unless data->acc_desc
> is present
It crashed for me with NULL pointer access.
Unable to handle kernel NULL pointer dereference at virtual address 0000000000000010
input: gpio-keys as /devices/platform/gpio-keys/input/input0
Mem abort info:
ESR = 0x0000000096000004
EC = 0x25: DABT (current EL), IL = 32 bits
SET = 0, FnV = 0
EA = 0, S1PTW = 0
clk: Disabling unused clocks
FSC = 0x04: level 0 translation fault
Data abort info:
ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000
CM = 0, WnR = 0, TnD = 0, TagAccess = 0
PM: genpd: Disabling unused power domains
GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
[0000000000000010] user address but active_mm is swapper
Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP
Modules linked in:
CPU: 0 UID: 0 PID: 74 Comm: sugov:0 Not tainted 6.10.0-rc6-next-20240703-00018-g3dfa5a2e6f31-dirty #13
Hardware name: Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7 (DT)
pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : cpr_commit_state+0x228/0x2a8
lr : cpr_commit_state+0x10c/0x2a8
sp : ffff800086163a90
x29: ffff800086163a90 x28: 0000000000000000 x27: 0000000000000000
x26: 0000000000000000 x25: ffff000006953080 x24: ffff000006913280
x23: 00000000000fa3e8 x22: 00000000000fa3e8 x21: 00000000000fa3e8
x20: 0000000000000003 x19: 00000000000fa3e8 x18: 0000000000000000
x17: 63682d6963687820 x16: 0000000000000000 x15: ffff00003fc8fd00
x14: 0000000000000000 x13: 0000000000000001 x12: ffff8000814e8c60
x11: 0000000000000000 x10: 00000000000009b0 x9 : 0000000000000000
x8 : ffff00003fc87f40 x7 : 0000000000000240 x6 : 0000000000000002
x5 : 000000000000007f x4 : 0000000000000000 x3 : 0000000000000000
x2 : 0000000000000000 x1 : 0000000000000000 x0 : 0000000000000000
Call trace:
cpr_commit_state+0x228/0x2a8
cpr_set_performance_state+0x94/0xf4
_genpd_set_performance_state+0x190/0x1ac
genpd_set_performance_state.isra.0+0xbc/0xdc
genpd_dev_pm_set_performance_state+0x60/0xc0
dev_pm_domain_set_performance_state+0x24/0x3c
_set_opp+0xb4/0x51c
dev_pm_opp_set_opp+0x70/0xfc
_set_required_opps.isra.0+0x74/0xd4
_set_opp+0x90/0x51c
dev_pm_opp_set_rate+0x184/0x274
set_target+0x34/0x40
__cpufreq_driver_target+0x250/0x698
sugov_work+0x54/0x70
kthread_worker_fn+0xc4/0x174
kthread+0x110/0x114
ret_from_fork+0x10/0x20
Thanks
Varada
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 8/9] soc: qcom: cpr3: Add IPQ9574 definitions
2024-07-10 6:11 ` [PATCH v6 8/9] soc: qcom: cpr3: Add IPQ9574 definitions Varadarajan Narayanan
@ 2024-07-10 11:12 ` Konrad Dybcio
2024-07-11 4:58 ` Varadarajan Narayanan
0 siblings, 1 reply; 21+ messages in thread
From: Konrad Dybcio @ 2024-07-10 11:12 UTC (permalink / raw)
To: Varadarajan Narayanan, robh, krzk+dt, conor+dt, andersson,
mturquette, sboyd, ilia.lin, rafael, viresh.kumar, ulf.hansson,
quic_sibis, quic_rjendra, danila, neil.armstrong, otto.pflueger,
abel.vesa, luca, geert+renesas, stephan.gerhold, linux-arm-msm,
devicetree, linux-kernel, linux-pm, linux-clk
Cc: Praveenkumar I
On 10.07.2024 8:11 AM, Varadarajan Narayanan wrote:
> From: Praveenkumar I <quic_ipkumar@quicinc.com>
>
> * Add thread, scaling factor, CPR descriptor defines to enable
> CPR on IPQ9574.
>
> * Skip 'acc' usage since IPQ9574 does not have acc
>
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
[...]
>
> /* CPRh disallows MEM-ACC access from the HLOS */
> - if (!(data->acc_desc || desc->cpr_type == CTRL_TYPE_CPRH))
> + if (!(data->acc_desc || desc->cpr_type == CTRL_TYPE_CPRH ||
> + of_device_is_compatible(dev->of_node, "qcom,ipq9574-cpr4")))
> return dev_err_probe(dev, -EINVAL, "Invalid ACC data\n");
This is something I'd also like to fold into v16.. perhaps
if (data->acc_desc && desc->cpr_type == CTRL_TYPE_CPRH)
could work instead? this way we trust the programmer that
acc_desc's presence/absence is intentional and only throw and
error if it's present with type == CPRH
Konrad
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 8/9] soc: qcom: cpr3: Add IPQ9574 definitions
2024-07-10 11:12 ` Konrad Dybcio
@ 2024-07-11 4:58 ` Varadarajan Narayanan
0 siblings, 0 replies; 21+ messages in thread
From: Varadarajan Narayanan @ 2024-07-11 4:58 UTC (permalink / raw)
To: Konrad Dybcio
Cc: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, ilia.lin,
rafael, viresh.kumar, ulf.hansson, quic_sibis, quic_rjendra,
danila, neil.armstrong, otto.pflueger, abel.vesa, luca,
geert+renesas, stephan.gerhold, linux-arm-msm, devicetree,
linux-kernel, linux-pm, linux-clk, Praveenkumar I
On Wed, Jul 10, 2024 at 01:12:19PM +0200, Konrad Dybcio wrote:
> On 10.07.2024 8:11 AM, Varadarajan Narayanan wrote:
> > From: Praveenkumar I <quic_ipkumar@quicinc.com>
> >
> > * Add thread, scaling factor, CPR descriptor defines to enable
> > CPR on IPQ9574.
> >
> > * Skip 'acc' usage since IPQ9574 does not have acc
> >
> > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
>
> [...]
>
> >
> > /* CPRh disallows MEM-ACC access from the HLOS */
> > - if (!(data->acc_desc || desc->cpr_type == CTRL_TYPE_CPRH))
> > + if (!(data->acc_desc || desc->cpr_type == CTRL_TYPE_CPRH ||
> > + of_device_is_compatible(dev->of_node, "qcom,ipq9574-cpr4")))
> > return dev_err_probe(dev, -EINVAL, "Invalid ACC data\n");
>
> This is something I'd also like to fold into v16.. perhaps
>
> if (data->acc_desc && desc->cpr_type == CTRL_TYPE_CPRH)
>
> could work instead? this way we trust the programmer that
> acc_desc's presence/absence is intentional and only throw and
> error if it's present with type == CPRH
I tried this change and it works for ipq9574.
Thanks
Varada
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 5/9] pmdomain: qcom: rpmpd: Add IPQ9574 power domains
2024-07-10 6:10 ` [PATCH v6 5/9] pmdomain: qcom: rpmpd: Add IPQ9574 power domains Varadarajan Narayanan
@ 2024-07-16 12:15 ` Konrad Dybcio
2024-07-17 9:14 ` Varadarajan Narayanan
0 siblings, 1 reply; 21+ messages in thread
From: Konrad Dybcio @ 2024-07-16 12:15 UTC (permalink / raw)
To: Varadarajan Narayanan, robh, krzk+dt, conor+dt, andersson,
mturquette, sboyd, ilia.lin, rafael, viresh.kumar, ulf.hansson,
quic_sibis, quic_rjendra, danila, neil.armstrong, otto.pflueger,
abel.vesa, luca, geert+renesas, stephan.gerhold, linux-arm-msm,
devicetree, linux-kernel, linux-pm, linux-clk
Cc: Praveenkumar I, Dmitry Baryshkov
On 10.07.2024 8:10 AM, Varadarajan Narayanan wrote:
> From: Praveenkumar I <quic_ipkumar@quicinc.com>
>
> Add the APC power domain definitions used in IPQ9574.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
Could you please confirm [1]?
Konrad
[1] https://lore.kernel.org/linux-arm-msm/57dadb35-5dde-4127-87aa-962613730336@linaro.org/
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 5/9] pmdomain: qcom: rpmpd: Add IPQ9574 power domains
2024-07-16 12:15 ` Konrad Dybcio
@ 2024-07-17 9:14 ` Varadarajan Narayanan
2024-07-24 4:32 ` Varadarajan Narayanan
0 siblings, 1 reply; 21+ messages in thread
From: Varadarajan Narayanan @ 2024-07-17 9:14 UTC (permalink / raw)
To: Konrad Dybcio
Cc: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, ilia.lin,
rafael, viresh.kumar, ulf.hansson, quic_sibis, quic_rjendra,
danila, neil.armstrong, otto.pflueger, abel.vesa, luca,
geert+renesas, stephan.gerhold, linux-arm-msm, devicetree,
linux-kernel, linux-pm, linux-clk, Praveenkumar I,
Dmitry Baryshkov
On Tue, Jul 16, 2024 at 02:15:12PM +0200, Konrad Dybcio wrote:
> On 10.07.2024 8:10 AM, Varadarajan Narayanan wrote:
> > From: Praveenkumar I <quic_ipkumar@quicinc.com>
> >
> > Add the APC power domain definitions used in IPQ9574.
> >
> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
>
> Could you please confirm [1]?
>
> Konrad
>
> [1] https://lore.kernel.org/linux-arm-msm/57dadb35-5dde-4127-87aa-962613730336@linaro.org/
The author is off for a few days. Will get back to you once he is in.
Thanks
Varada
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 5/9] pmdomain: qcom: rpmpd: Add IPQ9574 power domains
2024-07-17 9:14 ` Varadarajan Narayanan
@ 2024-07-24 4:32 ` Varadarajan Narayanan
2024-07-24 17:26 ` Dmitry Baryshkov
0 siblings, 1 reply; 21+ messages in thread
From: Varadarajan Narayanan @ 2024-07-24 4:32 UTC (permalink / raw)
To: Konrad Dybcio
Cc: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, ilia.lin,
rafael, viresh.kumar, ulf.hansson, quic_sibis, quic_rjendra,
danila, neil.armstrong, otto.pflueger, abel.vesa, luca,
geert+renesas, stephan.gerhold, linux-arm-msm, devicetree,
linux-kernel, linux-pm, linux-clk, Praveenkumar I,
Dmitry Baryshkov
On Wed, Jul 17, 2024 at 02:44:08PM +0530, Varadarajan Narayanan wrote:
> On Tue, Jul 16, 2024 at 02:15:12PM +0200, Konrad Dybcio wrote:
> > On 10.07.2024 8:10 AM, Varadarajan Narayanan wrote:
> > > From: Praveenkumar I <quic_ipkumar@quicinc.com>
> > >
> > > Add the APC power domain definitions used in IPQ9574.
> > >
> > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > > ---
> >
> > Could you please confirm [1]?
> >
> > Konrad
> >
> > [1] https://lore.kernel.org/linux-arm-msm/57dadb35-5dde-4127-87aa-962613730336@linaro.org/
>
> The author is off for a few days. Will get back to you once he is in.
Have responded to that query. Please see https://lore.kernel.org/linux-arm-msm/ZqCCpf1FwLWulSgr@hu-varada-blr.qualcomm.com/
Thanks
Varada
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 5/9] pmdomain: qcom: rpmpd: Add IPQ9574 power domains
2024-07-24 4:32 ` Varadarajan Narayanan
@ 2024-07-24 17:26 ` Dmitry Baryshkov
2024-08-05 10:32 ` Ulf Hansson
0 siblings, 1 reply; 21+ messages in thread
From: Dmitry Baryshkov @ 2024-07-24 17:26 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: Konrad Dybcio, robh, krzk+dt, conor+dt, andersson, mturquette,
sboyd, ilia.lin, rafael, viresh.kumar, ulf.hansson, quic_sibis,
quic_rjendra, danila, neil.armstrong, otto.pflueger, abel.vesa,
luca, geert+renesas, stephan.gerhold, linux-arm-msm, devicetree,
linux-kernel, linux-pm, linux-clk, Praveenkumar I
On Wed, Jul 24, 2024 at 10:02:31AM GMT, Varadarajan Narayanan wrote:
> On Wed, Jul 17, 2024 at 02:44:08PM +0530, Varadarajan Narayanan wrote:
> > On Tue, Jul 16, 2024 at 02:15:12PM +0200, Konrad Dybcio wrote:
> > > On 10.07.2024 8:10 AM, Varadarajan Narayanan wrote:
> > > > From: Praveenkumar I <quic_ipkumar@quicinc.com>
> > > >
> > > > Add the APC power domain definitions used in IPQ9574.
> > > >
> > > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> > > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > > > ---
> > >
> > > Could you please confirm [1]?
> > >
> > > Konrad
> > >
> > > [1] https://lore.kernel.org/linux-arm-msm/57dadb35-5dde-4127-87aa-962613730336@linaro.org/
> >
> > The author is off for a few days. Will get back to you once he is in.
>
> Have responded to that query. Please see https://lore.kernel.org/linux-arm-msm/ZqCCpf1FwLWulSgr@hu-varada-blr.qualcomm.com/
If it responds to voltage values, please model it as a regulator rather
than a power domain.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 5/9] pmdomain: qcom: rpmpd: Add IPQ9574 power domains
2024-07-24 17:26 ` Dmitry Baryshkov
@ 2024-08-05 10:32 ` Ulf Hansson
2024-08-20 6:19 ` Varadarajan Narayanan
0 siblings, 1 reply; 21+ messages in thread
From: Ulf Hansson @ 2024-08-05 10:32 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Varadarajan Narayanan, Konrad Dybcio, robh, krzk+dt, conor+dt,
andersson, mturquette, sboyd, ilia.lin, rafael, viresh.kumar,
quic_sibis, quic_rjendra, danila, neil.armstrong, otto.pflueger,
abel.vesa, luca, geert+renesas, stephan.gerhold, linux-arm-msm,
devicetree, linux-kernel, linux-pm, linux-clk, Praveenkumar I
On Wed, 24 Jul 2024 at 19:26, Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On Wed, Jul 24, 2024 at 10:02:31AM GMT, Varadarajan Narayanan wrote:
> > On Wed, Jul 17, 2024 at 02:44:08PM +0530, Varadarajan Narayanan wrote:
> > > On Tue, Jul 16, 2024 at 02:15:12PM +0200, Konrad Dybcio wrote:
> > > > On 10.07.2024 8:10 AM, Varadarajan Narayanan wrote:
> > > > > From: Praveenkumar I <quic_ipkumar@quicinc.com>
> > > > >
> > > > > Add the APC power domain definitions used in IPQ9574.
> > > > >
> > > > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> > > > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > > > > ---
> > > >
> > > > Could you please confirm [1]?
> > > >
> > > > Konrad
> > > >
> > > > [1] https://lore.kernel.org/linux-arm-msm/57dadb35-5dde-4127-87aa-962613730336@linaro.org/
> > >
> > > The author is off for a few days. Will get back to you once he is in.
> >
> > Have responded to that query. Please see https://lore.kernel.org/linux-arm-msm/ZqCCpf1FwLWulSgr@hu-varada-blr.qualcomm.com/
>
> If it responds to voltage values, please model it as a regulator rather
> than a power domain.
Just wanted to give my brief opinion around this too.
I agree that it seems to make sense to model it as a regulator, but
that doesn't necessarily mean that we shouldn't model it as a
power-domain too.
If it is a power-domain it should be modelled like that - and then the
power-domain provider should be assigned as the consumer of that
regulator.
Kind regards
Uffe
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 5/9] pmdomain: qcom: rpmpd: Add IPQ9574 power domains
2024-08-05 10:32 ` Ulf Hansson
@ 2024-08-20 6:19 ` Varadarajan Narayanan
0 siblings, 0 replies; 21+ messages in thread
From: Varadarajan Narayanan @ 2024-08-20 6:19 UTC (permalink / raw)
To: Ulf Hansson
Cc: Dmitry Baryshkov, Konrad Dybcio, robh, krzk+dt, conor+dt,
andersson, mturquette, sboyd, ilia.lin, rafael, viresh.kumar,
quic_sibis, quic_rjendra, danila, neil.armstrong, otto.pflueger,
abel.vesa, luca, geert+renesas, stephan.gerhold, linux-arm-msm,
devicetree, linux-kernel, linux-pm, linux-clk, Praveenkumar I
On Mon, Aug 05, 2024 at 12:32:34PM +0200, Ulf Hansson wrote:
> On Wed, 24 Jul 2024 at 19:26, Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
> >
> > On Wed, Jul 24, 2024 at 10:02:31AM GMT, Varadarajan Narayanan wrote:
> > > On Wed, Jul 17, 2024 at 02:44:08PM +0530, Varadarajan Narayanan wrote:
> > > > On Tue, Jul 16, 2024 at 02:15:12PM +0200, Konrad Dybcio wrote:
> > > > > On 10.07.2024 8:10 AM, Varadarajan Narayanan wrote:
> > > > > > From: Praveenkumar I <quic_ipkumar@quicinc.com>
> > > > > >
> > > > > > Add the APC power domain definitions used in IPQ9574.
> > > > > >
> > > > > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > > > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> > > > > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > > > > > ---
> > > > >
> > > > > Could you please confirm [1]?
> > > > >
> > > > > Konrad
> > > > >
> > > > > [1] https://lore.kernel.org/linux-arm-msm/57dadb35-5dde-4127-87aa-962613730336@linaro.org/
> > > >
> > > > The author is off for a few days. Will get back to you once he is in.
> > >
> > > Have responded to that query. Please see https://lore.kernel.org/linux-arm-msm/ZqCCpf1FwLWulSgr@hu-varada-blr.qualcomm.com/
> >
> > If it responds to voltage values, please model it as a regulator rather
> > than a power domain.
>
> Just wanted to give my brief opinion around this too.
>
> I agree that it seems to make sense to model it as a regulator, but
> that doesn't necessarily mean that we shouldn't model it as a
> power-domain too.
>
> If it is a power-domain it should be modelled like that - and then the
> power-domain provider should be assigned as the consumer of that
> regulator.
Have posted V7 (without modelling as power-domain).
Please review.
Thanks
Varada
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2024-08-20 6:19 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-07-10 6:10 [PATCH v6 0/9] Enable CPR for IPQ9574 Varadarajan Narayanan
2024-07-10 6:10 ` [PATCH v6 1/9] soc: qcom: cpr3: Fix 'acc_desc' usage Varadarajan Narayanan
2024-07-10 11:05 ` Konrad Dybcio
2024-07-10 11:10 ` Varadarajan Narayanan
2024-07-10 6:10 ` [PATCH v6 2/9] cpufreq: qcom-nvmem: Add support for IPQ9574 Varadarajan Narayanan
2024-07-10 11:05 ` Konrad Dybcio
2024-07-10 6:10 ` [PATCH v6 3/9] dt-bindings: power: rpmpd: Add IPQ9574 power domains Varadarajan Narayanan
2024-07-10 6:10 ` [PATCH v6 4/9] dt-bindings: soc: qcom: cpr3: Add bindings for IPQ9574 Varadarajan Narayanan
2024-07-10 6:10 ` [PATCH v6 5/9] pmdomain: qcom: rpmpd: Add IPQ9574 power domains Varadarajan Narayanan
2024-07-16 12:15 ` Konrad Dybcio
2024-07-17 9:14 ` Varadarajan Narayanan
2024-07-24 4:32 ` Varadarajan Narayanan
2024-07-24 17:26 ` Dmitry Baryshkov
2024-08-05 10:32 ` Ulf Hansson
2024-08-20 6:19 ` Varadarajan Narayanan
2024-07-10 6:10 ` [PATCH v6 6/9] dt-bindings: clock: Add CPR clock defines for IPQ9574 Varadarajan Narayanan
2024-07-10 6:11 ` [PATCH v6 7/9] clk: qcom: gcc-ipq9574: Add CPR clock definition Varadarajan Narayanan
2024-07-10 6:11 ` [PATCH v6 8/9] soc: qcom: cpr3: Add IPQ9574 definitions Varadarajan Narayanan
2024-07-10 11:12 ` Konrad Dybcio
2024-07-11 4:58 ` Varadarajan Narayanan
2024-07-10 6:11 ` [PATCH v6 9/9] arm64: dts: qcom: ipq9574: Enable CPR Varadarajan Narayanan
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