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X-CSE-ConnectionGUID: bfogTIZBTnunq0Cr87dWRg== X-CSE-MsgGUID: nC+kqSMJToOQLV/PefyeLA== X-IronPort-AV: E=McAfee;i="6600,9927,11041"; a="8477867" X-IronPort-AV: E=Sophos;i="6.07,195,1708416000"; d="scan'208";a="8477867" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2024 23:17:46 -0700 X-CSE-ConnectionGUID: WoPCkQFySrilZjLdRbsGNQ== X-CSE-MsgGUID: MwvHk+UERuqY7ad9C/NZjw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,195,1708416000"; d="scan'208";a="21185053" Received: from xiongzha-mobl1.ccr.corp.intel.com (HELO [10.124.244.162]) ([10.124.244.162]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2024 23:17:41 -0700 Message-ID: <3a0c2542-2aa7-464b-8a09-e09e570c88da@linux.intel.com> Date: Fri, 12 Apr 2024 14:17:38 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 07/41] perf/x86: Add interface to reflect virtual LVTPC_MASK bit onto HW Content-Language: en-US To: Sean Christopherson Cc: pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, Xiong Zhang References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> <20240126085444.324918-8-xiong.y.zhang@linux.intel.com> From: "Zhang, Xiong Y" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 4/12/2024 3:21 AM, Sean Christopherson wrote: > On Fri, Jan 26, 2024, Xiong Zhang wrote: >> From: Xiong Zhang >> >> When guest clear LVTPC_MASK bit in guest PMI handler at PMU passthrough >> mode, this bit should be reflected onto HW, otherwise HW couldn't generate >> PMI again during VM running until it is cleared. > > This fixes a bug in the previous patch, i.e. this should not be a standalone > patch. > >> >> This commit set HW LVTPC_MASK bit at PMU vecctor switching to KVM PMI >> vector. >> >> Signed-off-by: Xiong Zhang >> Signed-off-by: Mingwei Zhang >> --- >> arch/x86/events/core.c | 9 +++++++-- >> arch/x86/include/asm/perf_event.h | 2 +- >> arch/x86/kvm/lapic.h | 1 - >> 3 files changed, 8 insertions(+), 4 deletions(-) >> >> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c >> index 3f87894d8c8e..ece042cfb470 100644 >> --- a/arch/x86/events/core.c >> +++ b/arch/x86/events/core.c >> @@ -709,13 +709,18 @@ void perf_guest_switch_to_host_pmi_vector(void) >> } >> EXPORT_SYMBOL_GPL(perf_guest_switch_to_host_pmi_vector); >> >> -void perf_guest_switch_to_kvm_pmi_vector(void) >> +void perf_guest_switch_to_kvm_pmi_vector(bool mask) >> { >> lockdep_assert_irqs_disabled(); >> >> - apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_VPMU_VECTOR); >> + if (mask) >> + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_VPMU_VECTOR | >> + APIC_LVT_MASKED); >> + else >> + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_VPMU_VECTOR); >> } > > Or more simply: > > void perf_guest_enter(u32 guest_lvtpc) > { > ... > > apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_VPMU_VECTOR | > (guest_lvtpc & APIC_LVT_MASKED)); > } > > and then on the KVM side: > > perf_guest_enter(kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVTPC)); > > because an in-kernel APIC should be a hard requirement for the mediated PMU. > this is simpler and we will follow this. thanks