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Sat, 12 Aug 2023 08:58:32 GMT Received: from [10.216.24.170] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Sat, 12 Aug 2023 01:58:26 -0700 Message-ID: <3c1a9e91-d49a-b191-4f3c-506fe41ea343@quicinc.com> Date: Sat, 12 Aug 2023 14:28:21 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.1 Subject: Re: [PATCH v8 6/9] usb: dwc3: qcom: Add multiport controller support for qcom wrapper To: Konrad Dybcio , Johan Hovold , Wesley Cheng , Jack Pham CC: Thinh Nguyen , Greg Kroah-Hartman , Philipp Zabel , "Andy Gross" , Bjorn Andersson , "Rob Herring" , Krzysztof Kozlowski , Felipe Balbi , , , , , , , References: <20230514054917.21318-1-quic_kriskura@quicinc.com> <20230514054917.21318-7-quic_kriskura@quicinc.com> <26ae15d1-4e13-3ab7-6844-3a7d3ed03af4@quicinc.com> Content-Language: en-US From: Krishna Kurapati PSSNV In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: K3bohqmYqcvvVu6ynYL486F_dmSVTPK0 X-Proofpoint-ORIG-GUID: K3bohqmYqcvvVu6ynYL486F_dmSVTPK0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-12_07,2023-08-10_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 mlxscore=0 lowpriorityscore=0 adultscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 bulkscore=0 malwarescore=0 impostorscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308120082 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/11/2023 10:18 PM, Konrad Dybcio wrote: > On 21.07.2023 14:54, Johan Hovold wrote: >> On Fri, Jul 21, 2023 at 02:10:07PM +0200, Konrad Dybcio wrote: >>> On 21.07.2023 13:16, Johan Hovold wrote: >>>> On Fri, Jul 14, 2023 at 04:08:45PM +0530, Krishna Kurapati PSSNV wrote: >>>>> On 7/14/2023 2:30 PM, Johan Hovold wrote: >>>>>> On Mon, Jul 03, 2023 at 12:35:48AM +0530, Krishna Kurapati PSSNV wrote: >>>>>>> On 6/27/2023 9:13 PM, Johan Hovold wrote: >>>>>>>> On Wed, Jun 07, 2023 at 02:16:37PM +0200, Johan Hovold wrote: >>>>>>>>> On Sun, May 14, 2023 at 11:19:14AM +0530, Krishna Kurapati wrote: >>>>>> >>>>>>>>>> - val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG); >>>>>>>>>> - if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) >>>>>>>>>> - dev_err(qcom->dev, "HS-PHY not in L2\n"); >>>>>>>>>> + for (i = 0; i < dwc->num_usb2_ports; i++) { >>>>>>>>>> + val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg_offset[i]); >>>>>>>>>> + if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) >>>>>>>>>> + dev_err(qcom->dev, "HS-PHY%d not in L2\n", i); >>>>>>>>>> + } >>>>>>>> >>>>>>>>> When testing this on the X13s I get: >>>>>>>>> >>>>>>>>> dwc3-qcom a4f8800.usb: HS-PHY2 not in L2 >> >>> Sidenote, I get this on any Qcom device on any platform I try >>> to enter suspend on, without these MP patches. >> >> Ok, that might provide some hint. But on sc8280xp (X13s) we only get it >> on one of the four MP ports (i.e. on one out of six ports in total). >> >> While on sa8295p-adp there are no such errors on any port. > I've been playing with 8450 and it looks like snps,dis_u2_susphy_quirk > causes this error. > > The downstream tree contains this property and I'm inclined to believe > it means that this platforms should define it (as the devicetrees are > machine-generated to a degree, AFAIK), especially since this quirk does > the exact same thing on a known-working downstream, namely unsetting > DWC3_GUSB2PHYCFG_SUSPHY. > > Digging a bit deeper, dwc3-msm-core [1], the downstream version of dwc3-qcom > performs a bit of a dance in a couple of places.. Look for that register name. > > Unfortunately I have little idea what the "USB2 suspend phy" is.. is it a PHY > used in suspend? Is it the suspension of the USB2 PHY? No clue. > > [1] https://git.codelinaro.org/clo/la/kernel/msm-5.10/-/blob/KERNEL.PLATFORM.1.0.r2-08800-WAIPIOLE.0/drivers/usb/dwc3/dwc3-msm-core.c > The description for that bit (BIT(6)) as per the databook is as follows: --- 6 SUSPENDUSB20 R_W Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG configurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the application must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. For all other configurations, this bit can be set to 1 during core configuration. Note: ■ In host mode, on reset, this bit is set to 1. Software can override this bit after reset. ■ In device mode, before issuing any device endpoint command when operating in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bit when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed --- "L2" is the term we say when PHY is suspended, i.e., the main PLL is shut off. Internally, I was able to find out that there are several conditions where phy can fail to enter L2. The entry into L2 is controlled by the USB controller itself, but can be limited by toggling GUSB2PHY SUSPENDABLE bit. if that bit is 0 then controller won't place HSPHY into L2. For the failure to enter L2, there can be several situations, like there may be some pending line state change that happened on the bus. But Johan's error seems to be different as the register itself reads zero which I don't understand. Regards, Krishna,