From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750869AbcBAXCT (ORCPT ); Mon, 1 Feb 2016 18:02:19 -0500 Received: from foss.arm.com ([217.140.101.70]:52228 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750721AbcBAXCR (ORCPT ); Mon, 1 Feb 2016 18:02:17 -0500 From: =?UTF-8?Q?Andr=c3=a9_Przywara?= Subject: Re: [PATCH 06/11] clk: sunxi: add generic multi-parent bus clock gates driver To: Jean-Francois Moine References: <1454348370-3816-1-git-send-email-andre.przywara@arm.com> <1454348370-3816-7-git-send-email-andre.przywara@arm.com> <20160201194000.282a253b14a2ab35df8b8cc7@free.fr> Cc: Maxime Ripard , Chen-Yu Tsai , linux-sunxi@googlegroups.com, Arnd Bergmann , =?UTF-8?Q?Emilio_L=c3=b3pez?= , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, Jens Kuske , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Organization: ARM Ltd. Message-ID: <56AFE3D8.1000701@arm.com> Date: Mon, 1 Feb 2016 23:01:44 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <20160201194000.282a253b14a2ab35df8b8cc7@free.fr> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/02/16 18:40, Jean-Francois Moine wrote: > On Mon, 1 Feb 2016 17:39:25 +0000 > Andre Przywara wrote: > >> The Allwinner H3 SoC introduced bus clock gates with potentially >> different parents per clock gate. The H3 driver chose to hardcode the >> actual parent clock relation in the code. >> Add a new driver (which has the potential to drive the H3 and also >> the simple clock gates as well) which uses the power of DT to describe >> this relationship in an elegant and flexible way. >> Using one subnode for every parent clock we get away with a single >> DT compatible match, which can be used as a fallback value in the >> actual DTs without the need to add specific compatible strings to the >> code. This avoids adding a new driver or function for every new SoC. >> >> Signed-off-by: Andre Przywara >> --- >> Changelog RFC .. v1: >> - fix IRQ muxes to cover the three banks of the SoC >> - amend naming of PCM pins Just got embarrassed with seeing that this changelog here actually belongs into the previous patch :$ >> >> drivers/clk/sunxi/Makefile | 1 + >> drivers/clk/sunxi/clk-multi-gates.c | 105 ++++++++++++++++++++++++++++++++++++ >> 2 files changed, 106 insertions(+) >> create mode 100644 drivers/clk/sunxi/clk-multi-gates.c > [snip] > > Glad to see that things are moving to the right way. Thanks. > Acked-by: Jean-Francois Moine Thanks! I am relived to hear that (and hope that others agree as well ;-) If people are Ok with that approach I can do patches to move all existing clock gates into one driver, but I guess this would be part of a later series. Cheers, Andre.