From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753443AbcCAL4p (ORCPT ); Tue, 1 Mar 2016 06:56:45 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:36932 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753326AbcCAL4n (ORCPT ); Tue, 1 Mar 2016 06:56:43 -0500 Subject: Re: [PATCH v3 3/3] pci: dra7xx: use pdata callbacks to perform reset To: Paul Walmsley References: <1452780672-14339-1-git-send-email-kishon@ti.com> <1452780672-14339-4-git-send-email-kishon@ti.com> <20160127173104.GQ19432@atomide.com> <56A90971.4020409@ti.com> <20160127185649.GV19432@atomide.com> <56A94FB7.6020903@ti.com> <20160128183156.GH19432@atomide.com> <56B087AD.4000505@ti.com> <56B900E9.9040306@ti.com> <56BA2495.9020407@ti.com> <56BA958A.1020503@ti.com> <56BACCDB.2070507@ti.com> <56BD8091.4090007@ti.com> <56BE1454.3030002@ti.com> <56C5D377.50901@ti.com> <56CAA82D.6000507@ti.com> <56CADB23.8020202@ti.com> <56CC490F.3040301@ti.com> <56CD4BE1.3010701@ti.com> CC: Sekhar Nori , Suman Anna , , Tony Lindgren , Bjorn Helgaas , , Russell King , , , From: Kishon Vijay Abraham I Message-ID: <56D5834C.5030800@ti.com> Date: Tue, 1 Mar 2016 17:25:56 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Tuesday 01 March 2016 01:55 PM, Paul Walmsley wrote: > > Folks, the following is what I've queued for this. Thanks Paul. Bjorn, With this patch merged, enabling pci-dra7xx won't result in system freeze anymore. I can send a patch to revert depends on BROKEN. Thanks Kishon > > > - Paul > > > From: Sekhar Nori > Date: Thu, 18 Feb 2016 16:49:56 +0530 > Subject: [PATCH] ARM: DRA7: hwmod: Add custom reset handler for PCIeSS > > Add a custom reset handler for DRA7x PCIeSS. This > handler is required to deassert PCIe hardreset lines > after they have been asserted. > > This enables the PCIe driver to access registers after > PCIeSS has been runtime enabled without having to > deassert hardreset lines itself. > > With this patch applied, used lspci to make sure > connected PCIe device enumerates on DRA74x and DRA72x > EVMs. > > Signed-off-by: Sekhar Nori > Reported-by: Richard Cochran > Tested-by: Kishon Vijay Abraham I > Cc: Suman Anna > Cc: Dave Gerlach > Cc: Tony Lindgren > Cc: Bjorn Helgaas > Cc: Russell King > Signed-off-by: Paul Walmsley > --- > arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c > index b61355e2a771..252b74633e31 100644 > --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c > +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c > @@ -1526,8 +1526,31 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = { > * > */ > > +/* > + * As noted in documentation for _reset() in omap_hwmod.c, the stock reset > + * functionality of OMAP HWMOD layer does not deassert the hardreset lines > + * associated with an IP automatically leaving the driver to handle that > + * by itself. This does not work for PCIeSS which needs the reset lines > + * deasserted for the driver to start accessing registers. > + * > + * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset > + * lines after asserting them. > + */ > +static int dra7xx_pciess_reset(struct omap_hwmod *oh) > +{ > + int i; > + > + for (i = 0; i < oh->rst_lines_cnt; i++) { > + omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name); > + omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name); > + } > + > + return 0; > +} > + > static struct omap_hwmod_class dra7xx_pciess_hwmod_class = { > .name = "pcie", > + .reset = dra7xx_pciess_reset, > }; > > /* pcie1 */ >