From: Christophe Leroy <christophe.leroy@c-s.fr>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
Michael Ellerman <mpe@ellerman.id.au>,
Scott Wood <oss@buserror.net>
Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
Subject: [PATCH v5 16/23] powerpc/8xx: rewrite set_context() in C
Date: Wed, 3 Feb 2016 23:54:27 +0100 (CET) [thread overview]
Message-ID: <59bd0cb31204c68d15a8d7a3df3dfbf8412a546d.1454538978.git.christophe.leroy@c-s.fr> (raw)
In-Reply-To: <cover.1454538974.git.christophe.leroy@c-s.fr>
There is no real need to have set_context() in assembly.
Now that we have mtspr() handling CPU6 ERRATA directly, we
can rewrite set_context() in C language for easier maintenance.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
v2: no change
v3: no change
v4: no change
v5: no change
arch/powerpc/kernel/head_8xx.S | 44 ------------------------------------------
arch/powerpc/mm/8xx_mmu.c | 34 ++++++++++++++++++++++++++++++++
2 files changed, 34 insertions(+), 44 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 637f8e9..bb2b657 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -968,50 +968,6 @@ initial_mmu:
/*
- * Set up to use a given MMU context.
- * r3 is context number, r4 is PGD pointer.
- *
- * We place the physical address of the new task page directory loaded
- * into the MMU base register, and set the ASID compare register with
- * the new "context."
- */
-_GLOBAL(set_context)
-
-#ifdef CONFIG_BDI_SWITCH
- /* Context switch the PTE pointer for the Abatron BDI2000.
- * The PGDIR is passed as second argument.
- */
- lis r5, KERNELBASE@h
- lwz r5, 0xf0(r5)
- stw r4, 0x4(r5)
-#endif
-
- /* Register M_TW will contain base address of level 1 table minus the
- * lower part of the kernel PGDIR base address, so that all accesses to
- * level 1 table are done relative to lower part of kernel PGDIR base
- * address.
- */
- li r5, (swapper_pg_dir-PAGE_OFFSET)@l
- sub r4, r4, r5
- tophys (r4, r4)
-#ifdef CONFIG_8xx_CPU6
- lis r6, cpu6_errata_word@h
- ori r6, r6, cpu6_errata_word@l
- li r7, 0x3f80
- stw r7, 12(r6)
- lwz r7, 12(r6)
-#endif
- mtspr SPRN_M_TW, r4 /* Update pointeur to level 1 table */
-#ifdef CONFIG_8xx_CPU6
- li r7, 0x3380
- stw r7, 12(r6)
- lwz r7, 12(r6)
-#endif
- mtspr SPRN_M_CASID, r3 /* Update context */
- SYNC
- blr
-
-/*
* We put a few things here that have to be page-aligned.
* This stuff goes at the beginning of the data segment,
* which is page-aligned.
diff --git a/arch/powerpc/mm/8xx_mmu.c b/arch/powerpc/mm/8xx_mmu.c
index 6965575..8701e4d 100644
--- a/arch/powerpc/mm/8xx_mmu.c
+++ b/arch/powerpc/mm/8xx_mmu.c
@@ -147,3 +147,37 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base,
memblock_set_current_limit(min_t(u64, first_memblock_size,
initial_memory_size));
}
+
+/*
+ * Set up to use a given MMU context.
+ * id is context number, pgd is PGD pointer.
+ *
+ * We place the physical address of the new task page directory loaded
+ * into the MMU base register, and set the ASID compare register with
+ * the new "context."
+ */
+void set_context(unsigned long id, pgd_t *pgd)
+{
+ s16 offset = (s16)(__pa(swapper_pg_dir));
+
+#ifdef CONFIG_BDI_SWITCH
+ pgd_t **ptr = *(pgd_t ***)(KERNELBASE + 0xf0);
+
+ /* Context switch the PTE pointer for the Abatron BDI2000.
+ * The PGDIR is passed as second argument.
+ */
+ *(ptr + 1) = pgd;
+#endif
+
+ /* Register M_TW will contain base address of level 1 table minus the
+ * lower part of the kernel PGDIR base address, so that all accesses to
+ * level 1 table are done relative to lower part of kernel PGDIR base
+ * address.
+ */
+ mtspr(SPRN_M_TW, __pa(pgd) - offset);
+
+ /* Update context */
+ mtspr(SPRN_M_CASID, id);
+ /* sync */
+ mb();
+}
--
2.1.0
next prev parent reply other threads:[~2016-02-03 22:57 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-03 22:53 [PATCH v5 00/23] powerpc/8xx: Use large pages for RAM and IMMR and other improvments Christophe Leroy
2016-02-03 22:53 ` [PATCH v5 01/23] powerpc/8xx: Save r3 all the time in DTLB miss handler Christophe Leroy
2016-02-03 22:53 ` [PATCH v5 02/23] powerpc/8xx: Map linear kernel RAM with 8M pages Christophe Leroy
2016-02-03 22:53 ` [PATCH v5 03/23] powerpc: Update documentation for noltlbs kernel parameter Christophe Leroy
2016-02-03 22:53 ` [PATCH v5 04/23] powerpc/8xx: move setup_initial_memory_limit() into 8xx_mmu.c Christophe Leroy
2016-02-03 22:53 ` [PATCH v5 05/23] powerpc32: Fix pte_offset_kernel() to return NULL for bad pages Christophe Leroy
2016-02-03 22:54 ` [PATCH v5 06/23] powerpc32: refactor x_mapped_by_bats() and x_mapped_by_tlbcam() together Christophe Leroy
2016-02-07 9:42 ` kbuild test robot
2016-02-03 22:54 ` [PATCH v5 07/23] powerpc/8xx: Fix vaddr for IMMR early remap Christophe Leroy
2016-02-03 22:54 ` [PATCH v5 08/23] powerpc/8xx: Map IMMR area with 512k page at a fixed address Christophe Leroy
2016-02-04 9:58 ` kbuild test robot
2016-02-03 22:54 ` [PATCH v5 09/23] powerpc/8xx: CONFIG_PIN_TLB unneeded for CONFIG_PPC_EARLY_DEBUG_CPM Christophe Leroy
2016-02-03 22:54 ` [PATCH v5 10/23] powerpc/8xx: map more RAM at startup when needed Christophe Leroy
2016-02-03 22:54 ` [PATCH v5 11/23] powerpc32: Remove useless/wrong MMU:setio progress message Christophe Leroy
2016-02-03 22:54 ` [PATCH v5 12/23] powerpc32: remove ioremap_base Christophe Leroy
2016-02-03 22:54 ` [PATCH v5 13/23] powerpc/8xx: Add missing SPRN defines into reg_8xx.h Christophe Leroy
2016-02-03 22:54 ` [PATCH v5 14/23] powerpc/8xx: Handle CPU6 ERRATA directly in mtspr() macro Christophe Leroy
2016-02-03 22:54 ` [PATCH v5 15/23] powerpc/8xx: remove special handling of CPU6 errata in set_dec() Christophe Leroy
2016-02-03 22:54 ` Christophe Leroy [this message]
2016-02-03 22:54 ` [PATCH v5 17/23] powerpc/8xx: rewrite flush_instruction_cache() in C Christophe Leroy
2016-02-03 22:54 ` [PATCH v5 18/23] powerpc: add inline functions for cache related instructions Christophe Leroy
2016-02-03 22:54 ` [PATCH v5 19/23] powerpc32: Remove clear_pages() and define clear_page() inline Christophe Leroy
2016-02-03 22:54 ` [PATCH v5 20/23] powerpc32: move xxxxx_dcache_range() functions inline Christophe Leroy
2016-02-03 22:54 ` [PATCH v5 21/23] powerpc: Simplify test in __dma_sync() Christophe Leroy
2016-02-04 11:37 ` Denis Kirjanov
2016-02-04 13:42 ` Christophe Leroy
2016-02-05 7:52 ` Denis Kirjanov
2016-02-05 7:56 ` Christophe Leroy
2016-02-03 22:54 ` [PATCH v5 22/23] powerpc32: small optimisation in flush_icache_range() Christophe Leroy
2016-02-03 22:54 ` [PATCH v5 23/23] powerpc32: Remove one insn in mulhdu Christophe Leroy
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