From: Robin Murphy <robin.murphy@arm.com>
To: Colton Lewis <coltonlewis@google.com>, kvm@vger.kernel.org
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev,
Ricardo Koller <ricarkol@google.com>
Subject: Re: [PATCH 1/3] arm64: Add a capability for FEAT_BBM level 2
Date: Mon, 5 Jun 2023 16:07:09 +0100 [thread overview]
Message-ID: <79f43d6b-7407-56c5-3c7d-c8fc48625e95@arm.com> (raw)
In-Reply-To: <20230602170147.1541355-2-coltonlewis@google.com>
On 2023-06-02 18:01, Colton Lewis wrote:
> From: Ricardo Koller <ricarkol@google.com>
>
> Add a new capability to detect "Stage-2 Translation table
> break-before-make" (FEAT_BBM) level 2.
Why does this patch invent spurious "stage 2" references everywhere? The
full name of FEAT_BBM is "Translation table break-before-make levels",
and it is not specific to one stage of translation.
Thanks,
Robin.
> Signed-off-by: Ricardo Koller <ricarkol@google.com>
> ---
> arch/arm64/kernel/cpufeature.c | 11 +++++++++++
> arch/arm64/tools/cpucaps | 1 +
> 2 files changed, 12 insertions(+)
>
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index c331c49a7d19c..c538060f7f66b 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -2455,6 +2455,17 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
> .min_field_value = 1,
> .matches = has_cpuid_feature,
> },
> + {
> + .desc = "Stage-2 Translation table break-before-make level 2",
> + .type = ARM64_CPUCAP_SYSTEM_FEATURE,
> + .capability = ARM64_HAS_STAGE2_BBM2,
> + .sys_reg = SYS_ID_AA64MMFR2_EL1,
> + .sign = FTR_UNSIGNED,
> + .field_pos = ID_AA64MMFR2_EL1_BBM_SHIFT,
> + .field_width = 4,
> + .min_field_value = 2,
> + .matches = has_cpuid_feature,
> + },
> {
> .desc = "TLB range maintenance instructions",
> .capability = ARM64_HAS_TLB_RANGE,
> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
> index 40ba95472594d..010aca1892642 100644
> --- a/arch/arm64/tools/cpucaps
> +++ b/arch/arm64/tools/cpucaps
> @@ -41,6 +41,7 @@ HAS_PAN
> HAS_RAS_EXTN
> HAS_RNG
> HAS_SB
> +HAS_STAGE2_BBM2
> HAS_STAGE2_FWB
> HAS_TIDCP1
> HAS_TLB_RANGE
> --
> 2.41.0.rc0.172.g3f132b7071-goog
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-06-05 15:07 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-02 17:01 [PATCH 0/3] Relax break-before-make use with FEAT_BBM Colton Lewis
2023-06-02 17:01 ` [PATCH 1/3] arm64: Add a capability for FEAT_BBM level 2 Colton Lewis
2023-06-05 15:07 ` Robin Murphy [this message]
2023-06-02 17:01 ` [PATCH 2/3] KVM: arm64: Clear possible conflict aborts Colton Lewis
2023-06-09 15:44 ` Oliver Upton
2023-06-02 17:01 ` [PATCH 3/3] KVM: arm64: Skip break phase when we have FEAT_BBM level 2 Colton Lewis
2023-06-04 8:23 ` Marc Zyngier
2023-06-05 21:36 ` Oliver Upton
2023-06-08 17:21 ` Will Deacon
2023-06-09 14:59 ` Oliver Upton
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