From: Matthias Brugger <matthias.bgg@gmail.com>
To: Fabien Parent <fparent@baylibre.com>, Rob Herring <robh+dt@kernel.org>
Cc: mkorpershoek@baylibre.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: mediatek: mt8167: add power domains
Date: Tue, 6 Apr 2021 12:59:55 +0200 [thread overview]
Message-ID: <7e8532e1-710c-3239-4384-cbb10348c4b4@gmail.com> (raw)
In-Reply-To: <20210405172836.2038526-1-fparent@baylibre.com>
On 05/04/2021 19:28, Fabien Parent wrote:
> Add support for the MT8167 power domains.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
Applied to v5.12-next/dts64-2
Thanks
> ---
> arch/arm64/boot/dts/mediatek/mt8167.dtsi | 68 ++++++++++++++++++++++++
> 1 file changed, 68 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> index 1c5639ead622..156fbdad01fb 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> @@ -7,6 +7,7 @@
>
> #include <dt-bindings/clock/mt8167-clk.h>
> #include <dt-bindings/memory/mt8167-larb-port.h>
> +#include <dt-bindings/power/mt8167-power.h>
>
> #include "mt8167-pinfunc.h"
>
> @@ -34,6 +35,73 @@ apmixedsys: apmixedsys@10018000 {
> #clock-cells = <1>;
> };
>
> + scpsys: syscon@10006000 {
> + compatible = "syscon", "simple-mfd";
> + reg = <0 0x10006000 0 0x1000>;
> + #power-domain-cells = <1>;
> +
> + spm: power-controller {
> + compatible = "mediatek,mt8167-power-controller";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #power-domain-cells = <1>;
> +
> + /* power domains of the SoC */
> + power-domain@MT8167_POWER_DOMAIN_MM {
> + reg = <MT8167_POWER_DOMAIN_MM>;
> + clocks = <&topckgen CLK_TOP_SMI_MM>;
> + clock-names = "mm";
> + #power-domain-cells = <0>;
> + mediatek,infracfg = <&infracfg>;
> + };
> +
> + power-domain@MT8167_POWER_DOMAIN_VDEC {
> + reg = <MT8167_POWER_DOMAIN_VDEC>;
> + clocks = <&topckgen CLK_TOP_SMI_MM>,
> + <&topckgen CLK_TOP_RG_VDEC>;
> + clock-names = "mm", "vdec";
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@MT8167_POWER_DOMAIN_ISP {
> + reg = <MT8167_POWER_DOMAIN_ISP>;
> + clocks = <&topckgen CLK_TOP_SMI_MM>;
> + clock-names = "mm";
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {
> + reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>;
> + clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
> + <&topckgen CLK_TOP_RG_SLOW_MFG>;
> + clock-names = "axi_mfg", "mfg";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #power-domain-cells = <1>;
> + mediatek,infracfg = <&infracfg>;
> +
> + power-domain@MT8167_POWER_DOMAIN_MFG_2D {
> + reg = <MT8167_POWER_DOMAIN_MFG_2D>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #power-domain-cells = <1>;
> +
> + power-domain@MT8167_POWER_DOMAIN_MFG {
> + reg = <MT8167_POWER_DOMAIN_MFG>;
> + #power-domain-cells = <0>;
> + mediatek,infracfg = <&infracfg>;
> + };
> + };
> + };
> +
> + power-domain@MT8167_POWER_DOMAIN_CONN {
> + reg = <MT8167_POWER_DOMAIN_CONN>;
> + #power-domain-cells = <0>;
> + mediatek,infracfg = <&infracfg>;
> + };
> + };
> + };
> +
> imgsys: syscon@15000000 {
> compatible = "mediatek,mt8167-imgsys", "syscon";
> reg = <0 0x15000000 0 0x1000>;
>
prev parent reply other threads:[~2021-04-06 11:00 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-05 17:28 [PATCH] arm64: dts: mediatek: mt8167: add power domains Fabien Parent
2021-04-06 10:59 ` Matthias Brugger [this message]
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