* [PATCH net-next] net: intel: Enable SERDES PHY rx clk for PSE
@ 2021-04-05 16:33 Voon Weifeng
2021-04-05 18:06 ` Wong, Vee Khee
0 siblings, 1 reply; 2+ messages in thread
From: Voon Weifeng @ 2021-04-05 16:33 UTC (permalink / raw)
To: David S . Miller, Maxime Coquelin
Cc: netdev, linux-kernel, Jose Abreu, Jakub Kicinski,
Giuseppe Cavallaro, Alexandre Torgue, linux-stm32,
linux-arm-kernel, Ong Boon Leong, Voon Weifeng, Wong Vee Khee
EHL PSE SGMII mode requires to ungate the SERDES PHY rx clk for power up
sequence and vice versa.
Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 10 ++++++++++
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
index add95e20548d..a4fec5fe0779 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
@@ -153,6 +153,11 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
return data;
}
+ /* PSE only - ungate SGMII PHY Rx Clock */
+ if (intel_priv->is_pse)
+ mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
+ 0, SERDES_PHY_RX_CLK);
+
return 0;
}
@@ -168,6 +173,11 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
serdes_phy_addr = intel_priv->mdio_adhoc_addr;
+ /* PSE only - gate SGMII PHY Rx Clock */
+ if (intel_priv->is_pse)
+ mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
+ SERDES_PHY_RX_CLK, 0);
+
/* move power state to P3 */
data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
index e723096c0b15..542acb8ce467 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
@@ -14,6 +14,7 @@
/* SERDES defines */
#define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */
+#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */
#define SERDES_RST BIT(2) /* Serdes Reset */
#define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
#define SERDES_PWR_ST_SHIFT 4
--
2.17.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* RE: [PATCH net-next] net: intel: Enable SERDES PHY rx clk for PSE
2021-04-05 16:33 [PATCH net-next] net: intel: Enable SERDES PHY rx clk for PSE Voon Weifeng
@ 2021-04-05 18:06 ` Wong, Vee Khee
0 siblings, 0 replies; 2+ messages in thread
From: Wong, Vee Khee @ 2021-04-05 18:06 UTC (permalink / raw)
To: Voon, Weifeng, David S . Miller, Maxime Coquelin
Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jose Abreu,
Jakub Kicinski, Giuseppe Cavallaro, Alexandre Torgue,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org, Ong, Boon Leong
On Tue, Apr 06, 2021 at 12:33:57AM +0800, Voon Weifeng wrote:
>
> EHL PSE SGMII mode requires to ungate the SERDES PHY rx clk for power up
> sequence and vice versa.
>
> Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
> ---
> drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 10 ++++++++++
> drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h | 1 +
> 2 files changed, 11 insertions(+)
>
Why not use "stmmac: intel" for the commit message header?
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
> b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
> index add95e20548d..a4fec5fe0779 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
> @@ -153,6 +153,11 @@ static int intel_serdes_powerup(struct net_device
> *ndev, void *priv_data)
> return data;
> }
>
> + /* PSE only - ungate SGMII PHY Rx Clock */
> + if (intel_priv->is_pse)
> + mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
> + 0, SERDES_PHY_RX_CLK);
> +
> return 0;
> }
>
> @@ -168,6 +173,11 @@ static void intel_serdes_powerdown(struct
> net_device *ndev, void *intel_data)
>
> serdes_phy_addr = intel_priv->mdio_adhoc_addr;
>
> + /* PSE only - gate SGMII PHY Rx Clock */
> + if (intel_priv->is_pse)
> + mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
> + SERDES_PHY_RX_CLK, 0);
> +
> /* move power state to P3 */
> data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
> b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
> index e723096c0b15..542acb8ce467 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
> @@ -14,6 +14,7 @@
>
> /* SERDES defines */
> #define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal
> */
> +#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */
> #define SERDES_RST BIT(2) /* Serdes Reset */
> #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power
> state*/
> #define SERDES_PWR_ST_SHIFT 4
> --
> 2.17.1
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2021-04-05 18:06 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-05 16:33 [PATCH net-next] net: intel: Enable SERDES PHY rx clk for PSE Voon Weifeng
2021-04-05 18:06 ` Wong, Vee Khee
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).