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charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Apr 18, 2024 at 10:04=E2=80=AFAM Conor Dooley wr= ote: > > On Thu, Apr 18, 2024 at 09:32:19AM -0700, Tomasz Jeznach wrote: > > Add bindings for the RISC-V IOMMU device drivers. > > > > Co-developed-by: Anup Patel > > Signed-off-by: Anup Patel > > Signed-off-by: Tomasz Jeznach > > --- > > .../bindings/iommu/riscv,iommu.yaml | 149 ++++++++++++++++++ > > MAINTAINERS | 7 + > > 2 files changed, 156 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/iommu/riscv,iommu= .yaml > > > > diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b= /Documentation/devicetree/bindings/iommu/riscv,iommu.yaml > > new file mode 100644 > > index 000000000000..d6522ddd43fa > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml > > @@ -0,0 +1,149 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: RISC-V IOMMU Architecture Implementation > > + > > +maintainers: > > + - Tomasz Jeznach > > + > > +description: |+ > > FYI, the + here is probably not needed. > > > + The RISC-V IOMMU provides memory address translation and isolation f= or > > + input and output devices, supporting per-device translation context, > > + shared process address spaces including the ATS and PRI components o= f > > + the PCIe specification, two stage address translation and MSI remapp= ing. > > + It supports identical translation table format to the RISC-V address > > + translation tables with page level access and protection attributes. > > + Hardware uses in-memory command and fault reporting queues with wire= d > > + interrupt or MSI notifications. > > + > > + Visit https://github.com/riscv-non-isa/riscv-iommu for more details. > > + > > + For information on assigning RISC-V IOMMU to its peripheral devices, > > + see generic IOMMU bindings. > > + > > +properties: > > + # For PCIe IOMMU hardware compatible property should contain the ven= dor > > + # and device ID according to the PCI Bus Binding specification. > > + # Since PCI provides built-in identification methods, compatible is = not > > + # actually required. For non-PCIe hardware implementations 'riscv,io= mmu' > > + # should be specified along with 'reg' property providing MMIO locat= ion. > > I dunno, I'd like to see soc-specific compatibles for implementations of > the RISC-V IOMMU. If you need a DT compatible for use in QEMU, I'd > suggest doing what was done for the aplic and having a dedicated > compatible for that and disallow having "riscv,iommu" in isolation. > Makes sense. Will update to something like below: compatible: oneOf: - items: - enum: - qemu,iommu - const: riscv,iommu - items: - enum: - pci1efd,edf1 - const: riscv,pci-iommu > > + compatible: > > + oneOf: > > + - items: > > + - const: riscv,pci-iommu > > + - const: pci1efd,edf1 > > + - items: > > + - const: pci1efd,edf1 > > Why are both versions allowed? If the former is more understandable, > can't we just go with that? > > > + - items: > > + - const: riscv,iommu > > Other than the compatible setup I think this is pretty decent though, > Conor. ACK to other comments, Thanks for the review, - Tomasz