From: Anup Patel <apatel@ventanamicro.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Robin Murphy <robin.murphy@arm.com>,
Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
Frank Rowand <frowand.list@gmail.com>,
Atish Patra <atishp@atishpatra.org>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, iommu@lists.linux.dev
Subject: Re: [PATCH v3 01/11] RISC-V: Add riscv_fw_parent_hartid() function
Date: Tue, 13 Jun 2023 13:35:54 +0530 [thread overview]
Message-ID: <CAK9=C2VqAX+xGH0oPhda1ygMu4umhNAXbPAQ+Z4q+fGR0R54ug@mail.gmail.com> (raw)
In-Reply-To: <20230510-squealing-pruning-2c94b85785b0@wendy>
On Wed, May 10, 2023 at 6:15 PM Conor Dooley <conor.dooley@microchip.com> wrote:
>
> On Mon, May 08, 2023 at 07:58:32PM +0530, Anup Patel wrote:
> > We add common riscv_fw_parent_hartid() which help device drivers
> > to get parent hartid of the INTC (i.e. local interrupt controller)
> > fwnode. Currently, this new function only supports device tree
> > but it can be extended to support ACPI as well.
> >
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > ---
> > arch/riscv/include/asm/processor.h | 3 +++
> > arch/riscv/kernel/cpu.c | 12 ++++++++++++
> > 2 files changed, 15 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
> > index 94a0590c6971..6fb8bbec8459 100644
> > --- a/arch/riscv/include/asm/processor.h
> > +++ b/arch/riscv/include/asm/processor.h
> > @@ -77,6 +77,9 @@ struct device_node;
> > int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid);
> > int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);
> >
> > +struct fwnode_handle;
> > +int riscv_fw_parent_hartid(struct fwnode_handle *node, unsigned long *hartid);
> > +
> > extern void riscv_fill_hwcap(void);
> > extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
> >
> > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> > index 5de6fb703cc2..1adbe48b2b58 100644
> > --- a/arch/riscv/kernel/cpu.c
> > +++ b/arch/riscv/kernel/cpu.c
> > @@ -73,6 +73,18 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
> > return -1;
> > }
> >
> > +/* Find hart ID of the CPU fwnode under which given fwnode falls. */
> > +int riscv_fw_parent_hartid(struct fwnode_handle *node, unsigned long *hartid)
> > +{
> > + /*
> > + * Currently, this function only supports DT but it can be
> > + * extended to support ACPI as well.
> > + */
>
> Statement of the obvious here, no?
> Although, it seems a little odd to read this comment & the corresponding
> statement in the commit message, when the series appears to have been
> based on the ACPI?
>
> Perhaps by the time v4 comes around, ACPI support will have been merged
> & that'll be moot.
Yes, I was anyway going to update this in v4 to support both DT and ACPI.
>
> > + if (!is_of_node(node))
> > + return -EINVAL;
> > + return riscv_of_parent_hartid(to_of_node(node), hartid);
>
> nit: blank line before the return here please.
Okay, I will update.
>
> Thanks,
> Conor.
Regards,
Anup
next prev parent reply other threads:[~2023-06-13 8:06 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-08 14:28 [PATCH v3 00/11] Linux RISC-V AIA Support Anup Patel
2023-05-08 14:28 ` [PATCH v3 01/11] RISC-V: Add riscv_fw_parent_hartid() function Anup Patel
2023-05-10 12:45 ` Conor Dooley
2023-06-13 8:05 ` Anup Patel [this message]
2023-05-08 14:28 ` [PATCH v3 02/11] of/irq: Set FWNODE_FLAG_BEST_EFFORT for the interrupt controller DT nodes Anup Patel
2023-06-08 18:28 ` Rob Herring
2023-06-08 20:04 ` Saravana Kannan
2023-06-09 11:40 ` Anup Patel
2023-06-09 21:17 ` Saravana Kannan
2023-06-13 4:42 ` Anup Patel
2023-05-08 14:28 ` [PATCH v3 03/11] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2023-05-08 14:28 ` [PATCH v3 04/11] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2023-05-10 12:16 ` Conor Dooley
2023-06-13 8:18 ` Anup Patel
2023-05-11 9:49 ` Krzysztof Kozlowski
2023-05-08 14:28 ` [PATCH v3 05/11] irqchip: Add RISC-V incoming MSI controller driver Anup Patel
2023-05-08 14:28 ` [PATCH v3 06/11] irqchip/riscv-imsic: Add support for PCI MSI irqdomain Anup Patel
2023-05-08 14:28 ` [PATCH v3 07/11] irqchip/riscv-imsic: Improve IOMMU DMA support Anup Patel
2023-05-10 10:48 ` Robin Murphy
2023-05-10 15:12 ` Anup Patel
2023-05-15 12:53 ` Jason Gunthorpe
2023-06-13 7:55 ` Anup Patel
2023-05-08 14:28 ` [PATCH v3 08/11] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2023-05-10 15:41 ` Conor Dooley
2023-06-13 10:37 ` Anup Patel
2023-05-08 14:28 ` [PATCH v3 09/11] irqchip: Add RISC-V advanced PLIC driver Anup Patel
2023-05-08 14:28 ` [PATCH v3 10/11] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2023-05-10 12:20 ` Conor Dooley
2023-05-08 14:28 ` [PATCH v3 11/11] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
2023-05-10 10:24 ` [PATCH v3 00/11] Linux RISC-V AIA Support Conor Dooley
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAK9=C2VqAX+xGH0oPhda1ygMu4umhNAXbPAQ+Z4q+fGR0R54ug@mail.gmail.com' \
--to=apatel@ventanamicro.com \
--cc=ajones@ventanamicro.com \
--cc=anup@brainfault.org \
--cc=atishp@atishpatra.org \
--cc=conor.dooley@microchip.com \
--cc=devicetree@vger.kernel.org \
--cc=frowand.list@gmail.com \
--cc=iommu@lists.linux.dev \
--cc=joro@8bytes.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=maz@kernel.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=robin.murphy@arm.com \
--cc=tglx@linutronix.de \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).