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AJvYcCUc60aqFV1rkp9vYBk9UvK6RzdeZ/JtAUdk/k7YdPkJh8TMMUKJJRFJwdzrFDUipeusLI8QGNsw218BTSq7FKIiMrCTvKsbVvNQVn+z X-Gm-Message-State: AOJu0Yzu3bbNjYvoK1rE4eFC2A7cBpJVhyKnsHR2dZYsdyAMRaOMuoQY fL6HKsXj13ZlztevPeMF2hggvTjvPfn+ZsDdPVVARepxyV02n54kKMWnaCxRbpVuoSHzyEsdO8d jt4gRfOmNzNvJzi0Ea0+l5YMxsPWwSHqVR+Kn X-Google-Smtp-Source: AGHT+IFie6kWXAuIKFD19BDQmEVuYkXyygSoVtc7g5k6fJ83evlUpB/kUdYyYkH1hFW80mrYrAAbpNBPLDkRavi0P4E= X-Received: by 2002:a05:6402:2917:b0:56f:ce8d:8f9 with SMTP id ee23-20020a056402291700b0056fce8d08f9mr24010edb.3.1712876943905; Thu, 11 Apr 2024 16:09:03 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> <20240126085444.324918-29-xiong.y.zhang@linux.intel.com> In-Reply-To: From: Jim Mattson Date: Thu, 11 Apr 2024 16:08:48 -0700 Message-ID: Subject: Re: [RFC PATCH 28/41] KVM: x86/pmu: Switch IA32_PERF_GLOBAL_CTRL at VM boundary To: Sean Christopherson Cc: Xiong Zhang , pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, Xiong Zhang Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Apr 11, 2024 at 3:54=E2=80=AFPM Sean Christopherson wrote: > > On Thu, Apr 11, 2024, Jim Mattson wrote: > > On Thu, Apr 11, 2024 at 2:54=E2=80=AFPM Sean Christopherson wrote: > > > > > > On Fri, Jan 26, 2024, Xiong Zhang wrote: > > > > +static void save_perf_global_ctrl_in_passthrough_pmu(struct vcpu_v= mx *vmx) > > > > +{ > > > > + struct kvm_pmu *pmu =3D vcpu_to_pmu(&vmx->vcpu); > > > > + int i; > > > > + > > > > + if (vm_exit_controls_get(vmx) & VM_EXIT_SAVE_IA32_PERF_GLOBAL= _CTRL) { > > > > + pmu->global_ctrl =3D vmcs_read64(GUEST_IA32_PERF_GLOB= AL_CTRL); > > > > + } else { > > > > + i =3D vmx_find_loadstore_msr_slot(&vmx->msr_autostore= .guest, > > > > + MSR_CORE_PERF_GLOBAL_= CTRL); > > > > + if (i < 0) > > > > + return; > > > > + pmu->global_ctrl =3D vmx->msr_autostore.guest.val[i].= value; > > > > > > As before, NAK to using the MSR load/store lists unless there's a *re= ally* good > > > reason I'm missing. > > > > The VM-exit control, "save IA32_PERF_GLOBAL_CTL," first appears in > > Sapphire Rapids. I think that's a compelling reason. > > Well that's annoying. When was PMU v4 introduced? E.g. if it came in IC= X, I'd > be sorely tempted to make VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL a hard requi= rement. Broadwell was v3. Skylake was v4. > And has someone confirmed that the CPU saves into the MSR store list befo= re > processing VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL? It's at the top of chapter 28 in volume 3 of the SDM. MSRs may be saved in the VM-exit MSR-store area before processor state is loaded based in part on the host-state area and some VM-exit controls. Anything else would be stupid. (Yes, I know that this is CPU design we're talking about!)