From: Evan Green <evan@rivosinc.com>
To: Charlie Jenkins <charlie@rivosinc.com>
Cc: "Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
"Palmer Dabbelt" <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v4 13/16] riscv: hwprobe: Add thead vendor extension probing
Date: Wed, 1 May 2024 09:46:00 -0700 [thread overview]
Message-ID: <CALs-HsuPXhc93jqs==-Gq5Os701jxmzjxg82EHdOFHn+H-9Jdg@mail.gmail.com> (raw)
In-Reply-To: <20240426-dev-charlie-support_thead_vector_6_9-v4-13-5cf53b5bc492@rivosinc.com>
On Fri, Apr 26, 2024 at 2:37 PM Charlie Jenkins <charlie@rivosinc.com> wrote:
>
> Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which
> allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR
> vendor extension.
>
> This new key will allow userspace code to probe for which thead vendor
> extensions are supported. This API is modeled to be consistent with
> RISCV_HWPROBE_KEY_IMA_EXT_0. The bitmask returned will have each bit
> corresponding to a supported thead vendor extension of the cpumask set.
> Just like RISCV_HWPROBE_KEY_IMA_EXT_0, this allows a userspace program
> to determine all of the supported thead vendor extensions in one call.
>
> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> ---
> arch/riscv/include/asm/hwprobe.h | 4 +--
> .../include/asm/vendor_extensions/thead_hwprobe.h | 11 ++++++
> arch/riscv/include/uapi/asm/hwprobe.h | 3 +-
> arch/riscv/include/uapi/asm/vendor/thead.h | 3 ++
> arch/riscv/kernel/sys_hwprobe.c | 9 +++++
> arch/riscv/kernel/vendor_extensions/Makefile | 1 +
> .../riscv/kernel/vendor_extensions/thead_hwprobe.c | 42 ++++++++++++++++++++++
> 7 files changed, 70 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
> index 630507dff5ea..e68496b4f8de 100644
> --- a/arch/riscv/include/asm/hwprobe.h
> +++ b/arch/riscv/include/asm/hwprobe.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
> /*
> - * Copyright 2023 Rivos, Inc
> + * Copyright 2023-2024 Rivos, Inc
> */
>
> #ifndef _ASM_HWPROBE_H
> @@ -8,7 +8,7 @@
>
> #include <uapi/asm/hwprobe.h>
>
> -#define RISCV_HWPROBE_MAX_KEY 6
> +#define RISCV_HWPROBE_MAX_KEY 7
>
> static inline bool riscv_hwprobe_key_is_valid(__s64 key)
> {
> diff --git a/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h b/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h
> new file mode 100644
> index 000000000000..907cfc4eb4dc
> --- /dev/null
> +++ b/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H
> +#define _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H
> +
> +#include <linux/cpumask.h>
> +
> +#include <uapi/asm/hwprobe.h>
> +
> +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus);
> +
> +#endif
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 9f2a8e3ff204..21e96a63f9ea 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
> /*
> - * Copyright 2023 Rivos, Inc
> + * Copyright 2023-2024 Rivos, Inc
> */
>
> #ifndef _UAPI_ASM_HWPROBE_H
> @@ -67,6 +67,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
> #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
> #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
> +#define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 7
> /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
>
> /* Flags */
> diff --git a/arch/riscv/include/uapi/asm/vendor/thead.h b/arch/riscv/include/uapi/asm/vendor/thead.h
> new file mode 100644
> index 000000000000..43790ebe5faf
> --- /dev/null
> +++ b/arch/riscv/include/uapi/asm/vendor/thead.h
> @@ -0,0 +1,3 @@
> +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
> +
> +#define RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR (1 << 0)
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index 8cae41a502dd..e59cac545df5 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -13,6 +13,7 @@
> #include <asm/uaccess.h>
> #include <asm/unistd.h>
> #include <asm/vector.h>
> +#include <asm/vendor_extensions/thead_hwprobe.h>
> #include <vdso/vsyscall.h>
>
>
> @@ -216,6 +217,14 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
> pair->value = riscv_cboz_block_size;
> break;
>
> + case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
> +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD
> + hwprobe_isa_vendor_ext_thead_0(pair, cpus);
> +#else
> + pair->value = 0;
> +#endif
Could we move this ifdef into the header by declaring a dummy
hwprobe_isa_vendor_ext_thead_0() in the header for the !ENABLED case?
> + break;
> +
> /*
> * For forward compatibility, unknown keys don't fail the whole
> * call, but get their element key set to -1 and value set to 0
> diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile
> index 8f1c5a4dc38f..f511fd269e8a 100644
> --- a/arch/riscv/kernel/vendor_extensions/Makefile
> +++ b/arch/riscv/kernel/vendor_extensions/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0-only
>
> obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead.o
> +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead_hwprobe.o
> obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) += andes.o
> diff --git a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c
> new file mode 100644
> index 000000000000..e8e2de292032
> --- /dev/null
> +++ b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c
> @@ -0,0 +1,42 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +#include <asm/vector.h>
> +#include <asm/vendor_extensions/thead.h>
> +#include <asm/vendor_extensions/thead_hwprobe.h>
> +
> +#include <linux/cpumask.h>
> +#include <linux/types.h>
> +
> +#include <uapi/asm/hwprobe.h>
> +#include <uapi/asm/vendor/thead.h>
> +
> +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus)
> +{
> + /*
> + * Loop through and record extensions that 1) anyone has, and 2) anyone
> + * doesn't have.
> + */
> +
> + struct riscv_isainfo *per_hart_thead_bitmap = riscv_isa_vendor_ext_list_thead.per_hart_vendor_bitmap;
> + int cpu;
> + u64 missing;
> +
> + for_each_cpu(cpu, cpus) {
> + struct riscv_isainfo *isainfo = &per_hart_thead_bitmap[cpu];
> +
> +#define EXT_KEY(ext) \
> + do { \
> + if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_VENDOR_EXT_##ext)) \
> + pair->value |= RISCV_HWPROBE_VENDOR_EXT_##ext; \
> + else \
> + missing |= RISCV_HWPROBE_VENDOR_EXT_##ext; \
> + } while (false)
> +
> + EXT_KEY(XTHEADVECTOR);
> +
> +#undef EXT_KEY
> + }
> +
> + /* Now turn off reporting features if any CPU is missing it. */> + pair->value &= ~missing;
> +}
Something to consider, perhaps when there's a second vendor, is how we
might reduce this boilerplate on the second vendor. Probably best to
wait though until we know exactly what the commonalities are. This
looks good for now.
>
> --
> 2.44.0
>
next prev parent reply other threads:[~2024-05-01 16:46 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20240426-dev-charlie-support_thead_vector_6_9-v4-0-5cf53b5bc492@rivosinc.com>
2024-04-26 21:37 ` [PATCH v4 09/16] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-04-26 21:37 ` [PATCH v4 10/16] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT Charlie Jenkins
2024-04-26 21:37 ` [PATCH v4 11/16] riscv: Add xtheadvector instruction definitions Charlie Jenkins
2024-04-26 21:37 ` [PATCH v4 12/16] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-04-26 21:37 ` [PATCH v4 13/16] riscv: hwprobe: Add thead vendor extension probing Charlie Jenkins
2024-05-01 16:46 ` Evan Green [this message]
2024-05-01 19:31 ` Charlie Jenkins
2024-05-01 19:50 ` Charlie Jenkins
2024-04-26 21:37 ` [PATCH v4 14/16] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Charlie Jenkins
2024-04-26 21:37 ` [PATCH v4 15/16] selftests: riscv: Fix vector tests Charlie Jenkins
2024-04-26 21:37 ` [PATCH v4 16/16] selftests: riscv: Support xtheadvector in " Charlie Jenkins
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