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AJvYcCVFl9Z2Vw7QBIg6g+FC7kCrl3wlaRAgbfyPFyDJzzN6JEWJUMWPEnOlwHE7RLrGFkwZK+s9X/Y+IJvxHUD6KgybSAxSzh5D/2OEFgzH X-Gm-Message-State: AOJu0Yzt82IEgaPY8M5pLdCUiVNXauap1SDoE/kemry0N0L6racygce8 XAAqK8NHEtEC5SY8RthVKec9Z+jzwbABPU9/EXDWgSmndNYfg2YWTaXKSMdN0xEI/7epp95eKAs djQ== X-Google-Smtp-Source: AGHT+IHPgtVqy0nFz025gGkTnMo7Alsvac05GAyUWXxa4k7Ytx/BHJCnyE1o2+n0hRWW+1ji8QfCIZN6pMU= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:90a:fb94:b0:2a5:2428:2253 with SMTP id cp20-20020a17090afb9400b002a524282253mr1232pjb.8.1712863291990; Thu, 11 Apr 2024 12:21:31 -0700 (PDT) Date: Thu, 11 Apr 2024 12:21:30 -0700 In-Reply-To: <20240126085444.324918-8-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> <20240126085444.324918-8-xiong.y.zhang@linux.intel.com> Message-ID: Subject: Re: [RFC PATCH 07/41] perf/x86: Add interface to reflect virtual LVTPC_MASK bit onto HW From: Sean Christopherson To: Xiong Zhang Cc: pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, Xiong Zhang Content-Type: text/plain; charset="us-ascii" On Fri, Jan 26, 2024, Xiong Zhang wrote: > From: Xiong Zhang > > When guest clear LVTPC_MASK bit in guest PMI handler at PMU passthrough > mode, this bit should be reflected onto HW, otherwise HW couldn't generate > PMI again during VM running until it is cleared. This fixes a bug in the previous patch, i.e. this should not be a standalone patch. > > This commit set HW LVTPC_MASK bit at PMU vecctor switching to KVM PMI > vector. > > Signed-off-by: Xiong Zhang > Signed-off-by: Mingwei Zhang > --- > arch/x86/events/core.c | 9 +++++++-- > arch/x86/include/asm/perf_event.h | 2 +- > arch/x86/kvm/lapic.h | 1 - > 3 files changed, 8 insertions(+), 4 deletions(-) > > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c > index 3f87894d8c8e..ece042cfb470 100644 > --- a/arch/x86/events/core.c > +++ b/arch/x86/events/core.c > @@ -709,13 +709,18 @@ void perf_guest_switch_to_host_pmi_vector(void) > } > EXPORT_SYMBOL_GPL(perf_guest_switch_to_host_pmi_vector); > > -void perf_guest_switch_to_kvm_pmi_vector(void) > +void perf_guest_switch_to_kvm_pmi_vector(bool mask) > { > lockdep_assert_irqs_disabled(); > > - apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_VPMU_VECTOR); > + if (mask) > + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_VPMU_VECTOR | > + APIC_LVT_MASKED); > + else > + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_VPMU_VECTOR); > } Or more simply: void perf_guest_enter(u32 guest_lvtpc) { ... apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_VPMU_VECTOR | (guest_lvtpc & APIC_LVT_MASKED)); } and then on the KVM side: perf_guest_enter(kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVTPC)); because an in-kernel APIC should be a hard requirement for the mediated PMU.