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AJvYcCVZHVDmARDfAHlnZezoAYwDDd/UrphoqOsurTBWBco+WpOaZVruJt+KyHRZJkYTwbeNfDQJ7CJC7H9y51pYVmam5eXqr/2FxsWfz0yo X-Gm-Message-State: AOJu0YxDkd/0cBjEbaRPsOumeR2p/AMmNVDXH8irjYeiv0497Fq6mNdQ vQDSriKZNu7kEZiF93NSBcGMe3ggSW+9cgWK5RrNpfsqNApdD8T3fI6+q9VkMr/CtkDDL3NQ6Bg olw== X-Google-Smtp-Source: AGHT+IGZ+qny5vsAryEUnYuYWfWFnPNMFNS3iikjoJhbHBN2jn6aXOOhLAyFbwTh2/A/B+k9D+DvbhyoZDs= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:902:f68c:b0:1e3:cf18:7472 with SMTP id l12-20020a170902f68c00b001e3cf187472mr1091plg.9.1712864053929; Thu, 11 Apr 2024 12:34:13 -0700 (PDT) Date: Thu, 11 Apr 2024 12:34:12 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> <20240126085444.324918-7-xiong.y.zhang@linux.intel.com> Message-ID: Subject: Re: [RFC PATCH 06/41] perf: x86: Add function to switch PMI handler From: Sean Christopherson To: Xiong Zhang Cc: pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, Xiong Zhang Content-Type: text/plain; charset="us-ascii" On Thu, Apr 11, 2024, Sean Christopherson wrote: > On Fri, Jan 26, 2024, Xiong Zhang wrote: > > From: Xiong Zhang > > > > Add function to switch PMI handler since passthrough PMU and host PMU will > > use different interrupt vectors. > > > > Signed-off-by: Xiong Zhang > > Signed-off-by: Mingwei Zhang > > --- > > arch/x86/events/core.c | 15 +++++++++++++++ > > arch/x86/include/asm/perf_event.h | 3 +++ > > 2 files changed, 18 insertions(+) > > > > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c > > index 40ad1425ffa2..3f87894d8c8e 100644 > > --- a/arch/x86/events/core.c > > +++ b/arch/x86/events/core.c > > @@ -701,6 +701,21 @@ struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data) > > } > > EXPORT_SYMBOL_GPL(perf_guest_get_msrs); > > > > +void perf_guest_switch_to_host_pmi_vector(void) > > +{ > > + lockdep_assert_irqs_disabled(); > > + > > + apic_write(APIC_LVTPC, APIC_DM_NMI); > > +} > > +EXPORT_SYMBOL_GPL(perf_guest_switch_to_host_pmi_vector); > > + > > +void perf_guest_switch_to_kvm_pmi_vector(void) > > +{ > > + lockdep_assert_irqs_disabled(); > > + > > + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_VPMU_VECTOR); > > +} > > +EXPORT_SYMBOL_GPL(perf_guest_switch_to_kvm_pmi_vector); > > Why slice and dice the context switch if it's all in perf? Just do this in > perf_guest_enter(). Ah, because perf_guest_enter() isn't x86-specific. That can be solved by having the exported APIs be arch specific, e.g. x86_perf_guest_enter(), and making perf_guest_enter() a perf-internal API. That has the advantage of making it impossible to call perf_guest_enter() on an unsupported architecture (modulo perf bugs).