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AJvYcCUJOGEwoZjZLFRsFCYDCqTv6ECBDB4nAuPnxVd1jAzK+uK7khWwqdrvYaaUQbcNPj55hyVolUNQsbtJHfNJxs+6+gw/zqygvbNcQBe+ X-Gm-Message-State: AOJu0YyrIr/Ad9L93vf0zT7VpjOe5EjtuSMO1dXGO4EeNPQb3rFRg/A3 bYcz6UVKHU+Nm1R1QtpF5fmoLEz9aeyvLxelqCvXY83yBr6AJEhmJ+BQTcqD3fDsSHSaLwSRwof eLQ== X-Google-Smtp-Source: AGHT+IH9dyBjwYQ6qyY0Soi/iKEoDhgE0NmUsd3HLY8ONMNaCYYAfiPmG+fuJNw1ZCLcK+rYaU6AuAjCHHs= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6902:c0c:b0:de1:d49:7ff6 with SMTP id fs12-20020a0569020c0c00b00de10d497ff6mr95831ybb.7.1712872560644; Thu, 11 Apr 2024 14:56:00 -0700 (PDT) Date: Thu, 11 Apr 2024 14:55:59 -0700 In-Reply-To: <20240126085444.324918-35-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> <20240126085444.324918-35-xiong.y.zhang@linux.intel.com> Message-ID: Subject: Re: [RFC PATCH 34/41] KVM: x86/pmu: Intercept EVENT_SELECT MSR From: Sean Christopherson To: Xiong Zhang Cc: pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, Xiong Zhang Content-Type: text/plain; charset="us-ascii" On Fri, Jan 26, 2024, Xiong Zhang wrote: > From: Xiong Zhang > > Event selectors for GP counters are still intercepted for the purpose of > security, i.e., preventing guest from using unallowed events to steal > information or take advantages of any CPU errata. Heh, so then they shouldn't have been passed through in the first place. > Signed-off-by: Xiong Zhang > Signed-off-by: Mingwei Zhang > --- > arch/x86/kvm/vmx/pmu_intel.c | 1 - > arch/x86/kvm/vmx/vmx.c | 1 - > 2 files changed, 2 deletions(-) > > diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c > index 9bbd5084a766..621922005184 100644 > --- a/arch/x86/kvm/vmx/pmu_intel.c > +++ b/arch/x86/kvm/vmx/pmu_intel.c > @@ -809,7 +809,6 @@ void intel_passthrough_pmu_msrs(struct kvm_vcpu *vcpu) > int i; > > for (i = 0; i < vcpu_to_pmu(vcpu)->nr_arch_gp_counters; i++) { > - vmx_set_intercept_for_msr(vcpu, MSR_ARCH_PERFMON_EVENTSEL0 + i, MSR_TYPE_RW, false); > vmx_set_intercept_for_msr(vcpu, MSR_IA32_PERFCTR0 + i, MSR_TYPE_RW, false); > if (fw_writes_is_enabled(vcpu)) > vmx_set_intercept_for_msr(vcpu, MSR_IA32_PMC0 + i, MSR_TYPE_RW, false); > diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c > index d28afa87be70..1a518800d154 100644 > --- a/arch/x86/kvm/vmx/vmx.c > +++ b/arch/x86/kvm/vmx/vmx.c > @@ -698,7 +698,6 @@ static bool is_valid_passthrough_msr(u32 msr) > case MSR_LBR_CORE_FROM ... MSR_LBR_CORE_FROM + 8: > case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8: > /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */ > - case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 7: > case MSR_IA32_PMC0 ... MSR_IA32_PMC0 + 7: > case MSR_IA32_PERFCTR0 ... MSR_IA32_PERFCTR0 + 7: > case MSR_CORE_PERF_FIXED_CTR_CTRL: > -- > 2.34.1 >