From: Frank Li <Frank.li@nxp.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: "Richard Zhu" <hongxing.zhu@nxp.com>,
"Lucas Stach" <l.stach@pengutronix.de>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Shawn Guo" <shawnguo@kernel.org>,
"Sascha Hauer" <s.hauer@pengutronix.de>,
"Pengutronix Kernel Team" <kernel@pengutronix.de>,
"Fabio Estevam" <festevam@gmail.com>,
"NXP Linux Team" <linux-imx@nxp.com>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Liam Girdwood" <lgirdwood@gmail.com>,
"Mark Brown" <broonie@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Conor Dooley" <conor+dt@kernel.org>,
linux-pci@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, bpf@vger.kernel.org,
devicetree@vger.kernel.org, "Jason Liu" <jason.hui.liu@nxp.com>
Subject: Re: [PATCH v3 02/11] PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI
Date: Mon, 29 Apr 2024 11:58:28 -0400 [thread overview]
Message-ID: <Zi/DpIhGN3lAZhG0@lizhi-Precision-Tower-5810> (raw)
In-Reply-To: <20240427092303.GG1981@thinkpad>
On Sat, Apr 27, 2024 at 02:53:03PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Apr 02, 2024 at 10:33:38AM -0400, Frank Li wrote:
> > From: Richard Zhu <hongxing.zhu@nxp.com>
> >
> > Fix i.MX8MP PCIe EP can't trigger MSI issue.
> > There is one 64Kbytes minimal requirement on i.MX8M PCIe outbound
> > region configuration.
> >
> > EP uses Bar0 to set the outboud region to configure the MSI setting.
>
> I don't understand this statement. How EP can use BAR0 for MSI? MSIs are
> triggered using outbound window memory while BARs are mapped as inbound.
>
> - Mani
Let's rewrite commit message.
PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI
i.MX8MP PCIe EP requires 64KB alignment. MSI triggering may fail if the
outbound MSI memory region (ep->msi_mem) is not aligned to 64KB.
In dw_pcie_ep_init():
ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
epc->mem->window.page_size);
Set ep->page_size to match drvdata::epc_features::align since different
SOCs have different alignment requirements.
Frank
>
> > Set the page_size to "epc_features->align" to meet the requirement,
> > let the MSI can be triggered successfully.
> >
> > Fixes: 1bd0d43dcf3b ("PCI: imx6: Clean up addr_space retrieval code")
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Acked-by: Jason Liu <jason.hui.liu@nxp.com>
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > drivers/pci/controller/dwc/pci-imx6.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> > index e43eda6b33ca7..6c4d25b92225e 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -1118,6 +1118,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
> > if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT))
> > dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
> >
> > + ep->page_size = imx6_pcie->drvdata->epc_features->align;
> > +
> > ret = dw_pcie_ep_init(ep);
> > if (ret) {
> > dev_err(dev, "failed to initialize endpoint\n");
> >
> > --
> > 2.34.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2024-04-29 15:58 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-02 14:33 [PATCH v3 00/11] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li
2024-04-02 14:33 ` [PATCH v3 01/11] PCI: imx6: Fix PCIe link down when i.MX8MM and i.MX8MP PCIe is EP mode Frank Li
2024-04-27 9:00 ` Manivannan Sadhasivam
2024-04-29 14:53 ` Frank Li
2024-04-02 14:33 ` [PATCH v3 02/11] PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI Frank Li
2024-04-27 9:23 ` Manivannan Sadhasivam
2024-04-29 15:58 ` Frank Li [this message]
2024-04-02 14:33 ` [PATCH v3 03/11] PCI: imx6: Rename imx6_* with imx_* Frank Li
2024-04-27 9:29 ` Manivannan Sadhasivam
2024-04-02 14:33 ` [PATCH v3 04/11] PCI: imx6: Rename pci-imx6.c to pcie-imx.c Frank Li
2024-04-27 9:31 ` Manivannan Sadhasivam
2024-04-29 16:01 ` Frank Li
2024-04-02 14:33 ` [PATCH v3 05/11] MAINTAINERS: pci: imx: update imx6* to imx* since rename driver file Frank Li
2024-04-27 9:33 ` Manivannan Sadhasivam
2024-04-29 15:03 ` Rob Herring
2024-04-02 14:33 ` [PATCH v3 06/11] PCI: imx: Simplify switch-case logic by involve set_ref_clk callback Frank Li
2024-04-27 9:54 ` Manivannan Sadhasivam
2024-04-02 14:33 ` [PATCH v3 07/11] PCI: imx: Simplify switch-case logic by involve core_reset callback Frank Li
2024-04-27 10:19 ` Manivannan Sadhasivam
2024-04-29 16:38 ` Frank Li
2024-04-02 14:33 ` [PATCH v3 08/11] PCI: imx: Config look up table(LUT) to support MSI ITS and IOMMU for i.MX95 Frank Li
2024-04-27 11:36 ` Manivannan Sadhasivam
2024-04-29 15:06 ` Rob Herring
2024-04-29 17:00 ` Frank Li
2024-04-29 15:08 ` Rob Herring
2024-04-02 14:33 ` [PATCH v3 09/11] PCI: imx: Consolidate redundant if-checks Frank Li
2024-04-27 11:38 ` Manivannan Sadhasivam
2024-04-02 14:33 ` [PATCH v3 10/11] dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string Frank Li
2024-04-29 15:48 ` Rob Herring
2024-04-29 21:23 ` Frank Li
2024-05-07 14:55 ` Rob Herring
2024-04-02 14:33 ` [PATCH v3 11/11] PCI: imx6: Add i.MX8Q PCIe support Frank Li
2024-04-27 11:47 ` Manivannan Sadhasivam
2024-04-29 17:56 ` Frank Li
2024-04-16 14:07 ` [PATCH v3 00/11] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li
2024-04-25 11:12 ` Manivannan Sadhasivam
2024-04-23 14:23 ` Frank Li
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