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Tue, 6 Jun 2023 17:09:22 GMT Received: from akhilpo-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 6 Jun 2023 10:09:16 -0700 Date: Tue, 6 Jun 2023 22:39:13 +0530 From: Akhil P Oommen To: Konrad Dybcio CC: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Conor Dooley , , , , , , Rob Clark , Marijn Suijten Subject: Re: [PATCH v8 06/18] drm/msm/a6xx: Improve a6xx_bus_clear_pending_transactions() Message-ID: References: <20230223-topic-gmuwrapper-v8-0-69c68206609e@linaro.org> <20230223-topic-gmuwrapper-v8-6-69c68206609e@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20230223-topic-gmuwrapper-v8-6-69c68206609e@linaro.org> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: DHc7Ixj7KM7S8vUVBI1mq2BpPrhNNbXE X-Proofpoint-GUID: DHc7Ixj7KM7S8vUVBI1mq2BpPrhNNbXE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-06_12,2023-06-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 adultscore=0 clxscore=1015 impostorscore=0 spamscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=958 bulkscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2306060148 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, May 29, 2023 at 03:52:25PM +0200, Konrad Dybcio wrote: > > Unify the indentation and explain the cryptic 0xF value. > > Signed-off-by: Konrad Dybcio Reviewed-by: Akhil P Oommen -Akhil > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 6bb4da70f6a6..e3ac3f045665 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1597,17 +1597,18 @@ static void a6xx_llc_slices_init(struct platform_device *pdev, > a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL); > } > > -#define GBIF_CLIENT_HALT_MASK BIT(0) > -#define GBIF_ARB_HALT_MASK BIT(1) > +#define GBIF_CLIENT_HALT_MASK BIT(0) > +#define GBIF_ARB_HALT_MASK BIT(1) > +#define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) > > void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off) > { > struct msm_gpu *gpu = &adreno_gpu->base; > > if (!a6xx_has_gbif(adreno_gpu)) { > - gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf); > + gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, VBIF_XIN_HALT_CTRL0_MASK); > spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & > - 0xf) == 0xf); > + (VBIF_XIN_HALT_CTRL0_MASK)) == VBIF_XIN_HALT_CTRL0_MASK); > gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); > > return; > > -- > 2.40.1 >