* [PATCH v6 00/13] LoongArch: Better backtraces
@ 2023-04-22 17:34 WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 01/13] LoongArch: Clean up the architectural interrupt definitions WANG Xuerui
` (12 more replies)
0 siblings, 13 replies; 16+ messages in thread
From: WANG Xuerui @ 2023-04-22 17:34 UTC (permalink / raw
To: Huacai Chen; +Cc: loongarch, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Hi,
Here are a bunch of tweaks to the backtrace code, so the Quality of Life
for unfortunate LoongArch kernel devs (including but not limited to,
myself) could be marginally improved by relieving them of having to
mentally decode the register names and CSR bitfields.
Before:
> [ 17.879976] $ 0 : 0000000000000000 9000000000cc980c 90000001002cc000 90000001002cfe30
> [ 17.887936] $ 4 : 0000000000000010 9000000000f1f770 90000001002cc000 9000000000cc3468
> [ 17.895895] $ 8 : 900000010028fd00 0000000000000001 000055558e569190 0000000000000004
> [ 17.903853] $12 : 0000000000000000 0000000000000004 9000000001026000 900000000132b2d8
> [ 17.911811] $16 : 9000000001026000 000000006674b539 9000000000d51d10 0000000000000001
> [ 17.919769] $20 : 0000000000000000 900000000025c27c 0000000000000004 0000000000000002
> [ 17.927727] $24 : 900000000102e5b0 900000000102e508 0000000000000000 0000000000000004
> [ 17.935686] $28 : 9000000009007840 0000000000000004 0000000000000000 0000000000000004
> [ 17.943644] era : 90000000002215a0 __arch_cpu_idle+0x20/0x24
> [ 17.949438] ra : 9000000000cc980c default_idle_call+0x34/0x5c
> [ 17.955406] CSR crmd: 000000b0
> [ 17.955408] CSR prmd: 00000004
> [ 17.958521] CSR euen: 00000000
> [ 17.961635] CSR ecfg: 00071c1c
> [ 17.964748] CSR estat: 00001000
> [ 17.971062] ExcCode : 0 (SubCode 0)
> [ 17.974522] PrId : 0014c010 (Loongson-64bit)
After:
> [ 34.320373] pc 9000000001691640 ra 90000000021e8e30 tp 90000000025d4000 sp 90000000025d7db0
> [ 34.328673] a0 0000000000000000 a1 90000000024cee38 a2 0000000000000001 a3 7fffffffffffffff
> [ 34.336972] a4 0000000000000002 a5 90000000023316a8 a6 0000000000000001 a7 0000000000000004
> [ 34.345271] t0 0000000000000000 t1 0000000000000001 t2 0000000000000001 t3 90000000025ee550
> [ 34.353570] t4 ffffffffffffffff t5 00000000cc620ce7 t6 0000000000000000 t7 0000000000000041
> [ 34.361869] t8 0000000000001492 u0 0000000000000001 s9 9000000002510340 s0 0000000000000004
> [ 34.370167] s1 90000000025ee5d0 s2 90000000025ee528 s3 0000000000000000 s4 0000000000000004
> [ 34.378466] s5 9000000000571880 s6 90000000005718b2 s7 0000000000000000 s8 9000000002510340
> [ 34.386765] ra: 90000000021e8e30 arch_cpu_idle+0x1c/0x34
> [ 34.392309] ERA: 9000000001691640 __arch_cpu_idle+0x20/0x24
> [ 34.398018] CRMD: 000000b0 (PLV0 -IE -DA +PG DACF=CC DACM=CC -WE)
> [ 34.404169] PRMD: 00000004 (PPLV0 +PIE -PWE)
> [ 34.408498] EUEN: 00000000 (-FPE -SXE -ASXE -BTE)
> [ 34.413259] ECFG: 00071c1d (LIE=0,2-4,10-12 VS=7)
> [ 34.418021] ESTAT: 00000004 [INT] (IS=2 ECode=0 EsubCode=0)
> [ 34.423471] PRID: 0014c010 (Loongson-64bit, Loongson-3A5000)
I've been told privately that the quirk I discovered in patch 12
(concerning BCE and CSR.BADV) may actually be expected, in which case
the patch wouldn't be needed at all. (Huacai: please feel free to drop
that patch when applying if this turns out to be the case.)
Changes in v6:
- show PC/ERA in place of $zero
- swap the symbolized $ra and ERA lines to make all CSRs appear together
- humanize all CSR fields from LSB to MSB
- show the CPU model name along with the family name
Changes in v5:
- rebased on top of current loongarch-next
- reverted to 4x8 layout for the GPRs
- show $ra twice (once in the GPRs, once below with symbol info) for
prettier grid
- use upper-case field names where applicable
Changes in v4:
- rebased on top of current loongarch-next
- show CSR.BADV in case of BCE too
Changes in v3:
- rebased and tested on top of v6.2-rc8
- restored the "era" name for PC per review suggestion
- show "u0" in case of r21 according to kernel register convention
- removed redundant print of $ra
- print the syscall restart flag if non-zero
Changes in v2:
- rebased and tested on top of next-20221226
- removed the mass symbol renamings per Huacai's suggestion (but the
output still uses the ISA manual names because users are expected to
be more familiar with those)
WANG Xuerui (13):
LoongArch: Clean up the architectural interrupt definitions
LoongArch: Add exception subcode definitions for the watchpoint
exception
LoongArch: Print GPRs with ABI names when showing registers
LoongArch: Print symbol info for CSR.ERA and $ra only for kernel-mode
contexts
LoongArch: Fix format of CSR lines during show_regs
LoongArch: Humanize the CRMD line when showing registers
LoongArch: Humanize the PRMD line when showing registers
LoongArch: Humanize the EUEN line when showing registers
LoongArch: Humanize the ECFG line when showing registers
LoongArch: Humanize the ESTAT line when showing registers
LoongArch: Use ISA manual names for BADV and CPUCFG.PRID lines in
show_regs
LoongArch: Include CSR.BADV in show_regs in case of BCE exceptions
LoongArch: Also include current CPU's full name in show_regs output
arch/loongarch/include/asm/loongarch.h | 51 +++---
arch/loongarch/kernel/irq.c | 2 +-
arch/loongarch/kernel/perf_event.c | 2 +-
arch/loongarch/kernel/time.c | 2 +-
arch/loongarch/kernel/traps.c | 225 +++++++++++++++++++++----
5 files changed, 221 insertions(+), 61 deletions(-)
--
2.40.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 01/13] LoongArch: Clean up the architectural interrupt definitions
2023-04-22 17:34 [PATCH v6 00/13] LoongArch: Better backtraces WANG Xuerui
@ 2023-04-22 17:34 ` WANG Xuerui
2023-04-25 7:32 ` Huacai Chen
2023-04-22 17:34 ` [PATCH v6 02/13] LoongArch: Add exception subcode definitions for the watchpoint exception WANG Xuerui
` (11 subsequent siblings)
12 siblings, 1 reply; 16+ messages in thread
From: WANG Xuerui @ 2023-04-22 17:34 UTC (permalink / raw
To: Huacai Chen; +Cc: loongarch, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
While interrupts are assigned ECodes `64 + interrupt number`, all
existing use sites of interrupt numbers want the 64 subtracted.
Re-arrange the definitions so that the actual interrupt number is used
everywhere, and make EXCCODE_INT_END inclusive as it is more intuitive
that way.
While at it, according to the asm/loongarch.h definitions, the total
number of architectural interrupts should be 14 instead of 13. Relevant
bitfields and masks have been adjusted as well.
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
arch/loongarch/include/asm/loongarch.h | 47 ++++++++++++++------------
arch/loongarch/kernel/irq.c | 2 +-
arch/loongarch/kernel/perf_event.c | 2 +-
arch/loongarch/kernel/time.c | 2 +-
arch/loongarch/kernel/traps.c | 2 +-
5 files changed, 29 insertions(+), 26 deletions(-)
diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index 83da5d29e2d1..7d8b83dd32e9 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -311,8 +311,8 @@ static __always_inline void iocsr_write64(u64 val, u32 reg)
#define CSR_ECFG_VS_WIDTH 3
#define CSR_ECFG_VS (_ULCAST_(0x7) << CSR_ECFG_VS_SHIFT)
#define CSR_ECFG_IM_SHIFT 0
-#define CSR_ECFG_IM_WIDTH 13
-#define CSR_ECFG_IM (_ULCAST_(0x1fff) << CSR_ECFG_IM_SHIFT)
+#define CSR_ECFG_IM_WIDTH 14
+#define CSR_ECFG_IM (_ULCAST_(0x3fff) << CSR_ECFG_IM_SHIFT)
#define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */
#define CSR_ESTAT_ESUBCODE_SHIFT 22
@@ -322,8 +322,8 @@ static __always_inline void iocsr_write64(u64 val, u32 reg)
#define CSR_ESTAT_EXC_WIDTH 6
#define CSR_ESTAT_EXC (_ULCAST_(0x3f) << CSR_ESTAT_EXC_SHIFT)
#define CSR_ESTAT_IS_SHIFT 0
-#define CSR_ESTAT_IS_WIDTH 15
-#define CSR_ESTAT_IS (_ULCAST_(0x7fff) << CSR_ESTAT_IS_SHIFT)
+#define CSR_ESTAT_IS_WIDTH 14
+#define CSR_ESTAT_IS (_ULCAST_(0x3fff) << CSR_ESTAT_IS_SHIFT)
#define LOONGARCH_CSR_ERA 0x6 /* ERA */
@@ -1090,7 +1090,7 @@ static __always_inline void iocsr_write64(u64 val, u32 reg)
#define ECFGF_IPI (_ULCAST_(1) << ECFGB_IPI)
#define ECFGF(hwirq) (_ULCAST_(1) << hwirq)
-#define ESTATF_IP 0x00001fff
+#define ESTATF_IP 0x00003fff
#define LOONGARCH_IOCSR_FEATURES 0x8
#define IOCSRF_TEMP BIT_ULL(0)
@@ -1418,23 +1418,26 @@ __BUILD_CSR_OP(tlbidx)
#define EXCSUBCODE_GCHC 1 /* Hardware caused */
#define EXCCODE_SE 25 /* Security */
-#define EXCCODE_INT_START 64
-#define EXCCODE_SIP0 64
-#define EXCCODE_SIP1 65
-#define EXCCODE_IP0 66
-#define EXCCODE_IP1 67
-#define EXCCODE_IP2 68
-#define EXCCODE_IP3 69
-#define EXCCODE_IP4 70
-#define EXCCODE_IP5 71
-#define EXCCODE_IP6 72
-#define EXCCODE_IP7 73
-#define EXCCODE_PMC 74 /* Performance Counter */
-#define EXCCODE_TIMER 75
-#define EXCCODE_IPI 76
-#define EXCCODE_NMI 77
-#define EXCCODE_INT_END 78
-#define EXCCODE_INT_NUM (EXCCODE_INT_END - EXCCODE_INT_START)
+/* Interrupt numbers */
+#define INT_SWI0 0 /* Software Interrupts */
+#define INT_SWI1 1
+#define INT_HWI0 2 /* Hardware Interrupts */
+#define INT_HWI1 3
+#define INT_HWI2 4
+#define INT_HWI3 5
+#define INT_HWI4 6
+#define INT_HWI5 7
+#define INT_HWI6 8
+#define INT_HWI7 9
+#define INT_PCOV 10 /* Performance Counter Overflow */
+#define INT_TI 11 /* Timer */
+#define INT_IPI 12
+#define INT_NMI 13
+
+/* ExcCodes corresponding to interrupts */
+#define EXCCODE_INT_NUM (INT_NMI + 1)
+#define EXCCODE_INT_START 64
+#define EXCCODE_INT_END (EXCCODE_INT_START + EXCCODE_INT_NUM - 1)
/* FPU register names */
#define LOONGARCH_FCSR0 $r0
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index 0524bf1169b7..883e5066ae44 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -92,7 +92,7 @@ static int __init get_ipi_irq(void)
struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
if (d)
- return irq_create_mapping(d, EXCCODE_IPI - EXCCODE_INT_START);
+ return irq_create_mapping(d, INT_IPI);
return -EINVAL;
}
diff --git a/arch/loongarch/kernel/perf_event.c b/arch/loongarch/kernel/perf_event.c
index 707bd32e5c4f..ff28f99b47d7 100644
--- a/arch/loongarch/kernel/perf_event.c
+++ b/arch/loongarch/kernel/perf_event.c
@@ -461,7 +461,7 @@ static int get_pmc_irq(void)
struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
if (d)
- return irq_create_mapping(d, EXCCODE_PMC - EXCCODE_INT_START);
+ return irq_create_mapping(d, INT_PCOV);
return -EINVAL;
}
diff --git a/arch/loongarch/kernel/time.c b/arch/loongarch/kernel/time.c
index 4351f69d9950..f377e50f3c66 100644
--- a/arch/loongarch/kernel/time.c
+++ b/arch/loongarch/kernel/time.c
@@ -133,7 +133,7 @@ static int get_timer_irq(void)
struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
if (d)
- return irq_create_mapping(d, EXCCODE_TIMER - EXCCODE_INT_START);
+ return irq_create_mapping(d, INT_TI);
return -EINVAL;
}
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index de8ebe20b666..3fb4709c3b19 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -792,7 +792,7 @@ void __init trap_init(void)
long i;
/* Set interrupt vector handler */
- for (i = EXCCODE_INT_START; i < EXCCODE_INT_END; i++)
+ for (i = EXCCODE_INT_START; i <= EXCCODE_INT_END; i++)
set_handler(i * VECSIZE, handle_vint, VECSIZE);
set_handler(EXCCODE_ADE * VECSIZE, handle_ade, VECSIZE);
--
2.40.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 02/13] LoongArch: Add exception subcode definitions for the watchpoint exception
2023-04-22 17:34 [PATCH v6 00/13] LoongArch: Better backtraces WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 01/13] LoongArch: Clean up the architectural interrupt definitions WANG Xuerui
@ 2023-04-22 17:34 ` WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 03/13] LoongArch: Print GPRs with ABI names when showing registers WANG Xuerui
` (10 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: WANG Xuerui @ 2023-04-22 17:34 UTC (permalink / raw
To: Huacai Chen; +Cc: loongarch, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Add them to enable matching the sub-exceptions for humanization purposes
later.
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
arch/loongarch/include/asm/loongarch.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index 7d8b83dd32e9..da5b572b2d2f 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -1408,7 +1408,9 @@ __BUILD_CSR_OP(tlbidx)
#define EXCCODE_FPE 18 /* Floating Point Exception */
#define EXCSUBCODE_FPE 0 /* Floating Point Exception */
#define EXCSUBCODE_VFPE 1 /* Vector Exception */
-#define EXCCODE_WATCH 19 /* Watch address reference */
+#define EXCCODE_WATCH 19 /* WatchPoint Exception */
+ #define EXCSUBCODE_WPEF 0 /* ... on instruction Fetch */
+ #define EXCSUBCODE_WPEM 1 /* ... on Memory access */
#define EXCCODE_BTDIS 20 /* Binary Trans. Disabled */
#define EXCCODE_BTE 21 /* Binary Trans. Exception */
#define EXCCODE_PSI 22 /* Guest Privileged Error */
--
2.40.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 03/13] LoongArch: Print GPRs with ABI names when showing registers
2023-04-22 17:34 [PATCH v6 00/13] LoongArch: Better backtraces WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 01/13] LoongArch: Clean up the architectural interrupt definitions WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 02/13] LoongArch: Add exception subcode definitions for the watchpoint exception WANG Xuerui
@ 2023-04-22 17:34 ` WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 04/13] LoongArch: Print symbol info for CSR.ERA and $ra only for kernel-mode contexts WANG Xuerui
` (9 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: WANG Xuerui @ 2023-04-22 17:34 UTC (permalink / raw
To: Huacai Chen; +Cc: loongarch, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Show PC (CSR.ERA) in place of $zero, and also show the syscall restart
flag (conveniently stuffed in regs[0]) if non-zero.
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
arch/loongarch/kernel/traps.c | 36 ++++++++++++++++++++++-------------
1 file changed, 23 insertions(+), 13 deletions(-)
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index 3fb4709c3b19..b67607916b7f 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -158,22 +158,32 @@ static void __show_regs(const struct pt_regs *regs)
const int field = 2 * sizeof(unsigned long);
unsigned int excsubcode;
unsigned int exccode;
- int i;
show_regs_print_info(KERN_DEFAULT);
- /*
- * Saved main processor registers
- */
- for (i = 0; i < 32; ) {
- if ((i % 4) == 0)
- printk("$%2d :", i);
- pr_cont(" %0*lx", field, regs->regs[i]);
-
- i++;
- if ((i % 4) == 0)
- pr_cont("\n");
- }
+ /* Print GPRs except $zero (substituting with PC/ERA) */
+#define GPR_FIELD(x) field, regs->regs[x]
+ pr_cont("pc %0*lx ra %0*lx tp %0*lx sp %0*lx\n",
+ field, regs->csr_era, GPR_FIELD(1), GPR_FIELD(2), GPR_FIELD(3));
+ pr_cont("a0 %0*lx a1 %0*lx a2 %0*lx a3 %0*lx\n",
+ GPR_FIELD(4), GPR_FIELD(5), GPR_FIELD(6), GPR_FIELD(7));
+ pr_cont("a4 %0*lx a5 %0*lx a6 %0*lx a7 %0*lx\n",
+ GPR_FIELD(8), GPR_FIELD(9), GPR_FIELD(10), GPR_FIELD(11));
+ pr_cont("t0 %0*lx t1 %0*lx t2 %0*lx t3 %0*lx\n",
+ GPR_FIELD(12), GPR_FIELD(13), GPR_FIELD(14), GPR_FIELD(15));
+ pr_cont("t4 %0*lx t5 %0*lx t6 %0*lx t7 %0*lx\n",
+ GPR_FIELD(16), GPR_FIELD(17), GPR_FIELD(18), GPR_FIELD(19));
+ pr_cont("t8 %0*lx u0 %0*lx s9 %0*lx s0 %0*lx\n",
+ GPR_FIELD(20), GPR_FIELD(21), GPR_FIELD(22), GPR_FIELD(23));
+ pr_cont("s1 %0*lx s2 %0*lx s3 %0*lx s4 %0*lx\n",
+ GPR_FIELD(24), GPR_FIELD(25), GPR_FIELD(26), GPR_FIELD(27));
+ pr_cont("s5 %0*lx s6 %0*lx s7 %0*lx s8 %0*lx\n",
+ GPR_FIELD(28), GPR_FIELD(29), GPR_FIELD(30), GPR_FIELD(31));
+
+ /* The slot for $zero is reused as the syscall restart flag */
+ if (regs->regs[0])
+ pr_cont("syscall restart flag: %0*lx\n", GPR_FIELD(0));
+#undef GPR_FIELD
/*
* Saved csr registers
--
2.40.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 04/13] LoongArch: Print symbol info for CSR.ERA and $ra only for kernel-mode contexts
2023-04-22 17:34 [PATCH v6 00/13] LoongArch: Better backtraces WANG Xuerui
` (2 preceding siblings ...)
2023-04-22 17:34 ` [PATCH v6 03/13] LoongArch: Print GPRs with ABI names when showing registers WANG Xuerui
@ 2023-04-22 17:34 ` WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 05/13] LoongArch: Fix format of CSR lines during show_regs WANG Xuerui
` (8 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: WANG Xuerui @ 2023-04-22 17:34 UTC (permalink / raw
To: Huacai Chen; +Cc: loongarch, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Otherwise the addresses wouldn't make sense at all.
While at it, align the "map keys" to maintain right-alignment with the
"estat:" line too; also swap the ERA and ra lines so all CSRs are shown
together.
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
arch/loongarch/kernel/traps.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index b67607916b7f..801469cf9f90 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -183,15 +183,15 @@ static void __show_regs(const struct pt_regs *regs)
/* The slot for $zero is reused as the syscall restart flag */
if (regs->regs[0])
pr_cont("syscall restart flag: %0*lx\n", GPR_FIELD(0));
-#undef GPR_FIELD
- /*
- * Saved csr registers
- */
- printk("era : %0*lx %pS\n", field, regs->csr_era,
- (void *) regs->csr_era);
- printk("ra : %0*lx %pS\n", field, regs->regs[1],
- (void *) regs->regs[1]);
+ if (user_mode(regs)) {
+ pr_cont(" ra: %0*lx\n", GPR_FIELD(1));
+ pr_cont(" ERA: %0*lx\n", field, regs->csr_era);
+ } else {
+ pr_cont(" ra: %0*lx %pS\n", GPR_FIELD(1), (void *) regs->regs[1]);
+ pr_cont(" ERA: %0*lx %pS\n", field, regs->csr_era, (void *) regs->csr_era);
+ }
+#undef GPR_FIELD
printk("CSR crmd: %08lx ", regs->csr_crmd);
printk("CSR prmd: %08lx ", regs->csr_prmd);
--
2.40.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 05/13] LoongArch: Fix format of CSR lines during show_regs
2023-04-22 17:34 [PATCH v6 00/13] LoongArch: Better backtraces WANG Xuerui
` (3 preceding siblings ...)
2023-04-22 17:34 ` [PATCH v6 04/13] LoongArch: Print symbol info for CSR.ERA and $ra only for kernel-mode contexts WANG Xuerui
@ 2023-04-22 17:34 ` WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 06/13] LoongArch: Humanize the CRMD line when showing registers WANG Xuerui
` (7 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: WANG Xuerui @ 2023-04-22 17:34 UTC (permalink / raw
To: Huacai Chen; +Cc: loongarch, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Use uppercase CSR names throughout for consistency with the manual
wording, and right-align the keys. The "CSR" part is inferrable from
context, hence dropped for more horizontal space.
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
arch/loongarch/kernel/traps.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index 801469cf9f90..8130063ed553 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -193,13 +193,12 @@ static void __show_regs(const struct pt_regs *regs)
}
#undef GPR_FIELD
- printk("CSR crmd: %08lx ", regs->csr_crmd);
- printk("CSR prmd: %08lx ", regs->csr_prmd);
- printk("CSR euen: %08lx ", regs->csr_euen);
- printk("CSR ecfg: %08lx ", regs->csr_ecfg);
- printk("CSR estat: %08lx ", regs->csr_estat);
-
- pr_cont("\n");
+ /* Print important CSRs */
+ pr_cont(" CRMD: %08lx\n", regs->csr_crmd);
+ pr_cont(" PRMD: %08lx\n", regs->csr_prmd);
+ pr_cont(" EUEN: %08lx\n", regs->csr_euen);
+ pr_cont(" ECFG: %08lx\n", regs->csr_ecfg);
+ pr_cont("ESTAT: %08lx\n", regs->csr_estat);
exccode = ((regs->csr_estat) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT;
excsubcode = ((regs->csr_estat) & CSR_ESTAT_ESUBCODE) >> CSR_ESTAT_ESUBCODE_SHIFT;
--
2.40.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 06/13] LoongArch: Humanize the CRMD line when showing registers
2023-04-22 17:34 [PATCH v6 00/13] LoongArch: Better backtraces WANG Xuerui
` (4 preceding siblings ...)
2023-04-22 17:34 ` [PATCH v6 05/13] LoongArch: Fix format of CSR lines during show_regs WANG Xuerui
@ 2023-04-22 17:34 ` WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 07/13] LoongArch: Humanize the PRMD " WANG Xuerui
` (6 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: WANG Xuerui @ 2023-04-22 17:34 UTC (permalink / raw
To: Huacai Chen; +Cc: loongarch, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Example output looks like:
[ xx.xxxxxx] CRMD: 000000b0 (PLV0 -IE -DA +PG DACF=CC DACM=CC -WE)
Some initial machinery for this pretty-printing format has been included
in this patch as well.
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
arch/loongarch/kernel/traps.c | 46 ++++++++++++++++++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index 8130063ed553..fb6d293e93d2 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -3,6 +3,7 @@
* Author: Huacai Chen <chenhuacai@loongson.cn>
* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
*/
+#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/bug.h>
#include <linux/compiler.h>
@@ -153,6 +154,49 @@ static void show_code(unsigned int *pc, bool user)
pr_cont("\n");
}
+static void print_bool_fragment(const char *key, unsigned long val, bool first)
+{
+ /* e.g. "+PG", "-DA" */
+ pr_cont("%s%c%s", first ? "" : " ", val ? '+' : '-', key);
+}
+
+static void print_plv_fragment(const char *key, int val)
+{
+ /* e.g. "PLV0", "PPLV3" */
+ pr_cont("%s%d", key, val);
+}
+
+static void print_memory_type_fragment(const char *key, unsigned long val)
+{
+ /* e.g. "DATM=WUC" */
+ const char *humanized_type = NULL;
+
+ switch (val) {
+ case 0: humanized_type = "SUC"; break;
+ case 1: humanized_type = "CC"; break;
+ case 2: humanized_type = "WUC"; break;
+ }
+
+ if (humanized_type) {
+ pr_cont(" %s=%s", key, humanized_type);
+ } else {
+ pr_cont(" %s=Reserved(%lu)", key, val);
+ }
+}
+
+static void print_crmd(unsigned long x)
+{
+ pr_cont(" CRMD: %08lx (", x);
+ print_plv_fragment("PLV", (int) FIELD_GET(CSR_CRMD_PLV, x));
+ print_bool_fragment("IE", FIELD_GET(CSR_CRMD_IE, x), false);
+ print_bool_fragment("DA", FIELD_GET(CSR_CRMD_DA, x), false);
+ print_bool_fragment("PG", FIELD_GET(CSR_CRMD_PG, x), false);
+ print_memory_type_fragment("DACF", FIELD_GET(CSR_CRMD_DACF, x));
+ print_memory_type_fragment("DACM", FIELD_GET(CSR_CRMD_DACM, x));
+ print_bool_fragment("WE", FIELD_GET(CSR_CRMD_WE, x), false);
+ pr_cont(")\n");
+}
+
static void __show_regs(const struct pt_regs *regs)
{
const int field = 2 * sizeof(unsigned long);
@@ -194,7 +238,7 @@ static void __show_regs(const struct pt_regs *regs)
#undef GPR_FIELD
/* Print important CSRs */
- pr_cont(" CRMD: %08lx\n", regs->csr_crmd);
+ print_crmd(regs->csr_crmd);
pr_cont(" PRMD: %08lx\n", regs->csr_prmd);
pr_cont(" EUEN: %08lx\n", regs->csr_euen);
pr_cont(" ECFG: %08lx\n", regs->csr_ecfg);
--
2.40.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 07/13] LoongArch: Humanize the PRMD line when showing registers
2023-04-22 17:34 [PATCH v6 00/13] LoongArch: Better backtraces WANG Xuerui
` (5 preceding siblings ...)
2023-04-22 17:34 ` [PATCH v6 06/13] LoongArch: Humanize the CRMD line when showing registers WANG Xuerui
@ 2023-04-22 17:34 ` WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 08/13] LoongArch: Humanize the EUEN " WANG Xuerui
` (5 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: WANG Xuerui @ 2023-04-22 17:34 UTC (permalink / raw
To: Huacai Chen; +Cc: loongarch, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Example output looks like:
[ xx.xxxxxx] PRMD: 00000004 (PPLV0 +PIE -PWE)
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
arch/loongarch/kernel/traps.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index fb6d293e93d2..3d4987d24552 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -197,6 +197,15 @@ static void print_crmd(unsigned long x)
pr_cont(")\n");
}
+static void print_prmd(unsigned long x)
+{
+ pr_cont(" PRMD: %08lx (", x);
+ print_plv_fragment("PPLV", (int) FIELD_GET(CSR_PRMD_PPLV, x));
+ print_bool_fragment("PIE", FIELD_GET(CSR_PRMD_PIE, x), false);
+ print_bool_fragment("PWE", FIELD_GET(CSR_PRMD_PWE, x), false);
+ pr_cont(")\n");
+}
+
static void __show_regs(const struct pt_regs *regs)
{
const int field = 2 * sizeof(unsigned long);
@@ -239,7 +248,7 @@ static void __show_regs(const struct pt_regs *regs)
/* Print important CSRs */
print_crmd(regs->csr_crmd);
- pr_cont(" PRMD: %08lx\n", regs->csr_prmd);
+ print_prmd(regs->csr_prmd);
pr_cont(" EUEN: %08lx\n", regs->csr_euen);
pr_cont(" ECFG: %08lx\n", regs->csr_ecfg);
pr_cont("ESTAT: %08lx\n", regs->csr_estat);
--
2.40.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 08/13] LoongArch: Humanize the EUEN line when showing registers
2023-04-22 17:34 [PATCH v6 00/13] LoongArch: Better backtraces WANG Xuerui
` (6 preceding siblings ...)
2023-04-22 17:34 ` [PATCH v6 07/13] LoongArch: Humanize the PRMD " WANG Xuerui
@ 2023-04-22 17:34 ` WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 09/13] LoongArch: Humanize the ECFG " WANG Xuerui
` (4 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: WANG Xuerui @ 2023-04-22 17:34 UTC (permalink / raw
To: Huacai Chen; +Cc: loongarch, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Example output looks like:
[ xx.xxxxxx] EUEN: 00000000 (-FPE -SXE -ASXE -BTE)
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
arch/loongarch/kernel/traps.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index 3d4987d24552..c41bc7913eb6 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -206,6 +206,16 @@ static void print_prmd(unsigned long x)
pr_cont(")\n");
}
+static void print_euen(unsigned long x)
+{
+ pr_cont(" EUEN: %08lx (", x);
+ print_bool_fragment("FPE", FIELD_GET(CSR_EUEN_FPEN, x), true);
+ print_bool_fragment("SXE", FIELD_GET(CSR_EUEN_LSXEN, x), false);
+ print_bool_fragment("ASXE", FIELD_GET(CSR_EUEN_LASXEN, x), false);
+ print_bool_fragment("BTE", FIELD_GET(CSR_EUEN_LBTEN, x), false);
+ pr_cont(")\n");
+}
+
static void __show_regs(const struct pt_regs *regs)
{
const int field = 2 * sizeof(unsigned long);
@@ -249,7 +259,7 @@ static void __show_regs(const struct pt_regs *regs)
/* Print important CSRs */
print_crmd(regs->csr_crmd);
print_prmd(regs->csr_prmd);
- pr_cont(" EUEN: %08lx\n", regs->csr_euen);
+ print_euen(regs->csr_euen);
pr_cont(" ECFG: %08lx\n", regs->csr_ecfg);
pr_cont("ESTAT: %08lx\n", regs->csr_estat);
--
2.40.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 09/13] LoongArch: Humanize the ECFG line when showing registers
2023-04-22 17:34 [PATCH v6 00/13] LoongArch: Better backtraces WANG Xuerui
` (7 preceding siblings ...)
2023-04-22 17:34 ` [PATCH v6 08/13] LoongArch: Humanize the EUEN " WANG Xuerui
@ 2023-04-22 17:34 ` WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 10/13] LoongArch: Humanize the ESTAT " WANG Xuerui
` (3 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: WANG Xuerui @ 2023-04-22 17:34 UTC (permalink / raw
To: Huacai Chen; +Cc: loongarch, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Example output looks like:
[ xx.xxxxxx] ECFG: 00071c1c (LIE=2-4,10-12 VS=7)
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
arch/loongarch/kernel/traps.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index c41bc7913eb6..cab31a9c7ea9 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -184,6 +184,12 @@ static void print_memory_type_fragment(const char *key, unsigned long val)
}
}
+static void print_intr_fragment(const char *key, unsigned long val)
+{
+ /* e.g. "LIE=0-1,3,5-7" */
+ pr_cont("%s=%*pbl", key, EXCCODE_INT_NUM, &val);
+}
+
static void print_crmd(unsigned long x)
{
pr_cont(" CRMD: %08lx (", x);
@@ -216,6 +222,13 @@ static void print_euen(unsigned long x)
pr_cont(")\n");
}
+static void print_ecfg(unsigned long x)
+{
+ pr_cont(" ECFG: %08lx (", x);
+ print_intr_fragment("LIE", FIELD_GET(CSR_ECFG_IM, x));
+ pr_cont(" VS=%d)\n", (int) FIELD_GET(CSR_ECFG_VS, x));
+}
+
static void __show_regs(const struct pt_regs *regs)
{
const int field = 2 * sizeof(unsigned long);
@@ -260,7 +273,7 @@ static void __show_regs(const struct pt_regs *regs)
print_crmd(regs->csr_crmd);
print_prmd(regs->csr_prmd);
print_euen(regs->csr_euen);
- pr_cont(" ECFG: %08lx\n", regs->csr_ecfg);
+ print_ecfg(regs->csr_ecfg);
pr_cont("ESTAT: %08lx\n", regs->csr_estat);
exccode = ((regs->csr_estat) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT;
--
2.40.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 10/13] LoongArch: Humanize the ESTAT line when showing registers
2023-04-22 17:34 [PATCH v6 00/13] LoongArch: Better backtraces WANG Xuerui
` (8 preceding siblings ...)
2023-04-22 17:34 ` [PATCH v6 09/13] LoongArch: Humanize the ECFG " WANG Xuerui
@ 2023-04-22 17:34 ` WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 11/13] LoongArch: Use ISA manual names for BADV and CPUCFG.PRID lines in show_regs WANG Xuerui
` (2 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: WANG Xuerui @ 2023-04-22 17:34 UTC (permalink / raw
To: Huacai Chen; +Cc: loongarch, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Example output looks like:
[ xx.xxxxxx] ESTAT: 00001000 [INT] (IS=12 ECode=0 EsubCode=0)
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
arch/loongarch/kernel/traps.c | 84 ++++++++++++++++++++++++++++++++---
1 file changed, 77 insertions(+), 7 deletions(-)
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index cab31a9c7ea9..bd562f2da065 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -229,11 +229,85 @@ static void print_ecfg(unsigned long x)
pr_cont(" VS=%d)\n", (int) FIELD_GET(CSR_ECFG_VS, x));
}
+static const char *humanize_exc_name(unsigned int ecode, unsigned int esubcode)
+{
+ /*
+ * Right now the kernel source refers to the exceptions using mostly
+ * MIPS-esque names, but LoongArch users and developers are probably
+ * more familiar with those in the ISA manual, so we are going to
+ * print out the latter. Expect much friction between the two sides
+ * below...
+ */
+ switch (ecode) {
+ case EXCCODE_RSV: return "INT";
+ case EXCCODE_TLBL: return "PIL";
+ case EXCCODE_TLBS: return "PIS";
+ case EXCCODE_TLBI: return "PIF";
+ case EXCCODE_TLBM: return "PME";
+ case EXCCODE_TLBNR: return "PNR";
+ case EXCCODE_TLBNX: return "PNX";
+ case EXCCODE_TLBPE: return "PPI";
+ case EXCCODE_ADE:
+ switch (esubcode) {
+ case EXSUBCODE_ADEF: return "ADEF";
+ case EXSUBCODE_ADEM: return "ADEM";
+ }
+ break;
+ case EXCCODE_ALE: return "ALE";
+ case EXCCODE_OOB: return "BCE";
+ case EXCCODE_SYS: return "SYS";
+ case EXCCODE_BP: return "BRK";
+ case EXCCODE_INE: return "INE";
+ case EXCCODE_IPE: return "IPE";
+ case EXCCODE_FPDIS: return "FPD";
+ case EXCCODE_LSXDIS: return "SXD";
+ case EXCCODE_LASXDIS: return "ASXD";
+ case EXCCODE_FPE:
+ switch (esubcode) {
+ case EXCSUBCODE_FPE: return "FPE";
+ case EXCSUBCODE_VFPE: return "VFPE";
+ }
+ break;
+ case EXCCODE_WATCH:
+ switch (esubcode) {
+ case EXCSUBCODE_WPEF: return "WPEF";
+ case EXCSUBCODE_WPEM: return "WPEM";
+ }
+ break;
+ case EXCCODE_BTDIS: return "BTD";
+ case EXCCODE_BTE: return "BTE";
+ case EXCCODE_PSI: return "GSPR";
+ case EXCCODE_HYP: return "HVC";
+ case EXCCODE_GCM:
+ switch (esubcode) {
+ case EXCSUBCODE_GCSC: return "GCSC";
+ case EXCSUBCODE_GCHC: return "GCHC";
+ }
+ break;
+ /*
+ * The manual did not mention the EXCCODE_SE case, but print out it
+ * nevertheless.
+ */
+ case EXCCODE_SE: return "SE";
+ }
+
+ return "???";
+}
+
+static void print_estat(unsigned long x)
+{
+ unsigned int ecode = FIELD_GET(CSR_ESTAT_EXC, x);
+ unsigned int esubcode = FIELD_GET(CSR_ESTAT_ESUBCODE, x);
+
+ pr_cont("ESTAT: %08lx [%s] (", x, humanize_exc_name(ecode, esubcode));
+ print_intr_fragment("IS", FIELD_GET(CSR_ESTAT_IS, x));
+ pr_cont(" ECode=%d EsubCode=%d)\n", (int) ecode, (int) esubcode);
+}
+
static void __show_regs(const struct pt_regs *regs)
{
const int field = 2 * sizeof(unsigned long);
- unsigned int excsubcode;
- unsigned int exccode;
+ unsigned int exccode = FIELD_GET(CSR_ESTAT_EXC, regs->csr_estat);
show_regs_print_info(KERN_DEFAULT);
@@ -274,11 +348,7 @@ static void __show_regs(const struct pt_regs *regs)
print_prmd(regs->csr_prmd);
print_euen(regs->csr_euen);
print_ecfg(regs->csr_ecfg);
- pr_cont("ESTAT: %08lx\n", regs->csr_estat);
-
- exccode = ((regs->csr_estat) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT;
- excsubcode = ((regs->csr_estat) & CSR_ESTAT_ESUBCODE) >> CSR_ESTAT_ESUBCODE_SHIFT;
- printk("ExcCode : %x (SubCode %x)\n", exccode, excsubcode);
+ print_estat(regs->csr_estat);
if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE)
printk("BadVA : %0*lx\n", field, regs->csr_badvaddr);
--
2.40.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 11/13] LoongArch: Use ISA manual names for BADV and CPUCFG.PRID lines in show_regs
2023-04-22 17:34 [PATCH v6 00/13] LoongArch: Better backtraces WANG Xuerui
` (9 preceding siblings ...)
2023-04-22 17:34 ` [PATCH v6 10/13] LoongArch: Humanize the ESTAT " WANG Xuerui
@ 2023-04-22 17:34 ` WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 12/13] LoongArch: Include CSR.BADV in show_regs in case of BCE exceptions WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 13/13] LoongArch: Also include current CPU's full name in show_regs output WANG Xuerui
12 siblings, 0 replies; 16+ messages in thread
From: WANG Xuerui @ 2023-04-22 17:34 UTC (permalink / raw
To: Huacai Chen; +Cc: loongarch, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
While at it, also change the printk to pr_cont.
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
arch/loongarch/kernel/traps.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index bd562f2da065..a87c74f2ed1a 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -351,9 +351,9 @@ static void __show_regs(const struct pt_regs *regs)
print_estat(regs->csr_estat);
if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE)
- printk("BadVA : %0*lx\n", field, regs->csr_badvaddr);
+ pr_cont(" BADV: %0*lx\n", field, regs->csr_badvaddr);
- printk("PrId : %08x (%s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
+ pr_cont(" PRID: %08x (%s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
cpu_family_string());
}
--
2.40.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 12/13] LoongArch: Include CSR.BADV in show_regs in case of BCE exceptions
2023-04-22 17:34 [PATCH v6 00/13] LoongArch: Better backtraces WANG Xuerui
` (10 preceding siblings ...)
2023-04-22 17:34 ` [PATCH v6 11/13] LoongArch: Use ISA manual names for BADV and CPUCFG.PRID lines in show_regs WANG Xuerui
@ 2023-04-22 17:34 ` WANG Xuerui
2023-04-25 7:36 ` Huacai Chen
2023-04-22 17:34 ` [PATCH v6 13/13] LoongArch: Also include current CPU's full name in show_regs output WANG Xuerui
12 siblings, 1 reply; 16+ messages in thread
From: WANG Xuerui @ 2023-04-22 17:34 UTC (permalink / raw
To: Huacai Chen; +Cc: loongarch, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
According to the LoongArch ISA Manual's description for CSR.BADV
(Volume 1, Section 7.4.8), CSR.BADV is supposed to be updated in case of
BCE [Bound checking error] too, in addition to the current implemented
list of exceptions.
Note: in my experiments CSR.BADV actually does *not* seem to reflect the
offending out-of-bounds value at all, regardless of the instruction used
(neither asrt{gt,le} nor {ld,st}{gt,le}). My wild guess is that when the
assertion fails, the execution of the instruction has not proceeded to
MEM stage yet, and that only in this stage is CSR.BADV potentially
updated. We show it nevertheless because it does not hurt and it is
generally better to maintain consistency with the manuals.
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
arch/loongarch/kernel/traps.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index a87c74f2ed1a..6c8ecc05183a 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -350,7 +350,7 @@ static void __show_regs(const struct pt_regs *regs)
print_ecfg(regs->csr_ecfg);
print_estat(regs->csr_estat);
- if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE)
+ if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_OOB)
pr_cont(" BADV: %0*lx\n", field, regs->csr_badvaddr);
pr_cont(" PRID: %08x (%s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
--
2.40.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 13/13] LoongArch: Also include current CPU's full name in show_regs output
2023-04-22 17:34 [PATCH v6 00/13] LoongArch: Better backtraces WANG Xuerui
` (11 preceding siblings ...)
2023-04-22 17:34 ` [PATCH v6 12/13] LoongArch: Include CSR.BADV in show_regs in case of BCE exceptions WANG Xuerui
@ 2023-04-22 17:34 ` WANG Xuerui
12 siblings, 0 replies; 16+ messages in thread
From: WANG Xuerui @ 2023-04-22 17:34 UTC (permalink / raw
To: Huacai Chen; +Cc: loongarch, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
It may be more helpful for developers looking at the resulting dumps,
because multiple distinct CPU models may share the same PRID. Not having
this info available may hide problems only found on some but not all of
the models sharing one specific PRID.
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
arch/loongarch/kernel/traps.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index 6c8ecc05183a..8b268c133b92 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -353,8 +353,8 @@ static void __show_regs(const struct pt_regs *regs)
if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_OOB)
pr_cont(" BADV: %0*lx\n", field, regs->csr_badvaddr);
- pr_cont(" PRID: %08x (%s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
- cpu_family_string());
+ pr_cont(" PRID: %08x (%s, %s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
+ cpu_family_string(), cpu_full_name_string());
}
void show_regs(struct pt_regs *regs)
--
2.40.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v6 01/13] LoongArch: Clean up the architectural interrupt definitions
2023-04-22 17:34 ` [PATCH v6 01/13] LoongArch: Clean up the architectural interrupt definitions WANG Xuerui
@ 2023-04-25 7:32 ` Huacai Chen
0 siblings, 0 replies; 16+ messages in thread
From: Huacai Chen @ 2023-04-25 7:32 UTC (permalink / raw
To: WANG Xuerui; +Cc: loongarch, WANG Xuerui
On Sun, Apr 23, 2023 at 1:35 AM WANG Xuerui <kernel@xen0n.name> wrote:
>
> From: WANG Xuerui <git@xen0n.name>
>
> While interrupts are assigned ECodes `64 + interrupt number`, all
> existing use sites of interrupt numbers want the 64 subtracted.
> Re-arrange the definitions so that the actual interrupt number is used
> everywhere, and make EXCCODE_INT_END inclusive as it is more intuitive
> that way.
>
> While at it, according to the asm/loongarch.h definitions, the total
> number of architectural interrupts should be 14 instead of 13. Relevant
> bitfields and masks have been adjusted as well.
>
> Signed-off-by: WANG Xuerui <git@xen0n.name>
> ---
> arch/loongarch/include/asm/loongarch.h | 47 ++++++++++++++------------
> arch/loongarch/kernel/irq.c | 2 +-
> arch/loongarch/kernel/perf_event.c | 2 +-
> arch/loongarch/kernel/time.c | 2 +-
> arch/loongarch/kernel/traps.c | 2 +-
> 5 files changed, 29 insertions(+), 26 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
> index 83da5d29e2d1..7d8b83dd32e9 100644
> --- a/arch/loongarch/include/asm/loongarch.h
> +++ b/arch/loongarch/include/asm/loongarch.h
> @@ -311,8 +311,8 @@ static __always_inline void iocsr_write64(u64 val, u32 reg)
> #define CSR_ECFG_VS_WIDTH 3
> #define CSR_ECFG_VS (_ULCAST_(0x7) << CSR_ECFG_VS_SHIFT)
> #define CSR_ECFG_IM_SHIFT 0
> -#define CSR_ECFG_IM_WIDTH 13
> -#define CSR_ECFG_IM (_ULCAST_(0x1fff) << CSR_ECFG_IM_SHIFT)
> +#define CSR_ECFG_IM_WIDTH 14
> +#define CSR_ECFG_IM (_ULCAST_(0x3fff) << CSR_ECFG_IM_SHIFT)
>
> #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */
> #define CSR_ESTAT_ESUBCODE_SHIFT 22
> @@ -322,8 +322,8 @@ static __always_inline void iocsr_write64(u64 val, u32 reg)
> #define CSR_ESTAT_EXC_WIDTH 6
> #define CSR_ESTAT_EXC (_ULCAST_(0x3f) << CSR_ESTAT_EXC_SHIFT)
> #define CSR_ESTAT_IS_SHIFT 0
> -#define CSR_ESTAT_IS_WIDTH 15
> -#define CSR_ESTAT_IS (_ULCAST_(0x7fff) << CSR_ESTAT_IS_SHIFT)
> +#define CSR_ESTAT_IS_WIDTH 14
> +#define CSR_ESTAT_IS (_ULCAST_(0x3fff) << CSR_ESTAT_IS_SHIFT)
>
> #define LOONGARCH_CSR_ERA 0x6 /* ERA */
>
> @@ -1090,7 +1090,7 @@ static __always_inline void iocsr_write64(u64 val, u32 reg)
> #define ECFGF_IPI (_ULCAST_(1) << ECFGB_IPI)
> #define ECFGF(hwirq) (_ULCAST_(1) << hwirq)
>
> -#define ESTATF_IP 0x00001fff
> +#define ESTATF_IP 0x00003fff
>
> #define LOONGARCH_IOCSR_FEATURES 0x8
> #define IOCSRF_TEMP BIT_ULL(0)
> @@ -1418,23 +1418,26 @@ __BUILD_CSR_OP(tlbidx)
> #define EXCSUBCODE_GCHC 1 /* Hardware caused */
> #define EXCCODE_SE 25 /* Security */
>
> -#define EXCCODE_INT_START 64
> -#define EXCCODE_SIP0 64
> -#define EXCCODE_SIP1 65
> -#define EXCCODE_IP0 66
> -#define EXCCODE_IP1 67
> -#define EXCCODE_IP2 68
> -#define EXCCODE_IP3 69
> -#define EXCCODE_IP4 70
> -#define EXCCODE_IP5 71
> -#define EXCCODE_IP6 72
> -#define EXCCODE_IP7 73
> -#define EXCCODE_PMC 74 /* Performance Counter */
> -#define EXCCODE_TIMER 75
> -#define EXCCODE_IPI 76
> -#define EXCCODE_NMI 77
> -#define EXCCODE_INT_END 78
> -#define EXCCODE_INT_NUM (EXCCODE_INT_END - EXCCODE_INT_START)
> +/* Interrupt numbers */
> +#define INT_SWI0 0 /* Software Interrupts */
> +#define INT_SWI1 1
> +#define INT_HWI0 2 /* Hardware Interrupts */
> +#define INT_HWI1 3
> +#define INT_HWI2 4
> +#define INT_HWI3 5
> +#define INT_HWI4 6
> +#define INT_HWI5 7
> +#define INT_HWI6 8
> +#define INT_HWI7 9
> +#define INT_PCOV 10 /* Performance Counter Overflow */
> +#define INT_TI 11 /* Timer */
> +#define INT_IPI 12
> +#define INT_NMI 13
> +
> +/* ExcCodes corresponding to interrupts */
> +#define EXCCODE_INT_NUM (INT_NMI + 1)
> +#define EXCCODE_INT_START 64
> +#define EXCCODE_INT_END (EXCCODE_INT_START + EXCCODE_INT_NUM - 1)
>
> /* FPU register names */
> #define LOONGARCH_FCSR0 $r0
> diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
> index 0524bf1169b7..883e5066ae44 100644
> --- a/arch/loongarch/kernel/irq.c
> +++ b/arch/loongarch/kernel/irq.c
> @@ -92,7 +92,7 @@ static int __init get_ipi_irq(void)
> struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
>
> if (d)
> - return irq_create_mapping(d, EXCCODE_IPI - EXCCODE_INT_START);
> + return irq_create_mapping(d, INT_IPI);
>
> return -EINVAL;
> }
> diff --git a/arch/loongarch/kernel/perf_event.c b/arch/loongarch/kernel/perf_event.c
> index 707bd32e5c4f..ff28f99b47d7 100644
> --- a/arch/loongarch/kernel/perf_event.c
> +++ b/arch/loongarch/kernel/perf_event.c
> @@ -461,7 +461,7 @@ static int get_pmc_irq(void)
> struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
>
> if (d)
> - return irq_create_mapping(d, EXCCODE_PMC - EXCCODE_INT_START);
> + return irq_create_mapping(d, INT_PCOV);
>
> return -EINVAL;
> }
> diff --git a/arch/loongarch/kernel/time.c b/arch/loongarch/kernel/time.c
> index 4351f69d9950..f377e50f3c66 100644
> --- a/arch/loongarch/kernel/time.c
> +++ b/arch/loongarch/kernel/time.c
> @@ -133,7 +133,7 @@ static int get_timer_irq(void)
> struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
>
> if (d)
> - return irq_create_mapping(d, EXCCODE_TIMER - EXCCODE_INT_START);
> + return irq_create_mapping(d, INT_TI);
>
> return -EINVAL;
> }
> diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
> index de8ebe20b666..3fb4709c3b19 100644
> --- a/arch/loongarch/kernel/traps.c
> +++ b/arch/loongarch/kernel/traps.c
> @@ -792,7 +792,7 @@ void __init trap_init(void)
> long i;
>
> /* Set interrupt vector handler */
> - for (i = EXCCODE_INT_START; i < EXCCODE_INT_END; i++)
> + for (i = EXCCODE_INT_START; i <= EXCCODE_INT_END; i++)
> set_handler(i * VECSIZE, handle_vint, VECSIZE);
NMI doesn't use handle_vint(), so this part can be dropped.
Huacai
>
> set_handler(EXCCODE_ADE * VECSIZE, handle_ade, VECSIZE);
> --
> 2.40.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6 12/13] LoongArch: Include CSR.BADV in show_regs in case of BCE exceptions
2023-04-22 17:34 ` [PATCH v6 12/13] LoongArch: Include CSR.BADV in show_regs in case of BCE exceptions WANG Xuerui
@ 2023-04-25 7:36 ` Huacai Chen
0 siblings, 0 replies; 16+ messages in thread
From: Huacai Chen @ 2023-04-25 7:36 UTC (permalink / raw
To: WANG Xuerui; +Cc: loongarch, WANG Xuerui
This patch can be dropped because it is expected that BCE doesn't update BADV.
On Sun, Apr 23, 2023 at 1:36 AM WANG Xuerui <kernel@xen0n.name> wrote:
>
> From: WANG Xuerui <git@xen0n.name>
>
> According to the LoongArch ISA Manual's description for CSR.BADV
> (Volume 1, Section 7.4.8), CSR.BADV is supposed to be updated in case of
> BCE [Bound checking error] too, in addition to the current implemented
> list of exceptions.
>
> Note: in my experiments CSR.BADV actually does *not* seem to reflect the
> offending out-of-bounds value at all, regardless of the instruction used
> (neither asrt{gt,le} nor {ld,st}{gt,le}). My wild guess is that when the
> assertion fails, the execution of the instruction has not proceeded to
> MEM stage yet, and that only in this stage is CSR.BADV potentially
> updated. We show it nevertheless because it does not hurt and it is
> generally better to maintain consistency with the manuals.
>
> Signed-off-by: WANG Xuerui <git@xen0n.name>
> ---
> arch/loongarch/kernel/traps.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
> index a87c74f2ed1a..6c8ecc05183a 100644
> --- a/arch/loongarch/kernel/traps.c
> +++ b/arch/loongarch/kernel/traps.c
> @@ -350,7 +350,7 @@ static void __show_regs(const struct pt_regs *regs)
> print_ecfg(regs->csr_ecfg);
> print_estat(regs->csr_estat);
>
> - if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE)
> + if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_OOB)
> pr_cont(" BADV: %0*lx\n", field, regs->csr_badvaddr);
>
> pr_cont(" PRID: %08x (%s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
> --
> 2.40.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2023-04-25 7:36 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-04-22 17:34 [PATCH v6 00/13] LoongArch: Better backtraces WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 01/13] LoongArch: Clean up the architectural interrupt definitions WANG Xuerui
2023-04-25 7:32 ` Huacai Chen
2023-04-22 17:34 ` [PATCH v6 02/13] LoongArch: Add exception subcode definitions for the watchpoint exception WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 03/13] LoongArch: Print GPRs with ABI names when showing registers WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 04/13] LoongArch: Print symbol info for CSR.ERA and $ra only for kernel-mode contexts WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 05/13] LoongArch: Fix format of CSR lines during show_regs WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 06/13] LoongArch: Humanize the CRMD line when showing registers WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 07/13] LoongArch: Humanize the PRMD " WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 08/13] LoongArch: Humanize the EUEN " WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 09/13] LoongArch: Humanize the ECFG " WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 10/13] LoongArch: Humanize the ESTAT " WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 11/13] LoongArch: Use ISA manual names for BADV and CPUCFG.PRID lines in show_regs WANG Xuerui
2023-04-22 17:34 ` [PATCH v6 12/13] LoongArch: Include CSR.BADV in show_regs in case of BCE exceptions WANG Xuerui
2023-04-25 7:36 ` Huacai Chen
2023-04-22 17:34 ` [PATCH v6 13/13] LoongArch: Also include current CPU's full name in show_regs output WANG Xuerui
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