* [PATCH V3 0/5] irqchip/loongson: Fix some loongson irqchip drivers
@ 2023-06-14 11:59 Jianmin Lv
2023-06-14 11:59 ` [PATCH V3 1/5] irqchip/loongson-pch-pic: Fix initialization of HT vector register Jianmin Lv
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Jianmin Lv @ 2023-06-14 11:59 UTC (permalink / raw
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Lorenzo Pieralisi, Jiaxun Yang,
Huacai Chen, WANG Xuerui, loongson-kernel
The patch series provide some fixes for loongson-liointc and loongson-pch-pic driver.
V1->V2:
1. Adjust commit log for all patchs
2. Add some explanation for Loongson-3's polarity register
V2->V3:
1. Add a new patch[5] to fix irq affinity setting during resume for loongson-eiointc
Jianmin Lv (3):
irqchip/loongson-pch-pic: Fix initialization of HT vector register
irqchip/loongson-liointc: Fix IRQ trigger polarity
irqchip/loongson-eiointc: Fix irq affinity setting during resume
Liu Peibao (1):
irqchip/loongson-pch-pic: Fix potential incorrect hwirq assignment
Yinbo Zhu (1):
irqchip/loongson-liointc: Add IRQCHIP_SKIP_SET_WAKE flag
drivers/irqchip/irq-loongson-eiointc.c | 2 +-
drivers/irqchip/irq-loongson-liointc.c | 13 +++++++++----
drivers/irqchip/irq-loongson-pch-pic.c | 10 ++++------
3 files changed, 14 insertions(+), 11 deletions(-)
--
2.31.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH V3 1/5] irqchip/loongson-pch-pic: Fix initialization of HT vector register
2023-06-14 11:59 [PATCH V3 0/5] irqchip/loongson: Fix some loongson irqchip drivers Jianmin Lv
@ 2023-06-14 11:59 ` Jianmin Lv
2023-06-14 11:59 ` [PATCH V3 2/5] irqchip/loongson-pch-pic: Fix potential incorrect hwirq assignment Jianmin Lv
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Jianmin Lv @ 2023-06-14 11:59 UTC (permalink / raw
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Lorenzo Pieralisi, Jiaxun Yang,
Huacai Chen, WANG Xuerui, loongson-kernel, stable, liuyun
In an ACPI-based dual-bridge system, IRQ of each bridge's
PCH PIC sent to CPU is always a zero-based number, which
means that the IRQ on PCH PIC of each bridge is mapped into
vector range from 0 to 63 of upstream irqchip(e.g. EIOINTC).
EIOINTC N: [0 ... 63 | 64 ... 255]
-------- ----------
^ ^
| |
PCH PIC N |
PCH MSI N
For example, the IRQ vector number of sata controller on
PCH PIC of each bridge is 16, which is sent to upstream
irqchip of EIOINTC when an interrupt occurs, which will set
bit 16 of EIOINTC. Since hwirq of 16 on EIOINTC has been
mapped to a irq_desc for sata controller during hierarchy
irq allocation, the related mapped IRQ will be found through
irq_resolve_mapping() in the IRQ domain of EIOINTC.
So, the IRQ number set in HT vector register should be fixed
to be a zero-based number.
Cc: stable@vger.kernel.org
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Co-developed-by: liuyun <liuyun@loongson.cn>
Signed-off-by: liuyun <liuyun@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
drivers/irqchip/irq-loongson-pch-pic.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c
index e5fe4d50be05..921c5c0190d1 100644
--- a/drivers/irqchip/irq-loongson-pch-pic.c
+++ b/drivers/irqchip/irq-loongson-pch-pic.c
@@ -401,14 +401,12 @@ static int __init acpi_cascade_irqdomain_init(void)
int __init pch_pic_acpi_init(struct irq_domain *parent,
struct acpi_madt_bio_pic *acpi_pchpic)
{
- int ret, vec_base;
+ int ret;
struct fwnode_handle *domain_handle;
if (find_pch_pic(acpi_pchpic->gsi_base) >= 0)
return 0;
- vec_base = acpi_pchpic->gsi_base - GSI_MIN_PCH_IRQ;
-
domain_handle = irq_domain_alloc_fwnode(&acpi_pchpic->address);
if (!domain_handle) {
pr_err("Unable to allocate domain handle\n");
@@ -416,7 +414,7 @@ int __init pch_pic_acpi_init(struct irq_domain *parent,
}
ret = pch_pic_init(acpi_pchpic->address, acpi_pchpic->size,
- vec_base, parent, domain_handle, acpi_pchpic->gsi_base);
+ 0, parent, domain_handle, acpi_pchpic->gsi_base);
if (ret < 0) {
irq_domain_free_fwnode(domain_handle);
--
2.31.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V3 2/5] irqchip/loongson-pch-pic: Fix potential incorrect hwirq assignment
2023-06-14 11:59 [PATCH V3 0/5] irqchip/loongson: Fix some loongson irqchip drivers Jianmin Lv
2023-06-14 11:59 ` [PATCH V3 1/5] irqchip/loongson-pch-pic: Fix initialization of HT vector register Jianmin Lv
@ 2023-06-14 11:59 ` Jianmin Lv
2023-06-14 11:59 ` [PATCH V3 3/5] irqchip/loongson-liointc: Fix IRQ trigger polarity Jianmin Lv
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Jianmin Lv @ 2023-06-14 11:59 UTC (permalink / raw
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Lorenzo Pieralisi, Jiaxun Yang,
Huacai Chen, WANG Xuerui, loongson-kernel, Liu Peibao, stable
From: Liu Peibao <liupeibao@loongson.cn>
In DeviceTree path, when ht_vec_base is not zero, the hwirq of PCH PIC
will be assigned incorrectly. Because when pch_pic_domain_translate()
adds the ht_vec_base to hwirq, the hwirq does not have the ht_vec_base
subtracted when calling irq_domain_set_info().
The ht_vec_base is designed for the parent irq chip/domain of the PCH PIC.
It seems not proper to deal this in callbacks of the PCH PIC domain and
let's put this back like the initial commit ef8c01eb64ca ("irqchip: Add
Loongson PCH PIC controller").
Fixes: bcdd75c596c8 ("irqchip/loongson-pch-pic: Add ACPI init support")
Cc: stable@vger.kernel.org
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Liu Peibao <liupeibao@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
drivers/irqchip/irq-loongson-pch-pic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c
index 921c5c0190d1..93a71f66efeb 100644
--- a/drivers/irqchip/irq-loongson-pch-pic.c
+++ b/drivers/irqchip/irq-loongson-pch-pic.c
@@ -164,7 +164,7 @@ static int pch_pic_domain_translate(struct irq_domain *d,
if (fwspec->param_count < 2)
return -EINVAL;
- *hwirq = fwspec->param[0] + priv->ht_vec_base;
+ *hwirq = fwspec->param[0];
*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
} else {
if (fwspec->param_count < 1)
@@ -196,7 +196,7 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
parent_fwspec.fwnode = domain->parent->fwnode;
parent_fwspec.param_count = 1;
- parent_fwspec.param[0] = hwirq;
+ parent_fwspec.param[0] = hwirq + priv->ht_vec_base;
err = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
if (err)
--
2.31.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V3 3/5] irqchip/loongson-liointc: Fix IRQ trigger polarity
2023-06-14 11:59 [PATCH V3 0/5] irqchip/loongson: Fix some loongson irqchip drivers Jianmin Lv
2023-06-14 11:59 ` [PATCH V3 1/5] irqchip/loongson-pch-pic: Fix initialization of HT vector register Jianmin Lv
2023-06-14 11:59 ` [PATCH V3 2/5] irqchip/loongson-pch-pic: Fix potential incorrect hwirq assignment Jianmin Lv
@ 2023-06-14 11:59 ` Jianmin Lv
2023-06-14 11:59 ` [PATCH V3 4/5] irqchip/loongson-liointc: Add IRQCHIP_SKIP_SET_WAKE flag Jianmin Lv
2023-06-14 11:59 ` [PATCH V3 5/5] irqchip/loongson-eiointc: Fix irq affinity setting during resume Jianmin Lv
4 siblings, 0 replies; 6+ messages in thread
From: Jianmin Lv @ 2023-06-14 11:59 UTC (permalink / raw
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Lorenzo Pieralisi, Jiaxun Yang,
Huacai Chen, WANG Xuerui, loongson-kernel, stable, Huacai Chen,
Chong Qiao
For the INT_POLARITY register of Loongson-2K series IRQ
controller, '0' indicates high level or rising edge triggered,
'1' indicates low level or falling edge triggered, and we
can find out the information from the Loongson 2K1000LA User
Manual v1.0, Table 9-2, Section 9.3 (中断寄存器描述 / Description
of the Interrupt Registers).
For Loongson-3 CPU series, setting INT_POLARITY register is not
supported and writting it has no effect.
So trigger polarity setting shouled be fixed for Loongson-2K CPU
series.
Fixes: 17343d0b4039 ("irqchip/loongson-liointc: Support to set IRQ type for ACPI path")
Cc: stable@vger.kernel.org
Reviewed-by: Huacai Chen <chenhuacai@kernel.org>
Co-developed-by: Chong Qiao <qiaochong@loongson.cn>
Signed-off-by: Chong Qiao <qiaochong@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
drivers/irqchip/irq-loongson-liointc.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index 8d00a9ad5b00..5dd9db8f8fa8 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -32,6 +32,10 @@
#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
+/*
+ * LIOINTC_REG_INTC_POL register is only valid for Loongson-2K series, and
+ * Loongson-3 series behave as noops.
+ */
#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
@@ -116,19 +120,19 @@ static int liointc_set_type(struct irq_data *data, unsigned int type)
switch (type) {
case IRQ_TYPE_LEVEL_HIGH:
liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
- liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
break;
case IRQ_TYPE_LEVEL_LOW:
liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
- liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
break;
case IRQ_TYPE_EDGE_RISING:
liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
- liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
break;
case IRQ_TYPE_EDGE_FALLING:
liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
- liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
break;
default:
irq_gc_unlock_irqrestore(gc, flags);
--
2.31.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V3 4/5] irqchip/loongson-liointc: Add IRQCHIP_SKIP_SET_WAKE flag
2023-06-14 11:59 [PATCH V3 0/5] irqchip/loongson: Fix some loongson irqchip drivers Jianmin Lv
` (2 preceding siblings ...)
2023-06-14 11:59 ` [PATCH V3 3/5] irqchip/loongson-liointc: Fix IRQ trigger polarity Jianmin Lv
@ 2023-06-14 11:59 ` Jianmin Lv
2023-06-14 11:59 ` [PATCH V3 5/5] irqchip/loongson-eiointc: Fix irq affinity setting during resume Jianmin Lv
4 siblings, 0 replies; 6+ messages in thread
From: Jianmin Lv @ 2023-06-14 11:59 UTC (permalink / raw
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Lorenzo Pieralisi, Jiaxun Yang,
Huacai Chen, WANG Xuerui, loongson-kernel, Yinbo Zhu, Huacai Chen
From: Yinbo Zhu <zhuyinbo@loongson.cn>
LIOINTC doesn't require specific logic to work with wakeup IRQs,
and no irq_set_wake callback is needed. To allow registered IRQs
from LIOINTC to be used as a wakeup-source, and ensure irq_set_irq_wake()
works well, the flag IRQCHIP_SKIP_SET_WAKE should be added.
Reviewed-by: Huacai Chen <chenhuacai@kernel.org>
Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
drivers/irqchip/irq-loongson-liointc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index 5dd9db8f8fa8..e4b33aed1c97 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -295,6 +295,7 @@ static int liointc_init(phys_addr_t addr, unsigned long size, int revision,
ct->chip.irq_mask = irq_gc_mask_disable_reg;
ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
ct->chip.irq_set_type = liointc_set_type;
+ ct->chip.flags = IRQCHIP_SKIP_SET_WAKE;
gc->mask_cache = 0;
priv->gc = gc;
--
2.31.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V3 5/5] irqchip/loongson-eiointc: Fix irq affinity setting during resume
2023-06-14 11:59 [PATCH V3 0/5] irqchip/loongson: Fix some loongson irqchip drivers Jianmin Lv
` (3 preceding siblings ...)
2023-06-14 11:59 ` [PATCH V3 4/5] irqchip/loongson-liointc: Add IRQCHIP_SKIP_SET_WAKE flag Jianmin Lv
@ 2023-06-14 11:59 ` Jianmin Lv
4 siblings, 0 replies; 6+ messages in thread
From: Jianmin Lv @ 2023-06-14 11:59 UTC (permalink / raw
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Lorenzo Pieralisi, Jiaxun Yang,
Huacai Chen, WANG Xuerui, loongson-kernel, yangqiming
The hierarchy of PCH PIC, PCH PCI MSI and EIONTC is as following:
PCH PIC ------->|
|---->EIOINTC
PCH PCI MSI --->|
so the irq_data list of irq_desc for IRQs on PCH PIC and PCH PCI MSI
is like this:
irq_desc->irq_data(domain: PCH PIC)->parent_data(domain: EIOINTC)
irq_desc->irq_data(domain: PCH PCI MSI)->parent_data(domain: EIOINTC)
In eiointc_resume(), the irq_data passed into eiointc_set_irq_affinity()
should be matched to EIOINTC domain instead of PCH PIC or PCH PCI MSI
domain, so fix it.
Fixes: a90335c2dfb4 ("irqchip/loongson-eiointc: Add suspend/resume support")
Reported-by: yangqiming <yangqiming@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
drivers/irqchip/irq-loongson-eiointc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-loongson-eiointc.c
index 71ef19f77a5a..a7fcde3e3ecc 100644
--- a/drivers/irqchip/irq-loongson-eiointc.c
+++ b/drivers/irqchip/irq-loongson-eiointc.c
@@ -314,7 +314,7 @@ static void eiointc_resume(void)
desc = irq_resolve_mapping(eiointc_priv[i]->eiointc_domain, j);
if (desc && desc->handle_irq && desc->handle_irq != handle_bad_irq) {
raw_spin_lock(&desc->lock);
- irq_data = &desc->irq_data;
+ irq_data = irq_domain_get_irq_data(eiointc_priv[i]->eiointc_domain, irq_desc_get_irq(desc));
eiointc_set_irq_affinity(irq_data, irq_data->common->affinity, 0);
raw_spin_unlock(&desc->lock);
}
--
2.31.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-06-14 11:59 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-06-14 11:59 [PATCH V3 0/5] irqchip/loongson: Fix some loongson irqchip drivers Jianmin Lv
2023-06-14 11:59 ` [PATCH V3 1/5] irqchip/loongson-pch-pic: Fix initialization of HT vector register Jianmin Lv
2023-06-14 11:59 ` [PATCH V3 2/5] irqchip/loongson-pch-pic: Fix potential incorrect hwirq assignment Jianmin Lv
2023-06-14 11:59 ` [PATCH V3 3/5] irqchip/loongson-liointc: Fix IRQ trigger polarity Jianmin Lv
2023-06-14 11:59 ` [PATCH V3 4/5] irqchip/loongson-liointc: Add IRQCHIP_SKIP_SET_WAKE flag Jianmin Lv
2023-06-14 11:59 ` [PATCH V3 5/5] irqchip/loongson-eiointc: Fix irq affinity setting during resume Jianmin Lv
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