From: Jinjie Ruan <ruanjinjie@huawei.com>
To: <catalin.marinas@arm.com>, <will@kernel.org>,
<chenhuacai@kernel.org>, <kernel@xen0n.name>, <hca@linux.ibm.com>,
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Subject: [PATCH v14 3/4] arm64: Use generic TIF bits for common thread flags
Date: Fri, 20 Mar 2026 18:42:21 +0800 [thread overview]
Message-ID: <20260320104222.1381274-4-ruanjinjie@huawei.com> (raw)
In-Reply-To: <20260320104222.1381274-1-ruanjinjie@huawei.com>
Use the generic TIF bits defined in <asm-generic/thread_info_tif.h> for
standard thread flags (TIF_SIGPENDING, TIF_NEED_RESCHED, TIF_NOTIFY_RESUME,
TIF_RESTORE_SIGMASK, TIF_SINGLESTEP, etc.) instead of defining
them locally.
Arm64-specific bits (TIF_FOREIGN_FPSTATE, TIF_MTE_ASYNC_FAULT, TIF_SVE,
TIF_SSBD, etc.) are renumbered to start at bit 16 to avoid conflicts.
This enables RSEQ optimizations which require CONFIG_HAVE_GENERIC_TIF_BITS
combined with the generic entry infrastructure (already used by arm64).
By the way, remove TIF_FREEZE because this flag became unused since
commit d88e4cb67197 ("freezer: remove now unused TIF_FREEZE").
Cc: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Kevin Brodsky <kevin.brodsky@arm.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Reviewed-by: Yeoreum Yun <yeoreum.yun@arm.com>
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
---
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/thread_info.h | 61 ++++++++++++----------------
2 files changed, 27 insertions(+), 35 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 96fef01598be..33cf901fb1a0 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -224,6 +224,7 @@ config ARM64
select HAVE_SAMPLE_FTRACE_DIRECT_MULTI
select HAVE_BUILDTIME_MCOUNT_SORT
select HAVE_EFFICIENT_UNALIGNED_ACCESS
+ select HAVE_GENERIC_TIF_BITS
select HAVE_GUP_FAST
select HAVE_FTRACE_GRAPH_FUNC
select HAVE_FUNCTION_TRACER
diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h
index f89a15dc6ad5..57c37b05b961 100644
--- a/arch/arm64/include/asm/thread_info.h
+++ b/arch/arm64/include/asm/thread_info.h
@@ -58,42 +58,33 @@ void arch_setup_new_exec(void);
#endif
-#define TIF_SIGPENDING 0 /* signal pending */
-#define TIF_NEED_RESCHED 1 /* rescheduling necessary */
-#define TIF_NEED_RESCHED_LAZY 2 /* Lazy rescheduling needed */
-#define TIF_NOTIFY_RESUME 3 /* callback before returning to user */
-#define TIF_FOREIGN_FPSTATE 4 /* CPU's FP state is not current's */
-#define TIF_UPROBE 5 /* uprobe breakpoint or singlestep */
-#define TIF_MTE_ASYNC_FAULT 6 /* MTE Asynchronous Tag Check Fault */
-#define TIF_NOTIFY_SIGNAL 7 /* signal notifications exist */
-#define TIF_PATCH_PENDING 13 /* pending live patching update */
-#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
-#define TIF_FREEZE 19
-#define TIF_RESTORE_SIGMASK 20
-#define TIF_SINGLESTEP 21
-#define TIF_32BIT 22 /* 32bit process */
-#define TIF_SVE 23 /* Scalable Vector Extension in use */
-#define TIF_SVE_VL_INHERIT 24 /* Inherit SVE vl_onexec across exec */
-#define TIF_SSBD 25 /* Wants SSB mitigation */
-#define TIF_TAGGED_ADDR 26 /* Allow tagged user addresses */
-#define TIF_SME 27 /* SME in use */
-#define TIF_SME_VL_INHERIT 28 /* Inherit SME vl_onexec across exec */
-#define TIF_KERNEL_FPSTATE 29 /* Task is in a kernel mode FPSIMD section */
-#define TIF_TSC_SIGSEGV 30 /* SIGSEGV on counter-timer access */
-#define TIF_LAZY_MMU_PENDING 31 /* Ops pending for lazy mmu mode exit */
+/*
+ * Tell the generic TIF infrastructure which bits arm64 supports
+ */
+#define HAVE_TIF_NEED_RESCHED_LAZY
+#define HAVE_TIF_RESTORE_SIGMASK
+#define HAVE_TIF_SINGLESTEP
+
+#include <asm-generic/thread_info_tif.h>
+
+#define TIF_FOREIGN_FPSTATE 16 /* CPU's FP state is not current's */
+#define TIF_MTE_ASYNC_FAULT 17 /* MTE Asynchronous Tag Check Fault */
+#define TIF_32BIT 18 /* 32bit process */
+#define TIF_SVE 19 /* Scalable Vector Extension in use */
+#define TIF_SVE_VL_INHERIT 20 /* Inherit SVE vl_onexec across exec */
+#define TIF_SSBD 21 /* Wants SSB mitigation */
+#define TIF_TAGGED_ADDR 22 /* Allow tagged user addresses */
+#define TIF_SME 23 /* SME in use */
+#define TIF_SME_VL_INHERIT 24 /* Inherit SME vl_onexec across exec */
+#define TIF_KERNEL_FPSTATE 25 /* Task is in a kernel mode FPSIMD section */
+#define TIF_TSC_SIGSEGV 26 /* SIGSEGV on counter-timer access */
+#define TIF_LAZY_MMU_PENDING 27 /* Ops pending for lazy mmu mode exit */
-#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
-#define _TIF_NEED_RESCHED_LAZY (1 << TIF_NEED_RESCHED_LAZY)
-#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
-#define _TIF_FOREIGN_FPSTATE (1 << TIF_FOREIGN_FPSTATE)
-#define _TIF_PATCH_PENDING (1 << TIF_PATCH_PENDING)
-#define _TIF_UPROBE (1 << TIF_UPROBE)
-#define _TIF_32BIT (1 << TIF_32BIT)
-#define _TIF_SVE (1 << TIF_SVE)
-#define _TIF_MTE_ASYNC_FAULT (1 << TIF_MTE_ASYNC_FAULT)
-#define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL)
-#define _TIF_TSC_SIGSEGV (1 << TIF_TSC_SIGSEGV)
+#define _TIF_FOREIGN_FPSTATE BIT(TIF_FOREIGN_FPSTATE)
+#define _TIF_32BIT BIT(TIF_32BIT)
+#define _TIF_SVE BIT(TIF_SVE)
+#define _TIF_MTE_ASYNC_FAULT BIT(TIF_MTE_ASYNC_FAULT)
+#define _TIF_TSC_SIGSEGV BIT(TIF_TSC_SIGSEGV)
#ifdef CONFIG_SHADOW_CALL_STACK
#define INIT_SCS \
--
2.34.1
next prev parent reply other threads:[~2026-03-20 10:41 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-20 10:42 [PATCH v14 0/4] arm64: Use generic TIF bits for common thread flags Jinjie Ruan
2026-03-20 10:42 ` [PATCH v14 1/4] s390: Rename TIF_SINGLE_STEP to TIF_SINGLESTEP Jinjie Ruan
2026-03-20 10:42 ` [PATCH v14 2/4] asm-generic: Move TIF_SINGLESTEP to generic TIF bits Jinjie Ruan
2026-04-09 7:42 ` Mark Rutland
2026-04-10 3:39 ` Jinjie Ruan
2026-03-20 10:42 ` Jinjie Ruan [this message]
2026-04-01 10:55 ` [PATCH v14 3/4] arm64: Use generic TIF bits for common thread flags Catalin Marinas
2026-04-02 1:41 ` Jinjie Ruan
2026-03-20 10:42 ` [PATCH v14 4/4] selftests: sud_test: Support aarch64 Jinjie Ruan
2026-03-20 13:40 ` Linus Walleij
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