From: Tiezhu Yang <yangtiezhu@loongson.cn>
To: Huacai Chen <chenhuacai@kernel.org>, Hengqi Chen <hengqi.chen@gmail.com>
Cc: loongarch@lists.linux.dev, bpf@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v3 4/5] LoongArch: BPF: Support load-acquire and store-release instructions
Date: Mon, 13 Apr 2026 12:05:05 +0800 [thread overview]
Message-ID: <20260413040506.26640-5-yangtiezhu@loongson.cn> (raw)
In-Reply-To: <20260413040506.26640-1-yangtiezhu@loongson.cn>
Use the LoongArch common memory access instructions with the barrier dbar
to support the BPF load-acquire and store-release instructions.
With this patch, the following testcases passed on LoongArch if the macro
CAN_USE_LOAD_ACQ_STORE_REL is usable in bpf selftests:
sudo ./test_progs -t verifier_load_acquire
sudo ./test_progs -t verifier_store_release
sudo ./test_progs -t verifier_precision/bpf_load_acquire
sudo ./test_progs -t verifier_precision/bpf_store_release
sudo ./test_progs -t compute_live_registers/atomic_load_acq_store_rel
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
---
arch/loongarch/net/bpf_jit.c | 98 +++++++++++++++++++++++++++++++++++-
1 file changed, 97 insertions(+), 1 deletion(-)
diff --git a/arch/loongarch/net/bpf_jit.c b/arch/loongarch/net/bpf_jit.c
index c9a32f124f5e..805f95cbe798 100644
--- a/arch/loongarch/net/bpf_jit.c
+++ b/arch/loongarch/net/bpf_jit.c
@@ -344,6 +344,99 @@ static int emit_bpf_tail_call(struct jit_ctx *ctx, int insn)
#undef jmp_offset
}
+static int emit_atomic_ld_st(const struct bpf_insn *insn, struct jit_ctx *ctx)
+{
+ const u8 t1 = LOONGARCH_GPR_T1;
+ const u8 src = regmap[insn->src_reg];
+ const u8 dst = regmap[insn->dst_reg];
+ const s16 off = insn->off;
+ const s32 imm = insn->imm;
+
+ switch (imm) {
+ /* dst_reg = load_acquire(src_reg + off16) */
+ case BPF_LOAD_ACQ:
+ switch (BPF_SIZE(insn->code)) {
+ case BPF_B:
+ if (is_signed_imm12(off)) {
+ emit_insn(ctx, ldbu, dst, src, off);
+ } else {
+ move_imm(ctx, t1, off, false);
+ emit_insn(ctx, ldxbu, dst, src, t1);
+ }
+ break;
+ case BPF_H:
+ if (is_signed_imm12(off)) {
+ emit_insn(ctx, ldhu, dst, src, off);
+ } else {
+ move_imm(ctx, t1, off, false);
+ emit_insn(ctx, ldxhu, dst, src, t1);
+ }
+ break;
+ case BPF_W:
+ if (is_signed_imm12(off)) {
+ emit_insn(ctx, ldwu, dst, src, off);
+ } else {
+ move_imm(ctx, t1, off, false);
+ emit_insn(ctx, ldxwu, dst, src, t1);
+ }
+ break;
+ case BPF_DW:
+ if (is_signed_imm12(off)) {
+ emit_insn(ctx, ldd, dst, src, off);
+ } else {
+ move_imm(ctx, t1, off, false);
+ emit_insn(ctx, ldxd, dst, src, t1);
+ }
+ break;
+ }
+ emit_insn(ctx, dbar, 0b10100);
+ break;
+ /* store_release(dst_reg + off16, src_reg) */
+ case BPF_STORE_REL:
+ emit_insn(ctx, dbar, 0b10010);
+ switch (BPF_SIZE(insn->code)) {
+ case BPF_B:
+ if (is_signed_imm12(off)) {
+ emit_insn(ctx, stb, src, dst, off);
+ } else {
+ move_imm(ctx, t1, off, false);
+ emit_insn(ctx, stxb, src, dst, t1);
+ }
+ break;
+ case BPF_H:
+ if (is_signed_imm12(off)) {
+ emit_insn(ctx, sth, src, dst, off);
+ } else {
+ move_imm(ctx, t1, off, false);
+ emit_insn(ctx, stxh, src, dst, t1);
+ }
+ break;
+ case BPF_W:
+ if (is_signed_imm12(off)) {
+ emit_insn(ctx, stw, src, dst, off);
+ } else {
+ move_imm(ctx, t1, off, false);
+ emit_insn(ctx, stxw, src, dst, t1);
+ }
+ break;
+ case BPF_DW:
+ if (is_signed_imm12(off)) {
+ emit_insn(ctx, std, src, dst, off);
+ } else {
+ move_imm(ctx, t1, off, false);
+ emit_insn(ctx, stxd, src, dst, t1);
+ }
+ break;
+ }
+ break;
+ default:
+ pr_err_once("bpf-jit: invalid atomic load/store opcode %02x\n", imm);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int emit_atomic_rmw(const struct bpf_insn *insn, struct jit_ctx *ctx)
{
const u8 t1 = LOONGARCH_GPR_T1;
@@ -1326,7 +1419,10 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, bool ext
case BPF_STX | BPF_ATOMIC | BPF_H:
case BPF_STX | BPF_ATOMIC | BPF_W:
case BPF_STX | BPF_ATOMIC | BPF_DW:
- ret = emit_atomic_rmw(insn, ctx);
+ if (bpf_atomic_is_load_store(insn))
+ ret = emit_atomic_ld_st(insn, ctx);
+ else
+ ret = emit_atomic_rmw(insn, ctx);
if (ret)
return ret;
break;
--
2.42.0
next prev parent reply other threads:[~2026-04-13 4:05 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-13 4:05 [PATCH v3 0/5] LoongArch: BPF: Support more atomic instructions Tiezhu Yang
2026-04-13 4:05 ` [PATCH v3 1/5] LoongArch: Define instruction formats for AM{SWAP/ADD}.{B/H} and DBAR Tiezhu Yang
2026-04-15 2:24 ` Hengqi Chen
2026-04-13 4:05 ` [PATCH v3 2/5] LoongArch: BPF: Add the default case in emit_atomic() and rename it Tiezhu Yang
2026-04-15 2:24 ` Hengqi Chen
2026-04-13 4:05 ` [PATCH v3 3/5] LoongArch: BPF: Support 8 and 16 bit read-modify-write instructions Tiezhu Yang
2026-04-13 4:49 ` bot+bpf-ci
2026-04-13 8:05 ` WANG Rui
2026-04-13 4:05 ` Tiezhu Yang [this message]
2026-04-15 2:25 ` [PATCH v3 4/5] LoongArch: BPF: Support load-acquire and store-release instructions Hengqi Chen
2026-04-13 4:05 ` [PATCH v3 5/5] selftests/bpf: Make CAN_USE_LOAD_ACQ_STORE_REL usable for LoongArch Tiezhu Yang
2026-04-15 2:27 ` Hengqi Chen
2026-04-21 12:38 ` [PATCH v3 0/5] LoongArch: BPF: Support more atomic instructions Huacai Chen
2026-04-21 13:25 ` Tiezhu Yang
2026-04-21 13:46 ` Tiezhu Yang
2026-04-22 8:15 ` Huacai Chen
2026-04-23 2:56 ` Tiezhu Yang
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