From: Bibo Mao <maobibo@loongson.cn>
To: Huacai Chen <chenhuacai@kernel.org>
Cc: kernel@xen0n.name, kvm@vger.kernel.org,
loongarch@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: [PATCH v3 5/6] LoongArch: KVM: Add valid bit check when set ESTAT CSR register
Date: Tue, 19 May 2026 17:43:07 +0800 [thread overview]
Message-ID: <20260519094308.3983046-6-maobibo@loongson.cn> (raw)
In-Reply-To: <20260519094308.3983046-1-maobibo@loongson.cn>
When set ESTAT CSR register in function _kvm_setcsr(), valid bit check
is added here. Also interrupt CPU_AVEC is checked by msgint feature.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
arch/loongarch/kvm/vcpu.c | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c
index c6bcad1dd9e2..8864e55c33ac 100644
--- a/arch/loongarch/kvm/vcpu.c
+++ b/arch/loongarch/kvm/vcpu.c
@@ -602,7 +602,7 @@ struct kvm_vcpu *kvm_get_vcpu_by_cpuid(struct kvm *kvm, int cpuid)
static int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 *val)
{
- unsigned long gintc;
+ unsigned long gintc, estat;
struct loongarch_csrs *csr = vcpu->arch.csr;
if (get_gcsr_flag(id) & INVALID_GCSR)
@@ -621,8 +621,9 @@ static int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 *val)
preempt_enable();
/* ESTAT IP0~IP7 get from GINTC */
- gintc = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC) & 0xff;
- *val = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT) | (gintc << 2);
+ gintc = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC) & KVM_GINTC_IRQ_MASK;
+ estat = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT) & ~KVM_ESTAT_HWI_MASK;
+ *val = estat | (gintc << 2);
return 0;
}
@@ -637,7 +638,8 @@ static int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 *val)
static int _kvm_setcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 val)
{
- int ret = 0, gintc;
+ int ret = 0;
+ unsigned long gintc, estat;
struct loongarch_csrs *csr = vcpu->arch.csr;
if (get_gcsr_flag(id) & INVALID_GCSR)
@@ -648,11 +650,15 @@ static int _kvm_setcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 val)
if (id == LOONGARCH_CSR_ESTAT) {
/* ESTAT IP0~IP7 inject through GINTC */
- gintc = (val >> 2) & 0xff;
+ gintc = (val >> 2) & KVM_GINTC_IRQ_MASK;
kvm_set_sw_gcsr(csr, LOONGARCH_CSR_GINTC, gintc);
- gintc = val & ~(0xffUL << 2);
- kvm_set_sw_gcsr(csr, LOONGARCH_CSR_ESTAT, gintc);
+ /* only set valid ESTAT bits */
+ estat = val & ~KVM_ESTAT_HWI_MASK;
+ estat &= CSR_ESTAT_IS | CSR_ESTAT_EXC | CSR_ESTAT_ESUBCODE;
+ if (!kvm_guest_has_msgint(&vcpu->arch))
+ estat &= ~CPU_AVEC;
+ kvm_set_sw_gcsr(csr, LOONGARCH_CSR_ESTAT, estat);
return ret;
}
--
2.39.3
next prev parent reply other threads:[~2026-05-19 9:43 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-19 9:43 [PATCH v3 0/6] LoongArch: KVM: Small enhancement about interrupt injection Bibo Mao
2026-05-19 9:43 ` [PATCH v3 1/6] LoongArch: KVM: Check irq validility in kvm_vcpu_ioctl_interrupt() Bibo Mao
2026-05-19 12:57 ` Bibo Mao
2026-05-19 9:43 ` [PATCH v3 2/6] LoongArch: KVM: Check msgint feature in interrupt post Bibo Mao
2026-05-19 9:43 ` [PATCH v3 3/6] LoongArch: KVM: Use existing macro about interrupt bit mask Bibo Mao
2026-05-19 9:43 ` [PATCH v3 4/6] LoongArch: KVM: Inject interrupt with batch method Bibo Mao
2026-05-19 9:43 ` Bibo Mao [this message]
2026-05-19 9:43 ` [PATCH v3 6/6] LoongArch: KVM: Simple interrupt status acquire interface Bibo Mao
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