From: "Jiaxun Yang" <jiaxun.yang@flygoat.com>
To: "Icenowy Zheng" <zhengxingda@iscas.ac.cn>,
"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>
Cc: "Icenowy Zheng" <uwu@icenowy.me>, "Yao Zi" <me@ziyao.cc>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
loongarch@lists.linux.dev,
"linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
"Xuerui Wang" <kernel@xen0n.name>,
"Thomas Gleixner" <tglx@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Huacai Chen" <chenhuacai@kernel.org>
Subject: Re: [PATCH v4 1/6] MIPS: loongson64: Override arch_dynirq_lower_bound to reserve LPC IRQs
Date: Thu, 26 Mar 2026 21:40:09 +0000 [thread overview]
Message-ID: <a8cb7352-2d1e-46e9-b526-de4d4dd7b460@app.fastmail.com> (raw)
In-Reply-To: <20260321092032.3502701-2-zhengxingda@iscas.ac.cn>
On Sat, 21 Mar 2026, at 9:20 AM, Icenowy Zheng wrote:
> On some Loongson 3A devices, a LPC bus is present and some legacy
> devices (e.g. 8259) on it expect hardcoded low interrupt numbers. However
> currently the expected low range interrupt numbers are not exempted from
> the dynamic allocation, which leads to confliction when registering LPC
> interrupts in the fixed range.
>
> Override arch_dynirq_lower_bound() to reserve these low range interrupt
> numbers and prevent them from being dynamically allocated.
>
> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Acked-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
@Thomas Bogendoerfer, do you mind picking this over MIPS tree?
Thanks
Jiaxun
> ---
> arch/mips/loongson64/init.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c
> index 5f73f8663ab2d..c7cc5a3d7817f 100644
> --- a/arch/mips/loongson64/init.c
> +++ b/arch/mips/loongson64/init.c
> @@ -7,6 +7,7 @@
> #include <linux/irqchip.h>
> #include <linux/logic_pio.h>
> #include <linux/memblock.h>
> +#include <linux/minmax.h>
> #include <linux/of.h>
> #include <linux/of_address.h>
> #include <asm/bootinfo.h>
> @@ -227,3 +228,8 @@ void __init arch_init_irq(void)
> reserve_pio_range();
> irqchip_init();
> }
> +
> +unsigned int arch_dynirq_lower_bound(unsigned int from)
> +{
> + return MAX(from, NR_IRQS_LEGACY);
> +}
> --
> 2.52.0
--
- Jiaxun
next prev parent reply other threads:[~2026-03-26 21:40 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-21 9:20 [PATCH v4 0/6] Add support for LS7A LPC IRQ for MIPS Loongson systems Icenowy Zheng
2026-03-21 9:20 ` [PATCH v4 1/6] MIPS: loongson64: Override arch_dynirq_lower_bound to reserve LPC IRQs Icenowy Zheng
2026-03-26 21:40 ` Jiaxun Yang [this message]
2026-03-26 22:46 ` Thomas Bogendoerfer
2026-03-21 9:20 ` [PATCH v4 2/6] LoongArch: " Icenowy Zheng
2026-03-21 9:20 ` [PATCH v4 3/6] dt-bindings: interrupt-controller: add LS7A PCH LPC Icenowy Zheng
2026-03-21 11:45 ` Jiaxun Yang
2026-03-25 16:56 ` Rob Herring (Arm)
2026-03-21 9:20 ` [PATCH v4 4/6] irqchip/loongson-pch-lpc: Extract non-ACPI-related code from ACPI init Icenowy Zheng
2026-03-21 9:20 ` [PATCH v4 5/6] irqchip/loongson-pch-lpc: Add OF init code Icenowy Zheng
2026-03-21 9:20 ` [PATCH v4 6/6] irqchip/loongson-pch-lpc: Enable building on MIPS Loongson64 Icenowy Zheng
2026-03-21 11:46 ` Jiaxun Yang
2026-03-21 12:10 ` [PATCH v4 0/6] Add support for LS7A LPC IRQ for MIPS Loongson systems Huacai Chen
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