From: Tiezhu Yang <yangtiezhu@loongson.cn>
To: bot+bpf-ci@kernel.org, loongarch@lists.linux.dev, bpf@vger.kernel.org
Cc: ast@kernel.org, andrii@kernel.org, daniel@iogearbox.net,
martin.lau@kernel.org, eddyz87@gmail.com,
yonghong.song@linux.dev, clm@meta.com, ihor.solodrai@linux.dev,
WANG Rui <wangrui@loongson.cn>
Subject: Re: [RFC PATCH 6/7] LoongArch: BPF: Add load-acquire and store-release instructions
Date: Tue, 24 Mar 2026 21:10:51 +0800 [thread overview]
Message-ID: <bbb797cd-c6ea-f61c-d99c-66908e4e5f68@loongson.cn> (raw)
In-Reply-To: <5a2cfd2c3dddef83de46ea9b0f02bb5b90c29937c9b9d348542838fde1e29a93@mail.kernel.org>
On 2026/3/24 下午5:42, bot+bpf-ci@kernel.org wrote:
>> diff --git a/arch/loongarch/net/bpf_jit.c b/arch/loongarch/net/bpf_jit.c
>> index c9a32f124f5e..d1e9866911dd 100644
>> --- a/arch/loongarch/net/bpf_jit.c
>> +++ b/arch/loongarch/net/bpf_jit.c
>
> [ ... ]
>
>> + /* store_release(dst_reg + off16, src_reg) */
>> + case BPF_STORE_REL:
>> + switch (BPF_SIZE(insn->code)) {
>
> [ ... ]
>
>> + case BPF_W:
>> + if (cpu_has_llacq_screl) {
>> + move_imm(ctx, t1, off, false);
>> + emit_insn(ctx, addd, t2, dst, t1);
>> + emit_insn(ctx, screlw, src, t2);
>
> SCREL.W is a store-conditional instruction, not a plain store-release.
> It checks LLbit and then overwrites rd with the success indicator
> (1 or 0), which would clobber the BPF source register.
>
> Looking at emit_atomic_rmw() in the same file for BPF_CMPXCHG, the
> existing LL/SC usage carefully avoids this:
>
> move_reg(ctx, t3, src);
> emit_insn(ctx, scw, t3, t1, 0);
> emit_insn(ctx, beq, t3, LOONGARCH_GPR_ZERO, -6);
>
> Here SC.W is applied to the temp register t3 rather than the BPF
> register, and t3 is then checked for 0 to retry the loop. This
> confirms that SC-family instructions clobber their rd operand on
> LoongArch.
>
> Is SCREL.W/D the right instruction for a standalone store-release?
> The other architectures use plain stores with ordering guarantees
> for BPF_STORE_REL:
Indeed, I misunderstood the instructions before, thanks Wang Rui and
bot+bpf-ci. I did some changes locally and tested again, the related
testcases passed.
I will use the common memory access instruction with the barrier dbar
to support load-acquire and store-release in the next version.
Thanks,
Tiezhu
next prev parent reply other threads:[~2026-03-24 13:10 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-24 9:00 [RFC PATCH 0/7] LoongArch: BPF: Support more atomic instructions Tiezhu Yang
2026-03-24 9:01 ` [RFC PATCH 1/7] LoongArch: Add some code related with AM{SWAP/ADD}.{B/H} Tiezhu Yang
2026-03-24 9:01 ` [RFC PATCH 2/7] LoongArch: Add some code related with {LLACQ/SCREL}.{W/D} Tiezhu Yang
2026-03-24 9:01 ` [RFC PATCH 3/7] LoongArch: BPF: Rename emit_atomic() to emit_atomic_rmw() Tiezhu Yang
2026-03-24 9:01 ` [RFC PATCH 4/7] LoongArch: BPF: Add the default case in emit_atomic_rmw() Tiezhu Yang
2026-03-24 9:01 ` [RFC PATCH 5/7] LoongArch: BPF: Add {8,16}-bit read-modify-write instructions Tiezhu Yang
2026-03-24 9:01 ` [RFC PATCH 6/7] LoongArch: BPF: Add load-acquire and store-release instructions Tiezhu Yang
2026-03-24 9:33 ` WANG Rui
2026-03-24 9:42 ` bot+bpf-ci
2026-03-24 13:10 ` Tiezhu Yang [this message]
2026-03-24 9:01 ` [RFC PATCH 7/7] selftests/bpf: Enable CAN_USE_LOAD_ACQ_STORE_REL for LoongArch Tiezhu Yang
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