From: Jon Mason <jdmason@kudzu.us>
To: Dave Jiang <dave.jiang@intel.com>
Cc: allenbh@gmail.com, ntb@lists.linux.dev
Subject: Re: [PATCH] ntb: intel: add GNR support for Intel PCIe gen5 NTB
Date: Fri, 12 Aug 2022 10:14:38 -0400 [thread overview]
Message-ID: <YvZgTmDTm+e6lIxK@kudzu.us> (raw)
In-Reply-To: <165765900595.1786187.5476611141315542956.stgit@djiang5-desk3.ch.intel.com>
On Tue, Jul 12, 2022 at 01:50:06PM -0700, Dave Jiang wrote:
> Add Intel Granite Rapids NTB PCI device ID and related enabling.
> Expectation is same hardware interface as Saphire Rapids Xeon platforms.
>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Sorry for the extremely long delay in response. This series is in my
ntb branch and will be in my pull request for v5.20 which should be
going out later today.
Thanks,
Jon
> ---
> drivers/ntb/hw/intel/ntb_hw_gen1.c | 4 +++-
> drivers/ntb/hw/intel/ntb_hw_gen4.c | 2 +-
> drivers/ntb/hw/intel/ntb_hw_intel.h | 9 +++++++++
> 3 files changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/ntb/hw/intel/ntb_hw_gen1.c b/drivers/ntb/hw/intel/ntb_hw_gen1.c
> index e5f14e20a9ff..72e2027a71c4 100644
> --- a/drivers/ntb/hw/intel/ntb_hw_gen1.c
> +++ b/drivers/ntb/hw/intel/ntb_hw_gen1.c
> @@ -1874,7 +1874,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
> rc = gen3_init_dev(ndev);
> if (rc)
> goto err_init_dev;
> - } else if (pdev_is_gen4(pdev)) {
> + } else if (pdev_is_gen4(pdev) || pdev_is_gen5(pdev)) {
> ndev->ntb.ops = &intel_ntb4_ops;
> rc = intel_ntb_init_pci(ndev, pdev);
> if (rc)
> @@ -2047,6 +2047,8 @@ static const struct pci_device_id intel_ntb_pci_tbl[] = {
>
> /* GEN4 */
> {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)},
> + /* SPR has same dev id has ICX but different revision id */
> + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_GNR)},
> {0}
> };
> MODULE_DEVICE_TABLE(pci, intel_ntb_pci_tbl);
> diff --git a/drivers/ntb/hw/intel/ntb_hw_gen4.c b/drivers/ntb/hw/intel/ntb_hw_gen4.c
> index 4081fc538ff4..22cac7975b3c 100644
> --- a/drivers/ntb/hw/intel/ntb_hw_gen4.c
> +++ b/drivers/ntb/hw/intel/ntb_hw_gen4.c
> @@ -197,7 +197,7 @@ int gen4_init_dev(struct intel_ntb_dev *ndev)
> ppd1 = ioread32(ndev->self_mmio + GEN4_PPD1_OFFSET);
> if (pdev_is_ICX(pdev))
> ndev->ntb.topo = gen4_ppd_topo(ndev, ppd1);
> - else if (pdev_is_SPR(pdev))
> + else if (pdev_is_SPR(pdev) || pdev_is_gen5(pdev))
> ndev->ntb.topo = spr_ppd_topo(ndev, ppd1);
> dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd1,
> ntb_topo_string(ndev->ntb.topo));
> diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.h b/drivers/ntb/hw/intel/ntb_hw_intel.h
> index b233d1c6ba2d..380ec0d8e0d9 100644
> --- a/drivers/ntb/hw/intel/ntb_hw_intel.h
> +++ b/drivers/ntb/hw/intel/ntb_hw_intel.h
> @@ -70,6 +70,8 @@
> #define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F
> #define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C
> #define PCI_DEVICE_ID_INTEL_NTB_B2B_ICX 0x347e
> +#define PCI_DEVICE_ID_INTEL_NTB_B2B_SPR 0x347e
> +#define PCI_DEVICE_ID_INTEL_NTB_B2B_GNR 0x0db4
>
> /* Ntb control and link status */
> #define NTB_CTL_CFG_LOCK BIT(0)
> @@ -225,7 +227,14 @@ static inline int pdev_is_gen4(struct pci_dev *pdev)
> {
> if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)
> return 1;
> + return 0;
> +}
>
> +static inline int pdev_is_gen5(struct pci_dev *pdev)
> +{
> + if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_GNR)
> + return 1;
> return 0;
> }
> +
> #endif
>
>
prev parent reply other threads:[~2022-08-12 14:14 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-12 20:50 [PATCH] ntb: intel: add GNR support for Intel PCIe gen5 NTB Dave Jiang
2022-08-12 14:14 ` Jon Mason [this message]
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