messages from 2017-06-30 13:45:10 to 2017-10-29 23:11:23 UTC [more...]
[OpenRISC] [PATCH v4 01/13] openrisc: use shadow registers to save regs on exception
2017-10-29 23:11 UTC (12+ messages)
` [OpenRISC] [PATCH v4 02/13] openrisc: add 1 and 2 byte cmpxchg support
` [OpenRISC] [PATCH v4 03/13] openrisc: use qspinlocks and qrwlocks
` [OpenRISC] [PATCH v4 05/13] irqchip: add initial support for ompic
` [OpenRISC] [PATCH v4 06/13] openrisc: initial SMP support
` [OpenRISC] [PATCH v4 07/13] openrisc: fix initial preempt state for secondary cpu tasks
` [OpenRISC] [PATCH v4 08/13] openrisc: sleep instead of spin on secondary wait
` [OpenRISC] [PATCH v4 09/13] openrisc: add cacheflush support to fix icache aliasing
` [OpenRISC] [PATCH v4 10/13] openrisc: add simple_smp dts and defconfig for simulators
` [OpenRISC] [PATCH v4 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT
` [OpenRISC] [PATCH v4 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing
` [OpenRISC] [PATCH v4 13/13] openrisc: add tick timer multi-core sync logic
[OpenRISC] [PATCH 0/3] OpenRISC doc updates
2017-10-29 11:33 UTC (6+ messages)
` [OpenRISC] [PATCH 1/3] Documentation: Move OpenRISC docs out of arch/
` [OpenRISC] [PATCH 2/3] Documentation: openrisc: Updates to README
` [OpenRISC] [PATCH 3/3] openrisc: dts: Add OpenRISC platform SoC
[OpenRISC] [PATCH v3 00/13] OpenRISC SMP Support
2017-10-27 3:19 UTC (17+ messages)
` [OpenRISC] [PATCH v3 01/13] openrisc: use shadow registers to save regs on exception
` [OpenRISC] [PATCH v3 02/13] openrisc: add 1 and 2 byte cmpxchg support
` [OpenRISC] [PATCH v3 03/13] openrisc: use qspinlocks and qrwlocks
` [OpenRISC] [PATCH v3 04/13] dt-bindings: add openrisc to vendor prefixes list
` [OpenRISC] [PATCH v3 05/13] irqchip: add initial support for ompic
` [OpenRISC] [PATCH v3 06/13] openrisc: initial SMP support
` [OpenRISC] [PATCH v3 07/13] openrisc: fix initial preempt state for secondary cpu tasks
` [OpenRISC] [PATCH v3 08/13] openrisc: sleep instead of spin on secondary wait
` [OpenRISC] [PATCH v3 09/13] openrisc: add cacheflush support to fix icache aliasing
` [OpenRISC] [PATCH v3 10/13] openrisc: add simple_smp dts and defconfig for simulators
` [OpenRISC] [PATCH v3 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT
` [OpenRISC] [PATCH v3 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing
` [OpenRISC] [PATCH v3 13/13] openrisc: add tick timer multi-core sync logic
[OpenRISC] OpenRISC Architecture 1.2
2017-10-23 20:34 UTC (2+ messages)
[OpenRISC] [PATCH v2] openrisc: dts: or1ksim: Add stdout-path
2017-10-22 2:23 UTC
[OpenRISC] [PATCH v6 6/6] sim: testsuite: add testsuite for or1k sim
2017-10-18 20:54 UTC (3+ messages)
[OpenRISC] [PATCH v6 4/6] sim: or1k: add cgen generated files
2017-10-18 20:38 UTC (2+ messages)
[OpenRISC] [PATCH v6 5/6] sim: or1k: add autoconf generated files
2017-10-18 20:19 UTC
[OpenRISC] [PATCH v6 3/6] sim: or1k: add or1k target to sim
2017-10-18 20:15 UTC
[OpenRISC] [PATCH v6 2/6] sim: cgen: add MUL2OFSI and MUL1OFSI functions (needed for OR1K l.mul[u])
2017-10-18 20:09 UTC
[OpenRISC] [PATCH v6 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])
2017-10-18 20:08 UTC
[OpenRISC] [PATCH v6 0/6] sim port for OpenRISC
2017-10-16 18:04 UTC
[OpenRISC] [linux-litex] Linux early_printk on Arty!
2017-10-14 1:39 UTC
[OpenRISC] [PATCH v2 0/5] OpenRISC SMP Support
2017-10-13 14:31 UTC (8+ messages)
` [OpenRISC] [PATCH v2 1/5] openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC)
` [OpenRISC] [PATCH v2 2/5] target/openrisc: Make coreid and numcores variable
` [OpenRISC] [PATCH v2 3/5] openrisc/cputimer: Perparation for Multicore
` [OpenRISC] [PATCH v2 4/5] openrisc: Initial SMP support
` [OpenRISC] [PATCH v2 5/5] openrisc: Only kick cpu on timeout, not on update
[OpenRISC] [PATCH v6 0/6] sim port for OpenRISC
2017-10-13 12:46 UTC (8+ messages)
` [OpenRISC] [PATCH v6 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])
` [OpenRISC] [PATCH v6 2/6] sim: cgen: add MUL2OFSI and MUL1OFSI functions (needed for OR1K l.mul[u])
` [OpenRISC] [PATCH v6 3/6] sim: or1k: add or1k target to sim
` [OpenRISC] [PATCH v6 4/6] sim: or1k: add cgen generated files
` [OpenRISC] [PATCH v6 5/6] sim: or1k: add autoconf "
` [OpenRISC] [PATCH v6 6/6] sim: testsuite: add testsuite for or1k sim
[OpenRISC] [PATCH 0/5] OpenRISC SMP Support
2017-10-12 21:28 UTC (12+ messages)
` [OpenRISC] [PATCH 1/5] openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC)
` [OpenRISC] [Qemu-devel] "
` [OpenRISC] [PATCH 2/5] target/openrisc: Make coreid and numcores configurable in state
` [OpenRISC] [Qemu-devel] "
` [OpenRISC] [PATCH 3/5] openrisc/cputimer: Perparation for Multicore
` [OpenRISC] [Qemu-devel] "
` [OpenRISC] [PATCH 4/5] openrisc: Initial SMP support
` [OpenRISC] [Qemu-devel] "
` [OpenRISC] [PATCH 5/5] openrisc: Only kick cpu on timeout, not on update
` [OpenRISC] [Qemu-devel] "
[OpenRISC] [PATCH v5 3/6] sim: or1k: add or1k target to sim
2017-10-10 23:03 UTC (2+ messages)
[OpenRISC] [PATCH v5 2/6] sim: cgen: add MUL2OFSI and MUL1OFSI macros (needed for OR1K l.mul[u])
2017-10-09 17:05 UTC
[OpenRISC] [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])
2017-10-09 17:01 UTC
[OpenRISC] [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])
2017-10-09 17:00 UTC
[OpenRISC] [PATCH v5 0/6] sim port for OpenRISC
2017-10-09 16:55 UTC
[OpenRISC] [PATCH v5 0/6] sim port for OpenRISC
2017-10-09 13:33 UTC (17+ messages)
` [OpenRISC] [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])
` [OpenRISC] [PATCH v5 2/6] sim: cgen: add MUL2OFSI and MUL1OFSI macros (needed for OR1K l.mul[u])
` [OpenRISC] [PATCH v5 3/6] sim: or1k: add or1k target to sim
` [OpenRISC] [PATCH v5 4/6] sim: or1k: add cgen generated files
` [OpenRISC] [PATCH v5 5/6] sim: or1k: add autoconf "
` [OpenRISC] [PATCH v5 6/6] sim: testsuite: add testsuite for or1k sim
[OpenRISC] OpenRISC Specification updates for Multicore
2017-10-07 15:08 UTC (3+ messages)
[OpenRISC] [PATCH] openrisc: dts: or1ksim: Add stdout-path
2017-09-20 14:04 UTC (3+ messages)
[OpenRISC] [PATCH] MAINTAINERS: Add OpenRISC pic maintainer
2017-09-19 14:01 UTC
[OpenRISC] [PATCH v2 00/14] OpenRISC SMP Support
2017-09-19 12:14 UTC (24+ messages)
` [OpenRISC] [PATCH v2 01/14] openrisc: use shadow registers to save regs on exception
` [OpenRISC] [PATCH v2 02/14] openrisc: define CPU_BIG_ENDIAN as true
` [OpenRISC] [PATCH v2 03/14] openrisc: add 1 and 2 byte cmpxchg support
` [OpenRISC] [PATCH v2 04/14] openrisc: use qspinlocks and qrwlocks
` [OpenRISC] [PATCH v2 05/14] dt-bindings: add openrisc to vendor prefixes list
` [OpenRISC] [PATCH v2 06/14] irqchip: add initial support for ompic
` [OpenRISC] [PATCH v2 07/14] openrisc: initial SMP support
` [OpenRISC] [PATCH v2 08/14] openrisc: fix initial preempt state for secondary cpu tasks
` [OpenRISC] [PATCH v2 09/14] openrisc: sleep instead of spin on secondary wait
` [OpenRISC] [PATCH v2 10/14] openrisc: add cacheflush support to fix icache aliasing
` [OpenRISC] [PATCH v2 11/14] openrisc: add simple_smp dts and defconfig for simulators
` [OpenRISC] [PATCH v2 12/14] openrisc: support framepointers and STACKTRACE_SUPPORT
` [OpenRISC] [PATCH v2 13/14] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing
` [OpenRISC] [PATCH v2 14/14] openrisc: add tick timer multicore sync logic
[OpenRISC] [PATCH 00/13] OpenRISC SMP Support
2017-09-12 22:15 UTC (34+ messages)
` [OpenRISC] [PATCH 01/13] openrisc: use shadow registers to save regs on exception
` [OpenRISC] [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true
` [OpenRISC] [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support
` [OpenRISC] [PATCH 04/13] openrisc: use qspinlocks and qrwlocks
` [OpenRISC] [PATCH 05/13] irqchip: add initial support for ompic
` [OpenRISC] [PATCH 06/13] openrisc: initial SMP support
` [OpenRISC] [PATCH 07/13] openrisc: fix initial preempt state for secondary cpu tasks
` [OpenRISC] [PATCH 08/13] openrisc: sleep instead of spin on secondary wait
` [OpenRISC] [PATCH 09/13] openrisc: add cacheflush support to fix icache aliasing
` [OpenRISC] [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators
` [OpenRISC] [PATCH 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT
` [OpenRISC] [PATCH 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing
` [OpenRISC] [PATCH 13/13] openrisc: add tick timer multicore sync logic
[OpenRISC] [GIT PULL] OpenRISC patches for 4.14
2017-09-12 21:22 UTC
[OpenRISC] [PATCH] openrisc: add forward declaration for struct vm_area_struct
2017-09-12 11:16 UTC (5+ messages)
[OpenRISC] [PATCH v4 0/5] sim port for OpenRISC
2017-09-05 18:52 UTC (18+ messages)
` [OpenRISC] [PATCH v4 1/5] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])
` [OpenRISC] [PATCH v4 2/5] sim: cgen: add MUL2OFSI and MUL1OFSI macros (needed for OR1K l.mul[u])
` [OpenRISC] [PATCH v4 3/5] sim: or1k: add or1k target to sim
[OpenRISC] difference between mor1Kx and or1200
2017-09-04 11:04 UTC
[OpenRISC] makefile and openrisctoolchain
2017-08-26 14:11 UTC
[OpenRISC] (no subject)
2017-08-24 21:36 UTC
[OpenRISC] (no subject)
2017-08-23 5:36 UTC (2+ messages)
[OpenRISC] ORConf 2017 update
2017-08-15 23:49 UTC
[OpenRISC] OpenRISC Digest, Vol 17, Issue 6
2017-08-05 22:32 UTC
[OpenRISC] OpenRISC Digest, Vol 17, Issue 4
2017-07-19 11:39 UTC (2+ messages)
[OpenRISC] Dev Digest, Vol 14, Issue 5
2017-07-19 8:47 UTC (3+ messages)
[OpenRISC] OpenRISC Digest, Vol 17, Issue 3
2017-07-18 10:31 UTC
[OpenRISC] [Librecores Developers] OpenRISC or1200
2017-07-17 21:45 UTC
[OpenRISC] OR1200
2017-07-15 11:55 UTC
[OpenRISC] [PATCH] irqchip: or1k-pic: Fix interrupt system
2017-06-30 13:45 UTC (3+ messages)
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