From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 20/28] target/arm: Let vfp_access_check() handle late NOCP checks
Date: Tue, 15 Jun 2021 16:43:57 +0100 [thread overview]
Message-ID: <20210615154405.21399-21-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org>
In commit a3494d4671797c we reworked the M-profile handling of its
checks for when the NOCP exception should be raised because the FPU
is disabled, so that (in line with the architecture) the NOCP check
is done early over a large range of the encoding space, and takes
precedence over UNDEF exceptions. As part of this, we removed the
code from full_vfp_access_check() which raised an exception there for
M-profile with the FPU disabled, because it was no longer reachable.
For MVE, some instructions which are outside the "coprocessor space"
region of the encoding space must nonetheless do "is the FPU enabled"
checks and possibly raise a NOCP exception. (In particular this
covers the MVE-specific low-overhead branch insns LCTP, DLSTP and
WLSTP.) To support these insns, reinstate the code in
full_vfp_access_check(), so that their trans functions can call
vfp_access_check() and get the correct behaviour.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614151007.4545-6-peter.maydell@linaro.org
---
target/arm/translate-vfp.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
index 2e12c694edc..01e26a246d6 100644
--- a/target/arm/translate-vfp.c
+++ b/target/arm/translate-vfp.c
@@ -143,11 +143,21 @@ static void gen_preserve_fp_state(DisasContext *s)
static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
{
if (s->fp_excp_el) {
- /* M-profile handled this earlier, in disas_m_nocp() */
- assert (!arm_dc_feature(s, ARM_FEATURE_M));
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
- syn_fp_access_trap(1, 0xe, false),
- s->fp_excp_el);
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
+ /*
+ * M-profile mostly catches the "FPU disabled" case early, in
+ * disas_m_nocp(), but a few insns (eg LCTP, WLSTP, DLSTP)
+ * which do coprocessor-checks are outside the large ranges of
+ * the encoding space handled by the patterns in m-nocp.decode,
+ * and for them we may need to raise NOCP here.
+ */
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
+ syn_uncategorized(), s->fp_excp_el);
+ } else {
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+ syn_fp_access_trap(1, 0xe, false),
+ s->fp_excp_el);
+ }
return false;
}
--
2.20.1
next prev parent reply other threads:[~2021-06-15 15:58 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-15 15:43 [PULL 00/28] target-arm queue Peter Maydell
2021-06-15 15:43 ` [PULL 01/28] hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes Peter Maydell
2021-06-15 15:43 ` [PULL 02/28] target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16 Peter Maydell
2021-06-15 15:43 ` [PULL 03/28] target/arm: Remove fprintf from disas_simd_mod_imm Peter Maydell
2021-06-15 15:43 ` [PULL 04/28] target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16 Peter Maydell
2021-06-15 15:43 ` [PULL 05/28] hw: virt: consider hw_compat_6_0 Peter Maydell
2021-06-15 15:43 ` [PULL 06/28] hw/arm: add quanta-gbs-bmc machine Peter Maydell
2021-06-15 15:43 ` [PULL 07/28] hw/arm: quanta-gbs-bmc add i2c comments Peter Maydell
2021-06-15 15:43 ` [PULL 08/28] hw/intc/armv7m_nvic: Remove stale comment Peter Maydell
2021-06-15 15:43 ` [PULL 09/28] hw/acpi: Provide stub version of acpi_ghes_record_errors() Peter Maydell
2021-06-15 15:43 ` [PULL 10/28] hw/acpi: Provide function acpi_ghes_present() Peter Maydell
2021-06-15 15:43 ` [PULL 11/28] target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors Peter Maydell
2021-06-15 15:43 ` [PULL 12/28] target/arm: Fix mte page crossing test Peter Maydell
2021-06-15 15:43 ` [PULL 13/28] hw/arm: gsj add i2c comments Peter Maydell
2021-06-15 15:43 ` [PULL 14/28] hw/arm: gsj add pca9548 Peter Maydell
2021-06-15 15:43 ` [PULL 15/28] hw/arm: quanta-q71l add pca954x muxes Peter Maydell
2021-06-15 15:43 ` [PULL 16/28] target/arm: Provide and use H8 and H1_8 macros Peter Maydell
2021-06-15 15:43 ` [PULL 17/28] target/arm: Enable FPSCR.QC bit for MVE Peter Maydell
2021-06-15 15:43 ` [PULL 18/28] target/arm: Handle VPR semantics in existing code Peter Maydell
2021-06-15 15:43 ` [PULL 19/28] target/arm: Add handling for PSR.ECI/ICI Peter Maydell
2021-06-15 15:43 ` Peter Maydell [this message]
2021-06-15 15:43 ` [PULL 21/28] target/arm: Implement MVE LCTP Peter Maydell
2021-06-15 15:43 ` [PULL 22/28] target/arm: Implement MVE WLSTP insn Peter Maydell
2021-06-15 15:44 ` [PULL 23/28] target/arm: Implement MVE DLSTP Peter Maydell
2021-06-15 15:44 ` [PULL 24/28] target/arm: Implement MVE LETP insn Peter Maydell
2021-06-15 15:44 ` [PULL 25/28] target/arm: Add framework for MVE decode Peter Maydell
2021-06-15 15:44 ` [PULL 26/28] target/arm: Move expand_pred_b() data to vec_helper.c Peter Maydell
2021-06-15 15:44 ` [PULL 27/28] bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations Peter Maydell
2021-06-15 15:44 ` [PULL 28/28] include/qemu/int128.h: Add function to create Int128 from int64_t Peter Maydell
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